mirror of
https://github.com/RIOT-OS/RIOT.git
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Merge pull request #13714 from aabadie/pr/boards/stm32l4_common_clock
boards/stm32l4: add common clock configuration
This commit is contained in:
Leandro Lanzieri
GitHub
commit
bc8bee4b17
@ -20,56 +20,13 @@
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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#include "l4/cfg_clock_80_1.h"
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#include "cfg_rtt_default.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock system configuration
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* @{
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*/
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/* 0: no external high speed crystal available
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* else: actual crystal frequency [in Hz] */
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#define CLOCK_HSE (0)
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/* 0: no external low speed crystal available,
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* 1: external crystal available (always 32.768kHz) */
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#define CLOCK_LSE (1)
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/* 0: enable MSI only if HSE isn't available
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* 1: always enable MSI (e.g. if USB or RNG is used)*/
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#define CLOCK_MSI_ENABLE (1)
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/* 0: disable Hardware auto calibration with LSE
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* 1: enable Hardware auto calibration with LSE (PLL-mode)*/
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#define CLOCK_MSI_LSE_PLL (1)
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/* give the target core clock (HCLK) frequency [in Hz], maximum: 80MHz */
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#define CLOCK_CORECLOCK (80000000U)
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/* PLL configuration: make sure your values are legit!
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*
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* compute by: CORECLOCK = (((PLL_IN / M) * N) / R)
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* with:
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* PLL_IN: input clock, HSE or MSI @ 48MHz
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* M: pre-divider, allowed range: [1:8]
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* N: multiplier, allowed range: [8:86]
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* R: post-divider, allowed range: [2,4,6,8]
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*
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* Also the following constraints need to be met:
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* (PLL_IN / M) -> [4MHz:16MHz]
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* (PLL_IN / M) * N -> [64MHz:344MHz]
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* CORECLOCK -> 80MHz MAX!
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*/
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#define CLOCK_PLL_M (6)
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#define CLOCK_PLL_N (20)
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#define CLOCK_PLL_R (2)
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/* peripheral clock setup */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
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/** @} */
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/**
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* @name DMA streams configuration
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* @{
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85
boards/common/stm32/include/l4/cfg_clock_80_1.h
Normal file
85
boards/common/stm32/include/l4/cfg_clock_80_1.h
Normal file
@ -0,0 +1,85 @@
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/*
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* Copyright (C) 2017 Freie Universität Berlin
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* 2019 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_common_stm32
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* @{
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*
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* @file
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* @brief Configure STM32L4 clock using 80MHz core clock and LSE (32.768kHz)
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*/
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#ifndef L4_CFG_CLOCK_80_1_H
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#define L4_CFG_CLOCK_80_1_H
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock system configuration
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* @{
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*/
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/* 0: no external high speed crystal available
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* else: actual crystal frequency [in Hz] */
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#define CLOCK_HSE (0)
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/* 0: no external low speed crystal available,
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* 1: external crystal available (always 32.768kHz)
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*/
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#define CLOCK_LSE (1)
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/* 0: enable MSI only if HSE isn't available
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* 1: always enable MSI (e.g. if USB or RNG is used)*/
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#define CLOCK_MSI_ENABLE (1)
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/* 0: disable Hardware auto calibration with LSE
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* 1: enable Hardware auto calibration with LSE (PLL-mode)
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* LSE is mandatory for MSI/LSE-trimming to work */
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#define CLOCK_MSI_LSE_PLL (1)
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/* give the target core clock (HCLK) frequency [in Hz], maximum: 80MHz */
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#define CLOCK_CORECLOCK (80000000U)
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/* PLL configuration: make sure your values are legit!
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*
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* compute by: CORECLOCK = (((PLL_IN / M) * N) / R)
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* with:
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* PLL_IN: input clock, HSE or MSI @ 48MHz
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* M: pre-divider, allowed range: [1:8]
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* N: multiplier, allowed range: [8:86]
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* R: post-divider, allowed range: [2,4,6,8]
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*
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* Also the following constraints need to be met:
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* (PLL_IN / M) -> [4MHz:16MHz]
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* (PLL_IN / M) * N -> [64MHz:344MHz]
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* CORECLOCK -> 80MHz MAX!
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*/
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#define CLOCK_PLL_M (6)
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#define CLOCK_PLL_N (20)
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#define CLOCK_PLL_R (2)
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/* peripheral clock setup */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* L4_CFG_CLOCK_80_1_H */
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/** @} */
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@ -24,6 +24,7 @@
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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#include "l4/cfg_clock_80_1.h"
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#include "cfg_i2c1_pb6_pb7.h"
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#include "cfg_timer_tim2.h"
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#include "cfg_rtt_default.h"
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@ -33,50 +34,6 @@
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extern "C" {
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#endif
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/**
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* @name Clock system configuration
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* @{
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*/
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/* 0: no external high speed crystal available
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* else: actual crystal frequency [in Hz] */
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#define CLOCK_HSE (0)
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/* 0: no external low speed crystal available,
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* 1: external crystal available (always 32.768kHz) */
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#define CLOCK_LSE (1)
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/* 0: enable MSI only if HSE isn't available
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* 1: always enable MSI (e.g. if USB or RNG is used)*/
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#define CLOCK_MSI_ENABLE (1)
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/* 0: disable Hardware auto calibration with LSE
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* 1: enable Hardware auto calibration with LSE (PLL-mode)*/
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#define CLOCK_MSI_LSE_PLL (1)
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/* give the target core clock (HCLK) frequency [in Hz], maximum: 80MHz */
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#define CLOCK_CORECLOCK (80000000U)
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/* PLL configuration: make sure your values are legit!
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*
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* compute by: CORECLOCK = (((PLL_IN / M) * N) / R)
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* with:
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* PLL_IN: input clock, HSE or MSI @ 48MHz
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* M: pre-divider, allowed range: [1:8]
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* N: multiplier, allowed range: [8:86]
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* R: post-divider, allowed range: [2,4,6,8]
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*
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* Also the following constraints need to be met:
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* (PLL_IN / M) -> [4MHz:16MHz]
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* (PLL_IN / M) * N -> [64MHz:344MHz]
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* CORECLOCK -> 80MHz MAX!
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*/
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#define CLOCK_PLL_M (6)
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#define CLOCK_PLL_N (20)
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#define CLOCK_PLL_R (2)
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/* peripheral clock setup */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
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/** @} */
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/**
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* @name UART configuration
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* @{
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@ -22,6 +22,7 @@
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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#include "l4/cfg_clock_80_1.h"
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#include "cfg_i2c1_pb6_pb7.h"
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#include "cfg_rtt_default.h"
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#include "cfg_timer_tim2.h"
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@ -30,50 +31,6 @@
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extern "C" {
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#endif
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/**
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* @name Clock system configuration
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* @{
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*/
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/* 0: no external high speed crystal available
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* else: actual crystal frequency [in Hz] */
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#define CLOCK_HSE (0)
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/* 0: no external low speed crystal available,
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* 1: external crystal available (always 32.768kHz) */
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#define CLOCK_LSE (1)
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/* 0: enable MSI only if HSE isn't available
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* 1: always enable MSI (e.g. if USB or RNG is used)*/
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#define CLOCK_MSI_ENABLE (1)
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/* 0: disable Hardware auto calibration with LSE
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* 1: enable Hardware auto calibration with LSE (PLL-mode)*/
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#define CLOCK_MSI_LSE_PLL (1)
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/* give the target core clock (HCLK) frequency [in Hz], maximum: 80MHz */
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#define CLOCK_CORECLOCK (80000000U)
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/* PLL configuration: make sure your values are legit!
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*
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* compute by: CORECLOCK = (((PLL_IN / M) * N) / R)
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* with:
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* PLL_IN: input clock, HSE or MSI @ 48MHz
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* M: pre-divider, allowed range: [1:8]
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* N: multiplier, allowed range: [8:86]
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* R: post-divider, allowed range: [2,4,6,8]
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*
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* Also the following constraints need to be met:
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* (PLL_IN / M) -> [4MHz:16MHz]
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* (PLL_IN / M) * N -> [64MHz:344MHz]
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* CORECLOCK -> 80MHz MAX!
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*/
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#define CLOCK_PLL_M (6)
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#define CLOCK_PLL_N (20)
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#define CLOCK_PLL_R (2)
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/* peripheral clock setup */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
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/** @} */
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/**
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* @name UART configuration
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* @{
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@ -20,6 +20,7 @@
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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#include "l4/cfg_clock_80_1.h"
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#include "cfg_rtt_default.h"
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#include "cfg_timer_tim2.h"
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@ -27,61 +28,6 @@
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extern "C" {
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#endif
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/**
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* @name Clock system configuration
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* @{
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*/
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/* 0: no external high speed crystal available
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* else: actual crystal frequency [in Hz] */
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#define CLOCK_HSE (0)
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#ifndef CLOCK_LSE
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/* 0: no external low speed crystal available,
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* 1: external crystal available (always 32.768kHz)
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*/
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#define CLOCK_LSE (1)
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#endif
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/* 0: enable MSI only if HSE isn't available
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* 1: always enable MSI (e.g. if USB or RNG is used)*/
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#define CLOCK_MSI_ENABLE (1)
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#ifndef CLOCK_MSI_LSE_PLL
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/* 0: disable Hardware auto calibration with LSE
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* 1: enable Hardware auto calibration with LSE (PLL-mode)
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* Same as with CLOCK_LSE above this defaults to 0 because LSE is
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* mandatory for MSI/LSE-trimming to work */
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#define CLOCK_MSI_LSE_PLL (0)
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#endif
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/* give the target core clock (HCLK) frequency [in Hz], maximum: 80MHz */
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#define CLOCK_CORECLOCK (80000000U)
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/* PLL configuration: make sure your values are legit!
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*
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* compute by: CORECLOCK = (((PLL_IN / M) * N) / R)
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* with:
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* PLL_IN: input clock, HSE or MSI @ 48MHz
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* M: pre-divider, allowed range: [1:8]
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* N: multiplier, allowed range: [8:86]
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* R: post-divider, allowed range: [2,4,6,8]
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*
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* Also the following constraints need to be met:
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* (PLL_IN / M) -> [4MHz:16MHz]
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* (PLL_IN / M) * N -> [64MHz:344MHz]
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* CORECLOCK -> 80MHz MAX!
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*/
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#define CLOCK_PLL_M (6)
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#define CLOCK_PLL_N (20)
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#define CLOCK_PLL_R (2)
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/* peripheral clock setup */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
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/** @} */
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/**
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* @name UART configuration
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* @{
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@ -24,6 +24,7 @@
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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#include "l4/cfg_clock_80_1.h"
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#include "cfg_i2c1_pb8_pb9.h"
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#include "cfg_rtt_default.h"
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@ -31,63 +32,6 @@
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extern "C" {
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#endif
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/**
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* @name Clock system configuration
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* @{
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*/
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/* 0: no external high speed crystal available
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* else: actual crystal frequency [in Hz] */
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#define CLOCK_HSE (0)
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#ifndef CLOCK_LSE
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/* 0: no external low speed crystal available,
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* 1: external crystal available (always 32.768kHz)
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* This defaults to 0 because hardware revision 'MB1136 C-01' of the nucleo-64
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* board disconnects LSE by default. You may safely set this to 1 on revisions
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* newer than 'MB1136 C-01' */
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#define CLOCK_LSE (1)
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#endif
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/* 0: enable MSI only if HSE isn't available
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* 1: always enable MSI (e.g. if USB or RNG is used)*/
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#define CLOCK_MSI_ENABLE (1)
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#ifndef CLOCK_MSI_LSE_PLL
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/* 0: disable Hardware auto calibration with LSE
|
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* 1: enable Hardware auto calibration with LSE (PLL-mode)
|
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* Same as with CLOCK_LSE above this defaults to 0 because LSE is
|
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* mandatory for MSI/LSE-trimming to work */
|
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#define CLOCK_MSI_LSE_PLL (0)
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#endif
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/* give the target core clock (HCLK) frequency [in Hz], maximum: 80MHz */
|
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#define CLOCK_CORECLOCK (80000000U)
|
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/* PLL configuration: make sure your values are legit!
|
||||
*
|
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* compute by: CORECLOCK = (((PLL_IN / M) * N) / R)
|
||||
* with:
|
||||
* PLL_IN: input clock, HSE or MSI @ 48MHz
|
||||
* M: pre-divider, allowed range: [1:8]
|
||||
* N: multiplier, allowed range: [8:86]
|
||||
* R: post-divider, allowed range: [2,4,6,8]
|
||||
*
|
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* Also the following constraints need to be met:
|
||||
* (PLL_IN / M) -> [4MHz:16MHz]
|
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* (PLL_IN / M) * N -> [64MHz:344MHz]
|
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* CORECLOCK -> 80MHz MAX!
|
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*/
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#define CLOCK_PLL_M (6)
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#define CLOCK_PLL_N (20)
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#define CLOCK_PLL_R (2)
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/* peripheral clock setup */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
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/** @} */
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/**
|
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* @name DMA streams configuration
|
||||
* @{
|
||||
|
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@ -20,6 +20,7 @@
|
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#define PERIPH_CONF_H
|
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|
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#include "periph_cpu.h"
|
||||
#include "l4/cfg_clock_80_1.h"
|
||||
#include "cfg_i2c1_pb8_pb9.h"
|
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#include "cfg_rtt_default.h"
|
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|
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@ -27,61 +28,6 @@
|
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extern "C" {
|
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#endif
|
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|
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/**
|
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* @name Clock system configuration
|
||||
* @{
|
||||
*/
|
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/* 0: no external high speed crystal available
|
||||
* else: actual crystal frequency [in Hz] */
|
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#define CLOCK_HSE (0)
|
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|
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#ifndef CLOCK_LSE
|
||||
/* 0: no external low speed crystal available,
|
||||
* 1: external crystal available (always 32.768kHz) */
|
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#define CLOCK_LSE (1)
|
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#endif
|
||||
|
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/* 0: enable MSI only if HSE isn't available
|
||||
* 1: always enable MSI (e.g. if USB or RNG is used)*/
|
||||
#define CLOCK_MSI_ENABLE (1)
|
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|
||||
#ifndef CLOCK_MSI_LSE_PLL
|
||||
/* 0: disable Hardware auto calibration with LSE
|
||||
* 1: enable Hardware auto calibration with LSE (PLL-mode)
|
||||
* Same as with CLOCK_LSE above this defaults to 0 because LSE is
|
||||
* mandatory for MSI/LSE-trimming to work */
|
||||
#define CLOCK_MSI_LSE_PLL (0)
|
||||
#endif
|
||||
|
||||
/* give the target core clock (HCLK) frequency [in Hz], maximum: 80MHz */
|
||||
#define CLOCK_CORECLOCK (80000000U)
|
||||
/* PLL configuration: make sure your values are legit!
|
||||
*
|
||||
* compute by: CORECLOCK = (((PLL_IN / M) * N) / R)
|
||||
* with:
|
||||
* PLL_IN: input clock, HSE or MSI @ 48MHz
|
||||
* M: pre-divider, allowed range: [1:8]
|
||||
* N: multiplier, allowed range: [8:86]
|
||||
* R: post-divider, allowed range: [2,4,6,8]
|
||||
*
|
||||
* Also the following constraints need to be met:
|
||||
* (PLL_IN / M) -> [4MHz:16MHz]
|
||||
* (PLL_IN / M) * N -> [64MHz:344MHz]
|
||||
* CORECLOCK -> 80MHz MAX!
|
||||
*/
|
||||
#define CLOCK_PLL_M (6)
|
||||
#define CLOCK_PLL_N (20)
|
||||
#define CLOCK_PLL_R (2)
|
||||
/* peripheral clock setup */
|
||||
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
|
||||
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
|
||||
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4
|
||||
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
|
||||
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2
|
||||
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
|
||||
/** @} */
|
||||
|
||||
|
||||
/**
|
||||
* @name Timer configuration
|
||||
* @{
|
||||
|
||||
@ -20,6 +20,7 @@
|
||||
#define PERIPH_CONF_H
|
||||
|
||||
#include "periph_cpu.h"
|
||||
#include "l4/cfg_clock_80_1.h"
|
||||
#include "cfg_rtt_default.h"
|
||||
#include "cfg_timer_tim2.h"
|
||||
|
||||
@ -27,50 +28,6 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @name Clock system configuration
|
||||
* @{
|
||||
*/
|
||||
/* 0: no external high speed crystal available
|
||||
* else: actual crystal frequency [in Hz] */
|
||||
#define CLOCK_HSE (0)
|
||||
/* 0: no external low speed crystal available,
|
||||
* 1: external crystal available (always 32.768kHz) */
|
||||
#define CLOCK_LSE (1)
|
||||
/* 0: enable MSI only if HSE isn't available
|
||||
* 1: always enable MSI (e.g. if USB or RNG is used)*/
|
||||
#define CLOCK_MSI_ENABLE (1)
|
||||
/* 0: disable Hardware auto calibration with LSE
|
||||
* 1: enable Hardware auto calibration with LSE (PLL-mode)*/
|
||||
#define CLOCK_MSI_LSE_PLL (1)
|
||||
/* give the target core clock (HCLK) frequency [in Hz], maximum: 80MHz */
|
||||
#define CLOCK_CORECLOCK (80000000U)
|
||||
/* PLL configuration: make sure your values are legit!
|
||||
*
|
||||
* compute by: CORECLOCK = (((PLL_IN / M) * N) / R)
|
||||
* with:
|
||||
* PLL_IN: input clock, HSE or MSI @ 48MHz
|
||||
* M: pre-divider, allowed range: [1:8]
|
||||
* N: multiplier, allowed range: [8:86]
|
||||
* R: post-divider, allowed range: [2,4,6,8]
|
||||
*
|
||||
* Also the following constraints need to be met:
|
||||
* (PLL_IN / M) -> [4MHz:16MHz]
|
||||
* (PLL_IN / M) * N -> [64MHz:344MHz]
|
||||
* CORECLOCK -> 80MHz MAX!
|
||||
*/
|
||||
#define CLOCK_PLL_M (6)
|
||||
#define CLOCK_PLL_N (20)
|
||||
#define CLOCK_PLL_R (2)
|
||||
/* peripheral clock setup */
|
||||
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
|
||||
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
|
||||
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4
|
||||
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
|
||||
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2
|
||||
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name UART configuration
|
||||
* @{
|
||||
|
||||
@ -20,56 +20,13 @@
|
||||
#define PERIPH_CONF_H
|
||||
|
||||
#include "periph_cpu.h"
|
||||
#include "l4/cfg_clock_80_1.h"
|
||||
#include "cfg_rtt_default.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @name Clock system configuration
|
||||
* @{
|
||||
*/
|
||||
/* 0: no external high speed crystal available
|
||||
* else: actual crystal frequency [in Hz] */
|
||||
#define CLOCK_HSE (0)
|
||||
/* 0: no external low speed crystal available,
|
||||
* 1: external crystal available (always 32.768kHz) */
|
||||
#define CLOCK_LSE (1)
|
||||
/* 0: enable MSI only if HSE isn't available
|
||||
* 1: always enable MSI (e.g. if USB or RNG is used)*/
|
||||
#define CLOCK_MSI_ENABLE (1)
|
||||
/* 0: disable Hardware auto calibration with LSE
|
||||
* 1: enable Hardware auto calibration with LSE (PLL-mode)*/
|
||||
#define CLOCK_MSI_LSE_PLL (1)
|
||||
/* give the target core clock (HCLK) frequency [in Hz], maximum: 80MHz */
|
||||
#define CLOCK_CORECLOCK (80000000U)
|
||||
/* PLL configuration: make sure your values are legit!
|
||||
*
|
||||
* compute by: CORECLOCK = (((PLL_IN / M) * N) / R)
|
||||
* with:
|
||||
* PLL_IN: input clock, HSE or MSI @ 48MHz
|
||||
* M: pre-divider, allowed range: [1:8]
|
||||
* N: multiplier, allowed range: [8:86]
|
||||
* R: post-divider, allowed range: [2,4,6,8]
|
||||
*
|
||||
* Also the following constraints need to be met:
|
||||
* (PLL_IN / M) -> [4MHz:16MHz]
|
||||
* (PLL_IN / M) * N -> [64MHz:344MHz]
|
||||
* CORECLOCK -> 80MHz MAX!
|
||||
*/
|
||||
#define CLOCK_PLL_M (6)
|
||||
#define CLOCK_PLL_N (20)
|
||||
#define CLOCK_PLL_R (2)
|
||||
/* peripheral clock setup */
|
||||
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
|
||||
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
|
||||
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4
|
||||
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
|
||||
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2
|
||||
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Timer configuration
|
||||
* @{
|
||||
|
||||
Loading…
Reference in New Issue
Block a user