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cpu/stm32f0: some minor fixes to GPIO driver

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- fixed indention on some places
- s/gpio_config/isr_ctx/
- use BRR reg for clearing pin
This commit is contained in:
Hauke Petersen 2016-02-13 13:02:32 +01:00
parent a64a4df72e
commit b97afdc1b1
3 changed files with 19 additions and 26 deletions
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9
cpu/stm32f0/include/periph_cpu.h
View File

@ -42,14 +42,13 @@ typedef uint32_t gpio_t;
/**
* @brief Define a CPU specific GPIO pin generator macro
*/
#define GPIO_PIN(x, y) ((GPIOA_BASE + (x << 10)) | y)
#define GPIO_PIN(x, y) ((GPIOA_BASE + (x << 10)) | y)
/**
* @brief Override flank configuration values
* @{
*/
#define HAVE_GPIO_FLANK_T\
#define HAVE_GPIO_FLANK_T
typedef enum {
GPIO_RISING = 1, /**< emit interrupt on rising flank */
GPIO_FALLING = 2, /**< emit interrupt on falling flank */
@ -76,10 +75,6 @@ typedef enum {
GPIO_AF1, /**< use alternate function 1 */
GPIO_AF2, /**< use alternate function 2 */
GPIO_AF3, /**< use alternate function 3 */
GPIO_AF4, /**< use alternate function 4 */
GPIO_AF5, /**< use alternate function 5 */
GPIO_AF6, /**< use alternate function 6 */
GPIO_AF7, /**< use alternate function 7 */
} gpio_af_t;
/**

30
cpu/stm32f0/periph/gpio.c
View File

@ -32,7 +32,7 @@
/**
* @brief Allocate memory for one callback and argument per EXTI channel
*/
static gpio_isr_ctx_t gpio_config[EXTI_NUMOF];
static gpio_isr_ctx_t isr_ctx[EXTI_NUMOF];
/**
* @brief Extract the port base address from the given pin identifier
@ -91,8 +91,8 @@ int gpio_init_int(gpio_t pin, gpio_pp_t pullup, gpio_flank_t flank, gpio_cb_t cb
int port_num = _port_num(pin);
/* set callback */
gpio_config[pin_num].cb = cb;
gpio_config[pin_num].arg = arg;
isr_ctx[pin_num].cb = cb;
isr_ctx[pin_num].arg = arg;
/* enable clock of the SYSCFG module for EXTI configuration */
RCC->APB2ENR |= RCC_APB2ENR_SYSCFGCOMPEN;
@ -152,13 +152,11 @@ void gpio_irq_disable(gpio_t pin)
int gpio_read(gpio_t pin)
{
GPIO_TypeDef *port = _port(pin);
uint32_t pin_num = _pin_num(pin);
if (port->MODER & (1 << (pin_num * 2))) { /* if configured as output */
return port->ODR & (1 << pin_num); /* read output data reg */
} else {
return port->IDR & (1 << pin_num); /* else read input data reg */
if (_port(pin)->MODER & (0x3 << (_pin_num(pin) * 2))) {
return _port(pin)->ODR & (1 << _pin_num(pin));
}
else {
return _port(pin)->IDR & (1 << _pin_num(pin));
}
}
@ -169,24 +167,24 @@ void gpio_set(gpio_t pin)
void gpio_clear(gpio_t pin)
{
_port(pin)->BSRR = ((1 << _pin_num(pin)) << 16);
_port(pin)->BRR = (1 << _pin_num(pin));
}
void gpio_toggle(gpio_t pin)
{
if (gpio_read(pin)) {
_port(pin)->BSRR = ((1 << _pin_num(pin))<< 16);
_port(pin)->BRR = (1 << _pin_num(pin));
} else {
_port(pin)->BSRR = (1 << _pin_num(pin));
_port(pin)->BSRR = (1 << _pin_num(pin));
}
}
void gpio_write(gpio_t pin, int value)
{
if (value) {
_port(pin)->BSRR = (1 << _pin_num(pin));
_port(pin)->BSRR = (1 << _pin_num(pin));
} else {
_port(pin)->BSRR = ((1 << _pin_num(pin)) << 16);
_port(pin)->BRR = (1 << _pin_num(pin));
}
}
@ -195,7 +193,7 @@ void isr_exti(void)
for (size_t i = 0; i < EXTI_NUMOF; i++) {
if (EXTI->PR & (1 << i)) {
EXTI->PR = (1 << i); /* clear by writing a 1 */
gpio_config[i].cb(gpio_config[i].arg);
isr_ctx[i].cb(isr_ctx[i].arg);
}
}
if (sched_context_switch_request) {

6
cpu/stm32f0/vectors.c
View File

@ -93,9 +93,9 @@ ISR_VECTORS const void *interrupt_vector[] = {
(void*) isr_rtc, /* real time clock */
(void*) isr_flash, /* flash memory controller */
(void*) isr_rcc, /* reset and clock control */
(void*) isr_exti, /* external interrupt lines 0 and 1 */
(void*) isr_exti, /* external interrupt lines 2 and 3 */
(void*) isr_exti, /* external interrupt lines 4 and 15 */
(void*) isr_exti, /* external interrupt lines 0 and 1 */
(void*) isr_exti, /* external interrupt lines 2 and 3 */
(void*) isr_exti, /* external interrupt lines 4 to 15 */
(void*) isr_ts, /* touch sensing input*/
(void*) isr_dma1_ch1, /* direct memory access controller 1, channel 1*/
(void*) isr_dma1_ch2_3, /* direct memory access controller 1, channel 2 and 3*/