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cpu/esp32: define RAM_START_ADDR and RAM_LEN

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This commit is contained in:
Gunar Schorcht 2023-06-25 17:32:35 +02:00
parent 655211129e
commit b707235592
2 changed files with 32 additions and 1 deletions
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31
cpu/esp32/Makefile.include
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@ -28,6 +28,37 @@ else
$(error Unkwnown ESP32x SoC variant (family))
endif
# RAM configuration
ifeq (esp32,$(CPU_FAM))
ifneq (,$(filter esp_idf_ble,$(USEMODULE)))
# If BT is used, the first 0xdb5c bytes (ca. 55 kbytes) of RAM are shared
# with the BT controller. Usable RAM region the starts at 0x3FFBDB5C.
# We reduce the usable size by 55 kByte.
RAM_LEN = 120K
RAM_START_ADDR = 0x3FFBE000
else
RAM_LEN = 176K
RAM_START_ADDR = 0x3FFB0000
endif
else ifeq (esp32s2,$(CPU_FAM))
# The ESP32-S2 configuration in RIOT uses a data cache size and an
# instruction cache size of 8 kByte each. This means that the usable RAM
# starts at 0x3FFB0000 + 0x4000 and the size is reduced by 0x4000
RAM_LEN = 176K
RAM_START_ADDR = 0x3FFB4000
else ifeq (esp32s3,$(CPU_FAM))
RAM_LEN = 264K
RAM_START_ADDR = 0x3FC88000
else ifeq (esp32c3,$(CPU_FAM))
# Note: The address space is shared between the data and the instruction bus.
# Therefore, a part at the beginning of the RAM is not usable since it is
# used as instruction cache via the instruction bus.
RAM_LEN = 320K
RAM_START_ADDR = 0x3FC88000
else
$(error Unkwnown ESP32x SoC variant (family))
endif
ifneq (,$(filter periph_flashpage,$(USEMODULE)))
ifneq (,$(CONFIG_ESP_FLASHPAGE_CAPACITY_64K))
FLASHFILE_POS = 0x20000

2
cpu/esp32/include/sdkconfig_esp32.h
View File

@ -188,7 +188,7 @@ extern "C" {
#define CONFIG_BTDM_CTRL_PCM_POLAR_EFF 0
#define CONFIG_BTDM_CTRL_PINNED_TO_CORE_0 1
#define CONFIG_BTDM_CTRL_PINNED_TO_CORE 0
#define CONFIG_BTDM_RESERVE_DRAM 0xdb5c
#define CONFIG_BTDM_RESERVE_DRAM 0xe000 /* at least 0xdb5c, we use 56 kB */
#define CONFIG_BTDM_SCAN_DUPL_CACHE_SIZE 200
#define CONFIG_BTDM_SCAN_DUPL_TYPE_DEVICE 1
#define CONFIG_BTDM_SCAN_DUPL_TYPE 0