diff --git a/cpu/stm32/Makefile.cmsis b/cpu/stm32/Makefile.cmsis
index 153539da7b..b678e06a17 100644
--- a/cpu/stm32/Makefile.cmsis
+++ b/cpu/stm32/Makefile.cmsis
@@ -3,6 +3,8 @@ PKG_NAME=stm32cmsis
 # The package URL depends on the family of the target STM32
 PKG_URL=https://github.com/STMicroelectronics/cmsis_device_$(CPU_FAM)
 
+# v1.1.0
+PKG_VERSION_c0=7e32bf9d8117ee4c8f6a1d138b814fc24bf4c906
 # v2.3.7
 PKG_VERSION_f0=3973d99a89ac5fdf1f2593abc29a73d2981ce94a
 # v4.3.4
diff --git a/cpu/stm32/Makefile.features b/cpu/stm32/Makefile.features
index 4fb6ab240b..1ff35af515 100644
--- a/cpu/stm32/Makefile.features
+++ b/cpu/stm32/Makefile.features
@@ -17,7 +17,7 @@ FEATURES_PROVIDED += periph_gpio_ll_irq
 FEATURES_PROVIDED += periph_gpio_ll_irq_level_triggered_high
 FEATURES_PROVIDED += periph_gpio_ll_irq_level_triggered_low
 
-ifneq (,$(filter $(CPU_FAM),f0 f1 f3 g0 g4 l0 l1 l4 l5 u5 wb wl))
+ifneq (,$(filter $(CPU_FAM),c0 f0 f1 f3 g0 g4 l0 l1 l4 l5 u5 wb wl))
   FEATURES_PROVIDED += periph_flashpage
   FEATURES_PROVIDED += periph_flashpage_in_address_space
   FEATURES_PROVIDED += periph_flashpage_pagewise
diff --git a/cpu/stm32/cpu_common.c b/cpu/stm32/cpu_common.c
index 6dbfae8e2a..a3eddd5826 100644
--- a/cpu/stm32/cpu_common.c
+++ b/cpu/stm32/cpu_common.c
@@ -39,7 +39,7 @@ static const uint8_t apbmul[] = {
 #if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
     defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32G4) || \
     defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
-    defined(CPU_FAM_STM32WL)
+    defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32C0)
     [APB12] = 2,
 #endif
 #else
@@ -47,7 +47,7 @@ static const uint8_t apbmul[] = {
 #if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
     defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32G4) || \
     defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
-    defined(CPU_FAM_STM32WL)
+    defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32C0)
     [APB12] = 1,
 #endif
 #endif
@@ -83,7 +83,7 @@ void periph_clk_en(bus_t bus, uint32_t mask)
     defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32L5) || \
     defined(CPU_FAM_STM32U5) || defined(CPU_FAM_STM32WL)
             RCC->APB1ENR1 |= mask;
-#elif defined(CPU_FAM_STM32G0)
+#elif defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32C0)
             RCC->APBENR1 |= mask;
 #elif defined(CPU_FAM_STM32MP1)
             RCC->MC_APB1ENSETR |= mask;
@@ -91,7 +91,7 @@ void periph_clk_en(bus_t bus, uint32_t mask)
             RCC->APB1ENR |= mask;
 #endif
             break;
-#if !defined(CPU_FAM_STM32G0)
+#if !defined(CPU_FAM_STM32G0) && !defined(CPU_FAM_STM32C0)
         case APB2:
 #if defined(CPU_FAM_STM32MP1)
             RCC->MC_APB2ENSETR |= mask;
@@ -111,12 +111,13 @@ void periph_clk_en(bus_t bus, uint32_t mask)
         case APB12:
             RCC->APB1ENR2 |= mask;
             break;
-#elif defined(CPU_FAM_STM32G0)
+#elif defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32C0)
         case APB12:
             RCC->APBENR2 |= mask;
             break;
 #endif
-#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32G0)
+#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32G0) || \
+    defined(CPU_FAM_STM32C0)
         case AHB:
             RCC->AHBENR |= mask;
             break;
@@ -176,7 +177,7 @@ void periph_clk_dis(bus_t bus, uint32_t mask)
     defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32L5) || \
     defined(CPU_FAM_STM32U5) || defined(CPU_FAM_STM32WL)
             RCC->APB1ENR1 &= ~(mask);
-#elif defined(CPU_FAM_STM32G0)
+#elif defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32C0)
             RCC->APBENR1 &= ~(mask);
 #elif defined(CPU_FAM_STM32MP1)
             /* Write 1 to clear */
@@ -185,7 +186,7 @@ void periph_clk_dis(bus_t bus, uint32_t mask)
             RCC->APB1ENR &= ~(mask);
 #endif
             break;
-#if !defined(CPU_FAM_STM32G0)
+#if !defined(CPU_FAM_STM32G0) && !defined(CPU_FAM_STM32C0)
         case APB2:
 #if defined(CPU_FAM_STM32MP1)
             RCC->MC_APB2ENCLRR |= mask;
@@ -205,7 +206,7 @@ void periph_clk_dis(bus_t bus, uint32_t mask)
         case APB12:
             RCC->APB1ENR2 &= ~(mask);
             break;
-#elif defined(CPU_FAM_STM32G0)
+#elif defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32C0)
         case APB12:
             RCC->APBENR2 &= ~(mask);
             break;
diff --git a/cpu/stm32/cpu_init.c b/cpu/stm32/cpu_init.c
index 30b1956961..8087f11374 100644
--- a/cpu/stm32/cpu_init.c
+++ b/cpu/stm32/cpu_init.c
@@ -46,7 +46,7 @@
 #if defined (CPU_FAM_STM32L4) || defined (CPU_FAM_STM32G4) || \
     defined(CPU_FAM_STM32L5)
 #define BIT_APB_PWREN       RCC_APB1ENR1_PWREN
-#elif defined (CPU_FAM_STM32G0)
+#elif defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32C0)
 #define BIT_APB_PWREN       RCC_APBENR1_PWREN
 #elif !defined(CPU_FAM_STM32MP1)
 #define BIT_APB_PWREN       RCC_APB1ENR_PWREN
diff --git a/cpu/stm32/include/clk/c0/cfg_clock_default.h b/cpu/stm32/include/clk/c0/cfg_clock_default.h
new file mode 100644
index 0000000000..3118bb2688
--- /dev/null
+++ b/cpu/stm32/include/clk/c0/cfg_clock_default.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2024 BISSELL Homecare, Inc.
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     cpu_stm32
+ * @{
+ *
+ * @file
+ * @brief       Configure STM32C0 clock
+ *
+ * @author      Jason Parker <Jason.Parker@bissell.com>
+ */
+
+#ifndef CLK_C0_CFG_CLOCK_DEFAULT_H
+#define CLK_C0_CFG_CLOCK_DEFAULT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name    C0 clock settings
+ *
+ * @{
+ */
+#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE < MHZ(4) || CONFIG_CLOCK_HSE > MHZ(48))
+#error "HSE clock frequency must be between 4MHz and 48MHz"
+#endif
+
+#ifdef CPU_FAM_STM32C0
+#ifndef CONFIG_CLOCK_HSISYS_DIV
+#define CONFIG_CLOCK_HSISYS_DIV         (1)
+#endif
+#endif
+
+#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
+#define CLOCK_CORECLOCK                 (CONFIG_CLOCK_HSI / CONFIG_CLOCK_HSISYS_DIV)
+
+#elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE)
+#if !IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
+#error "The board doesn't provide an HSE oscillator"
+#endif
+#define CLOCK_CORECLOCK                 (CONFIG_CLOCK_HSE)
+
+#endif
+
+#define CLOCK_AHB                       CLOCK_CORECLOCK  /* max: 64MHz (G0), 170MHZ (G4) */
+
+#ifndef CONFIG_CLOCK_APB1_DIV
+#define CONFIG_CLOCK_APB1_DIV           (1)
+#endif
+#define CLOCK_APB1                      (CLOCK_CORECLOCK / CONFIG_CLOCK_APB1_DIV)  \
+                                        /* max: 64MHz (G0), 170MHZ (G4) */
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CLK_C0_CFG_CLOCK_DEFAULT_H */
+/** @} */
diff --git a/cpu/stm32/include/clk/cfg_clock_common_fx_gx_mp1.h b/cpu/stm32/include/clk/cfg_clock_common_fx_gx_mp1_c0.h
similarity index 80%
rename from cpu/stm32/include/clk/cfg_clock_common_fx_gx_mp1.h
rename to cpu/stm32/include/clk/cfg_clock_common_fx_gx_mp1_c0.h
index f6b2aaf4f2..b9f7fd3958 100644
--- a/cpu/stm32/include/clk/cfg_clock_common_fx_gx_mp1.h
+++ b/cpu/stm32/include/clk/cfg_clock_common_fx_gx_mp1_c0.h
@@ -13,22 +13,22 @@
  * @{
  *
  * @file
- * @brief       Base STM32Fx/Gx/MP1 clock configuration
+ * @brief       Base STM32Fx/Gx/MP1/C0 clock configuration
  *
  * @author      Hauke Petersen <hauke.petersen@fu-berlin.de>
  * @author      Vincent Dupont <vincent@otakeys.com>
  * @author      Alexandre Abadie <alexandre.abadie@inria.fr>
  */
 
-#ifndef CLK_CFG_CLOCK_COMMON_FX_GX_MP1_H
-#define CLK_CFG_CLOCK_COMMON_FX_GX_MP1_H
+#ifndef CLK_CFG_CLOCK_COMMON_FX_GX_MP1_C0_H
+#define CLK_CFG_CLOCK_COMMON_FX_GX_MP1_C0_H
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
 /**
- * @name    Clock common configuration (F0/F1/F2/F3/F4/F7/G0/G4/MP1)
+ * @name    Clock common configuration (F0/F1/F2/F3/F4/F7/G0/G4/MP1/C0)
  * @{
  */
 /* Select the desired system clock source between PLL, HSE or HSI */
@@ -36,8 +36,13 @@ extern "C" {
 #if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
 #define CONFIG_USE_CLOCK_PLL            0
 #else
+#if defined(CPU_FAM_STM32C0)  /* PLL not supported in STM32C0 */
+#define CONFIG_USE_CLOCK_PLL            0
+#define CONFIG_USE_CLOCK_HSI            1
+#else
 #define CONFIG_USE_CLOCK_PLL            1     /* Use PLL by default */
 #endif
+#endif
 #endif /* CONFIG_USE_CLOCK_PLL */
 
 #if IS_ACTIVE(CONFIG_USE_CLOCK_PLL) && \
@@ -57,7 +62,7 @@ extern "C" {
 
 #ifndef CONFIG_CLOCK_HSE
 #if defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32G4) || \
-    defined(CPU_FAM_STM32MP1)
+    defined(CPU_FAM_STM32MP1) || defined(CPU_FAM_STM32C0)
 #define CONFIG_CLOCK_HSE                       MHZ(24)
 #else
 #define CONFIG_CLOCK_HSE                       MHZ(8)
@@ -70,6 +75,8 @@ extern "C" {
 #define CONFIG_CLOCK_HSI                       MHZ(8)
 #elif defined(CPU_FAM_STM32MP1)
 #define CONFIG_CLOCK_HSI                       MHZ(64)
+#elif defined(CPU_FAM_STM32C0)
+#define CONFIG_CLOCK_HSI                       MHZ(48)
 #else
 #define CONFIG_CLOCK_HSI                       MHZ(16)
 #endif
@@ -80,5 +87,5 @@ extern "C" {
 }
 #endif
 
-#endif /* CLK_CFG_CLOCK_COMMON_FX_GX_MP1_H */
+#endif /* CLK_CFG_CLOCK_COMMON_FX_GX_MP1_C0_H */
 /** @} */
diff --git a/cpu/stm32/include/clk/clk_conf.h b/cpu/stm32/include/clk/clk_conf.h
index 57e31b611b..4b093cdd82 100644
--- a/cpu/stm32/include/clk/clk_conf.h
+++ b/cpu/stm32/include/clk/clk_conf.h
@@ -26,8 +26,8 @@
     defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F3) || \
     defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32F7) || \
     defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32G4) || \
-    defined(CPU_FAM_STM32MP1)
-#include "cfg_clock_common_fx_gx_mp1.h"
+    defined(CPU_FAM_STM32MP1) || defined(CPU_FAM_STM32C0)
+#include "cfg_clock_common_fx_gx_mp1_c0.h"
 #else /* CPU_FAM_STM32L0 || CPU_FAM_STM32L1 || CPU_FAM_STM32L4 ||
        * CPU_FAM_STM32L5 || CPU_FAM_STM32U5 || CPU_FAM_STM32WB */
 #include "cfg_clock_common_lx_u5_wx.h"
@@ -41,6 +41,8 @@
 #include "f2f4f7/cfg_clock_default.h"
 #elif defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32G4)
 #include "g0g4/cfg_clock_default.h"
+#elif defined(CPU_FAM_STM32C0)
+#include "c0/cfg_clock_default.h"
 #elif defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
 #include "l0l1/cfg_clock_default.h"
 #elif defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32L5) || \
diff --git a/cpu/stm32/include/cpu_conf.h b/cpu/stm32/include/cpu_conf.h
index a910fee151..d7785a38c9 100644
--- a/cpu/stm32/include/cpu_conf.h
+++ b/cpu/stm32/include/cpu_conf.h
@@ -49,6 +49,9 @@
 #elif CPU_FAM_STM32G0
 #include "stm32g0xx.h"
 #include "irqs/g0/irqs.h"
+#elif CPU_FAM_STM32C0
+#include "stm32c0xx.h"
+#include "irqs/c0/irqs.h"
 #elif CPU_FAM_STM32G4
 #include "stm32g4xx.h"
 #include "irqs/g4/irqs.h"
@@ -127,7 +130,8 @@ extern "C" {
    || defined(CPU_LINE_STM32F030xC) || defined(CPU_LINE_STM32F103xE) \
    || defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L4) \
    || defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) \
-   || defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL)
+   || defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL) \
+   || defined(CPU_FAM_STM32C0)
 #define FLASHPAGE_SIZE                  (2048U)
 #elif defined(CPU_LINE_STM32F051x8) || defined(CPU_LINE_STM32F042x6) \
    || defined(CPU_LINE_STM32F070xB) || defined(CPU_LINE_STM32F030x8) \
@@ -218,7 +222,7 @@ extern "C" {
 #if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
     defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
     defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
-    defined(CPU_FAM_STM32WL)
+    defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32C0)
 #define FLASHPAGE_WRITE_BLOCK_SIZE            (8U)
 typedef uint64_t stm32_flashpage_block_t;
 #elif defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1) || \
@@ -234,7 +238,7 @@ typedef uint16_t stm32_flashpage_block_t;
 #if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
     defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
     defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
-    defined(CPU_FAM_STM32WL)
+    defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32C0)
 #define FLASHPAGE_WRITE_BLOCK_ALIGNMENT       (8U)
 #else
 /* Writing should be always 4 bytes aligned */
diff --git a/cpu/stm32/include/periph/c0/periph_cpu.h b/cpu/stm32/include/periph/c0/periph_cpu.h
new file mode 100644
index 0000000000..81408b0349
--- /dev/null
+++ b/cpu/stm32/include/periph/c0/periph_cpu.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2024 BISSELL Homecare, Inc.
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup         cpu_stm32
+ * @{
+ *
+ * @file
+ * @brief           STM32C0 CPU specific definitions for internal peripheral handling
+ *
+ * @author      Jason Parker <Jason.Parker@bissell.com>
+ */
+
+#ifndef PERIPH_C0_PERIPH_CPU_H
+#define PERIPH_C0_PERIPH_CPU_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef DOXYGEN
+
+/**
+ * @brief   Starting address of the ROM bootloader
+ *          see application note AN2606
+ */
+#define STM32_BOOTLOADER_ADDR   (0x1FFF0000)
+
+/**
+ * @name   Constants for internal VBAT ADC line
+ * @{
+ */
+#define VBAT_ADC_RES        ADC_RES_12BIT
+#define VBAT_ADC_MAX        4095
+/** @} */
+
+#endif /* ndef DOXYGEN */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PERIPH_C0_PERIPH_CPU_H */
+/** @} */
diff --git a/cpu/stm32/include/periph/cpu_common.h b/cpu/stm32/include/periph/cpu_common.h
index 16b173c349..88b743c38e 100644
--- a/cpu/stm32/include/periph/cpu_common.h
+++ b/cpu/stm32/include/periph/cpu_common.h
@@ -62,7 +62,7 @@ extern "C" {
       defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4) || \
       defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) || \
       defined(CPU_FAM_STM32U5) || defined(CPU_FAM_STM32MP1) || \
-      defined(CPU_FAM_STM32WL)
+      defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32C0)
 #define CLOCK_LSI           (32000U)
 #else
 #error "error: LSI clock speed not defined for your target CPU"
@@ -80,10 +80,11 @@ typedef enum {
 #if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
     defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
     defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
-    defined(CPU_FAM_STM32WL)
+    defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32C0)
     APB12,          /**< AHB1 bus, second register */
 #endif
-#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32G0)
+#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32G0) || \
+    defined(CPU_FAM_STM32C0)
     AHB,            /**< AHB bus */
     IOP,            /**< IOP bus */
 #elif defined(CPU_FAM_STM32L1) || defined(CPU_FAM_STM32F1) || \
diff --git a/cpu/stm32/include/periph/cpu_i2c.h b/cpu/stm32/include/periph/cpu_i2c.h
index 0fc0e8b587..53f864faad 100644
--- a/cpu/stm32/include/periph/cpu_i2c.h
+++ b/cpu/stm32/include/periph/cpu_i2c.h
@@ -67,7 +67,7 @@ typedef enum {
     defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
     defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
     defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
-    defined(CPU_FAM_STM32WL)
+    defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32C0)
     I2C_SPEED_FAST_PLUS,    /**< fast plus mode: ~1Mbit/s */
 #endif
 } i2c_speed_t;
@@ -92,7 +92,8 @@ typedef struct {
     defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32G0) || \
     defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32L4) || \
     defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WB) || \
-    defined(CPU_FAM_STM32U5) || defined(CPU_FAM_STM32WL)
+    defined(CPU_FAM_STM32U5) || defined(CPU_FAM_STM32WL) || \
+    defined(CPU_FAM_STM32C0)
     uint32_t rcc_sw_mask;   /**< bit to switch I2C clock */
 #endif
 #if defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) || \
@@ -108,7 +109,7 @@ typedef struct {
     defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32L5) || \
     defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32G4) || \
     defined(CPU_FAM_STM32U5) || defined(CPU_FAM_STM32WB) || \
-    defined(CPU_FAM_STM32WL)
+    defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32C0)
 /**
  * @brief   Structure for I2C timing register settings
  */
@@ -159,14 +160,14 @@ static const i2c_timing_param_t timing_params[] = {
 #endif  /* CPU_FAM_STM32F0 || CPU_FAM_STM32F3 || CPU_FAM_STM32F7 ||
             CPU_FAM_STM32L0 || CPU_FAM_STM32L4 || CPU_FAM_STM32L5 ||
             CPU_FAM_STM32G0 || CPU_FAM_STM32G4 || CPU_FAM_STM32U5 ||
-            CPU_FAM_STM32WB || CPU_FAM_STM32WL */
+            CPU_FAM_STM32WB || CPU_FAM_STM32WL || CPU_FAM_STM32C0 */
 
 #if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F3) || \
     defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32G0) || \
     defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32L0) || \
     defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32L5) || \
     defined(CPU_FAM_STM32U5) || defined(CPU_FAM_STM32WB) || \
-    defined(CPU_FAM_STM32WL)
+    defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32C0)
 /**
  * @brief   The I2C implementation supports only a limited frame size.
  *          See i2c_1.c
diff --git a/cpu/stm32/include/periph_cpu.h b/cpu/stm32/include/periph_cpu.h
index 959ddcca6d..088a44b046 100644
--- a/cpu/stm32/include/periph_cpu.h
+++ b/cpu/stm32/include/periph_cpu.h
@@ -40,6 +40,8 @@
 #include "periph/f7/periph_cpu.h"
 #elif defined(CPU_FAM_STM32G0)
 #include "periph/g0/periph_cpu.h"
+#elif defined(CPU_FAM_STM32C0)
+#include "periph/c0/periph_cpu.h"
 #elif defined(CPU_FAM_STM32G4)
 #include "periph/g4/periph_cpu.h"
 #elif defined(CPU_FAM_STM32L0)
diff --git a/cpu/stm32/include/vendor/patches/c0/0001-stm32c0xx-remove-ErrorStatus.patch b/cpu/stm32/include/vendor/patches/c0/0001-stm32c0xx-remove-ErrorStatus.patch
new file mode 100644
index 0000000000..f939b2e898
Binary files /dev/null and b/cpu/stm32/include/vendor/patches/c0/0001-stm32c0xx-remove-ErrorStatus.patch differ
diff --git a/cpu/stm32/kconfigs/c0/Kconfig b/cpu/stm32/kconfigs/c0/Kconfig
new file mode 100644
index 0000000000..5229d868f0
--- /dev/null
+++ b/cpu/stm32/kconfigs/c0/Kconfig
@@ -0,0 +1,31 @@
+# Copyright (C) 2024 BISSELL Homecare, Inc.
+#
+# This file is subject to the terms and conditions of the GNU Lesser
+# General Public License v2.1. See the file LICENSE in the top level
+# directory for more details.
+#
+
+config CPU_FAM_C0
+    bool
+    select CPU_STM32
+    select CPU_CORE_CORTEX_M0PLUS
+    select HAS_CPU_STM32C0
+    select HAS_PERIPH_FLASHPAGE
+    select HAS_PERIPH_FLASHPAGE_IN_ADDRESS_SPACE
+    select HAS_PERIPH_FLASHPAGE_PAGEWISE
+    select HAS_PERIPH_FLASHPAGE_RAW
+    select HAS_PERIPH_GPIO_LL
+    select HAS_PERIPH_GPIO_LL_IRQ
+    select HAS_PERIPH_GPIO_LL_IRQ_LEVEL_TRIGGERED_HIGH
+    select HAS_PERIPH_GPIO_LL_IRQ_LEVEL_TRIGGERED_LOW
+    select HAS_PERIPH_VBAT
+    select HAS_PERIPH_WDT
+    select HAS_BOOTLOADER_STM32
+
+config CPU_FAM
+    default "c0" if CPU_FAM_C0
+
+config HAS_CPU_STM32C0
+    bool
+    help
+        Indicates that the cpu being used belongs to the 'stm32c0' family.
diff --git a/cpu/stm32/kconfigs/c0/Kconfig.clk b/cpu/stm32/kconfigs/c0/Kconfig.clk
new file mode 100644
index 0000000000..070fd3f94b
--- /dev/null
+++ b/cpu/stm32/kconfigs/c0/Kconfig.clk
@@ -0,0 +1,51 @@
+# Copyright (C) 2024 BISSELL Homecare, Inc.
+#
+# This file is subject to the terms and conditions of the GNU Lesser
+# General Public License v2.1. See the file LICENSE in the top level
+# directory for more details.
+#
+
+if CPU_FAM_C0
+
+choice
+bool "HSISYS division factor" if USE_CLOCK_HSI
+default CLOCK_HSISYS_DIV_1
+
+config CLOCK_HSISYS_DIV_1
+    bool "Divide HSISYS by 1"
+
+config CLOCK_HSISYS_DIV_2
+    bool "Divide HSISYS by 2"
+
+config CLOCK_HSISYS_DIV_4
+    bool "Divide HSISYS by 4"
+
+config CLOCK_HSISYS_DIV_8
+    bool "Divide HSISYS by 8"
+
+config CLOCK_HSISYS_DIV_16
+    bool "Divide HSISYS by 16"
+
+config CLOCK_HSISYS_DIV_32
+    bool "Divide HSISYS by 32"
+
+config CLOCK_HSISYS_DIV_64
+    bool "Divide HSISYS by 64"
+
+config CLOCK_HSISYS_DIV_128
+    bool "Divide HSISYS by 128"
+
+endchoice
+
+config CLOCK_HSISYS_DIV
+    int
+    default 1 if CLOCK_HSISYS_DIV_1
+    default 2 if CLOCK_HSISYS_DIV_2
+    default 4 if CLOCK_HSISYS_DIV_4
+    default 8 if CLOCK_HSISYS_DIV_8
+    default 16 if CLOCK_HSISYS_DIV_16
+    default 32 if CLOCK_HSISYS_DIV_32
+    default 64 if CLOCK_HSISYS_DIV_64
+    default 128 if CLOCK_HSISYS_DIV_128
+
+endif # CPU_FAM_C0
diff --git a/cpu/stm32/kconfigs/c0/Kconfig.lines b/cpu/stm32/kconfigs/c0/Kconfig.lines
new file mode 100644
index 0000000000..b99aac4d00
--- /dev/null
+++ b/cpu/stm32/kconfigs/c0/Kconfig.lines
@@ -0,0 +1,27 @@
+# Copyright (C) 2024 BISSELL Homecare, Inc.
+#
+# This file is subject to the terms and conditions of the GNU Lesser
+# General Public License v2.1. See the file LICENSE in the top level
+# directory for more details.
+#
+
+# This file was auto-generated from ST ProductsList.xlsx sheet using the
+# script in cpu/stm32/dist/kconfig/gen_kconfig.py
+# See cpu/stm32/dist/kconfig/README.md for details
+
+# CPU lines
+config CPU_LINE_STM32C011XX
+    bool
+    select CPU_FAM_C0
+
+config CPU_LINE_STM32C031XX
+    bool
+    select CPU_FAM_C0
+
+config CPU_LINE_STM32C071XX
+    bool
+    select CPU_FAM_C0
+
+config CPU_LINE_STM32C091XX
+    bool
+    select CPU_FAM_C0
diff --git a/cpu/stm32/kconfigs/c0/Kconfig.models b/cpu/stm32/kconfigs/c0/Kconfig.models
new file mode 100644
index 0000000000..7ec105f501
--- /dev/null
+++ b/cpu/stm32/kconfigs/c0/Kconfig.models
@@ -0,0 +1,129 @@
+# Copyright (C) 2024 BISSELL Homecare, Inc.
+#
+# This file is subject to the terms and conditions of the GNU Lesser
+# General Public License v2.1. See the file LICENSE in the top level
+# directory for more details.
+#
+
+# This file was auto-generated from ST ProductsList.xlsx sheet using the
+# script in cpu/stm32/dist/kconfig/gen_kconfig.py
+# See cpu/stm32/dist/kconfig/README.md for details
+
+# CPU models
+config CPU_MODEL_STM32C011D6
+    bool
+    select CPU_MODEL_STM32C011XX
+
+config CPU_MODEL_STM32C011F4
+    bool
+    select CPU_MODEL_STM32C011XX
+
+config CPU_MODEL_STM32C011F6
+    bool
+    select CPU_MODEL_STM32C011XX
+
+config CPU_MODEL_STM32C011J4
+    bool
+    select CPU_MODEL_STM32C011XX
+
+config CPU_MODEL_STM32C011J6
+    bool
+    select CPU_MODEL_STM32C011XX
+
+config CPU_MODEL_STM32C031C4
+    bool
+    select CPU_MODEL_STM32C031XX
+
+config CPU_MODEL_STM32C031C6
+    bool
+    select CPU_MODEL_STM32C031XX
+
+config CPU_MODEL_STM32C031F4
+    bool
+    select CPU_MODEL_STM32C031XX
+
+config CPU_MODEL_STM32C031F6
+    bool
+    select CPU_MODEL_STM32C031XX
+
+config CPU_MODEL_STM32C031G4
+    bool
+    select CPU_MODEL_STM32C031XX
+
+config CPU_MODEL_STM32C031G6
+    bool
+    select CPU_MODEL_STM32C031XX
+
+config CPU_MODEL_STM32C031K4
+    bool
+    select CPU_MODEL_STM32C031XX
+
+config CPU_MODEL_STM32C031K6
+    bool
+    select CPU_MODEL_STM32C031XX
+
+config CPU_MODEL_STM32C071CB
+    bool
+    select CPU_MODEL_STM32C071XX
+
+config CPU_MODEL_STM32C071FB
+    bool
+    select CPU_MODEL_STM32C071XX
+
+config CPU_MODEL_STM32C071GB
+    bool
+    select CPU_MODEL_STM32C071XX
+
+config CPU_MODEL_STM32C071KB
+    bool
+    select CPU_MODEL_STM32C071XX
+
+config CPU_MODEL_STM32C071RB
+    bool
+    select CPU_MODEL_STM32C071XX
+
+config CPU_MODEL_STM32C091CC
+    bool
+    select CPU_MODEL_STM32C091XX
+
+config CPU_MODEL_STM32C091FC
+    bool
+    select CPU_MODEL_STM32C091XX
+
+config CPU_MODEL_STM32C091GC
+    bool
+    select CPU_MODEL_STM32C091XX
+
+config CPU_MODEL_STM32C091KC
+    bool
+    select CPU_MODEL_STM32C091XX
+
+config CPU_MODEL_STM32C091RC
+    bool
+    select CPU_MODEL_STM32C091XX
+
+# Configure CPU model
+config CPU_MODEL
+    default "stm32c011d6" if CPU_MODEL_STM32C011D6
+    default "stm32c011f4" if CPU_MODEL_STM32C011F4
+    default "stm32c011f6" if CPU_MODEL_STM32C011F6
+    default "stm32c011j4" if CPU_MODEL_STM32C011J4
+    default "stm32c011j6" if CPU_MODEL_STM32C011J6
+    default "stm32c031c4" if CPU_MODEL_STM32C031C4
+    default "stm32c031c6" if CPU_MODEL_STM32C031C6
+    default "stm32c031f4" if CPU_MODEL_STM32C031F4
+    default "stm32c031f6" if CPU_MODEL_STM32C031F6
+    default "stm32c031g4" if CPU_MODEL_STM32C031G4
+    default "stm32c031g6" if CPU_MODEL_STM32C031G6
+    default "stm32c031k4" if CPU_MODEL_STM32C031K4
+    default "stm32c031k6" if CPU_MODEL_STM32C031K6
+    default "stm32c071cb" if CPU_MODEL_STM32C071CB
+    default "stm32c071fb" if CPU_MODEL_STM32C071FB
+    default "stm32c071gb" if CPU_MODEL_STM32C071GB
+    default "stm32c071kb" if CPU_MODEL_STM32C071KB
+    default "stm32c071rb" if CPU_MODEL_STM32C071RB
+    default "stm32c091cc" if CPU_MODEL_STM32C091CC
+    default "stm32c091fc" if CPU_MODEL_STM32C091FC
+    default "stm32c091gc" if CPU_MODEL_STM32C091GC
+    default "stm32c091kc" if CPU_MODEL_STM32C091KC
+    default "stm32c091rc" if CPU_MODEL_STM32C091RC
diff --git a/cpu/stm32/periph/Makefile b/cpu/stm32/periph/Makefile
index 04d0989545..af3456fbe6 100644
--- a/cpu/stm32/periph/Makefile
+++ b/cpu/stm32/periph/Makefile
@@ -2,7 +2,7 @@ MODULE = periph
 
 # Select the specific implementation for `periph_i2c`
 ifneq (,$(filter periph_i2c,$(USEMODULE)))
-  ifneq (,$(filter $(CPU_FAM),f0 f3 f7 g0 g4 l0 l4 l5 u5 wb wl))
+  ifneq (,$(filter $(CPU_FAM),f0 f3 f7 g0 g4 l0 l4 l5 u5 wb wl c0))
     SRC += i2c_1.c
   else ifneq (,$(filter $(CPU_FAM),f1 f2 f4 l1))
     SRC += i2c_2.c
@@ -15,8 +15,8 @@ endif
 ifneq (,$(filter periph_adc,$(USEMODULE)))
   ifneq (,$(filter $(CPU_FAM),f4 f7))
     SRC += adc_f4_f7.c
-  else ifneq (,$(filter $(CPU_FAM),f0 g0))
-    SRC += adc_f0_g0.c
+  else ifneq (,$(filter $(CPU_FAM),f0 g0 c0))
+    SRC += adc_f0_g0_c0.c
   else
     SRC += adc_$(CPU_FAM).c
   endif
diff --git a/cpu/stm32/periph/adc_f0_g0.c b/cpu/stm32/periph/adc_f0_g0_c0.c
similarity index 100%
rename from cpu/stm32/periph/adc_f0_g0.c
rename to cpu/stm32/periph/adc_f0_g0_c0.c
diff --git a/cpu/stm32/periph/dma.c b/cpu/stm32/periph/dma.c
index 0b4370aed4..f31f384f92 100644
--- a/cpu/stm32/periph/dma.c
+++ b/cpu/stm32/periph/dma.c
@@ -123,7 +123,7 @@ static inline DMA_TypeDef *dma_req(int stream_n)
 {
     return dma_base(stream_n);
 }
-#elif CPU_FAM_STM32L0 || CPU_FAM_STM32L4 || CPU_FAM_STM32G0
+#elif CPU_FAM_STM32L0 || CPU_FAM_STM32L4 || CPU_FAM_STM32G0 || CPU_FAM_STM32C0
 static inline DMA_Request_TypeDef *dma_req(int stream_n)
 {
 #ifdef DMA2
@@ -182,7 +182,7 @@ static IRQn_Type dma_get_irqn(int stream)
     else if (stream < 16) {
         return ((IRQn_Type)((int)DMA2_Stream5_IRQn + (stream - 13)));
     }
-#elif CPU_FAM_STM32F0 || CPU_FAM_STM32L0 || CPU_FAM_STM32G0
+#elif CPU_FAM_STM32F0 || CPU_FAM_STM32L0 || CPU_FAM_STM32G0 || CPU_FAM_STM32C0
     if (stream == 0) {
         return (DMA1_Channel1_IRQn);
     }
diff --git a/cpu/stm32/periph/flash_common.c b/cpu/stm32/periph/flash_common.c
index f47658af89..96c83eaffb 100644
--- a/cpu/stm32/periph/flash_common.c
+++ b/cpu/stm32/periph/flash_common.c
@@ -48,7 +48,8 @@
 #if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
     defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
     defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
-    defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32WL)
+    defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32WL) || \
+    defined(CPU_FAM_STM32C0)
 #define FLASH_KEY1             ((uint32_t)0x45670123)
 #define FLASH_KEY2             ((uint32_t)0xCDEF89AB)
 #endif
@@ -57,7 +58,7 @@
 #define KEY_REG                (FLASH->KEYR)
 #endif
 
-#if defined(CPU_FAM_STM32G0)
+#if defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32C0)
 #define FLASH_SR_BSY           (FLASH_SR_BSY1)
 #endif
 
diff --git a/cpu/stm32/periph/flashpage.c b/cpu/stm32/periph/flashpage.c
index 565cf7e13e..61fbcd8706 100644
--- a/cpu/stm32/periph/flashpage.c
+++ b/cpu/stm32/periph/flashpage.c
@@ -121,7 +121,8 @@ static void _erase_page(void *page_addr)
       defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
       defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32F2) || \
       defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32F7) || \
-      defined(CPU_FAM_STM32U5) || defined(CPU_FAM_STM32WL)
+      defined(CPU_FAM_STM32U5) || defined(CPU_FAM_STM32WL) || \
+      defined(CPU_FAM_STM32C0)
     DEBUG("[flashpage] erase: setting the page address\n");
     uint8_t pn;
 #if (FLASHPAGE_NUMOF <= MAX_PAGES_PER_BANK) || defined(CPU_FAM_STM32WB) || \
@@ -273,7 +274,7 @@ void flashpage_write(void *target_addr, const void *data, size_t len)
     defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) || \
     defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
     defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32U5) || \
-    defined(CPU_FAM_STM32WL)
+    defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32C0)
     /* set PG bit and program page to flash */
     CNTRL_REG |= FLASH_CR_PG;
 #endif
@@ -294,7 +295,7 @@ void flashpage_write(void *target_addr, const void *data, size_t len)
     defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) || \
     defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
     defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32U5) || \
-    defined(CPU_FAM_STM32WL)
+    defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32C0)
     CNTRL_REG &= ~(FLASH_CR_PG);
 #endif
     DEBUG("[flashpage_raw] write: done writing data\n");
diff --git a/cpu/stm32/periph/gpio_all.c b/cpu/stm32/periph/gpio_all.c
index 8a253d7503..4b6a578ca5 100644
--- a/cpu/stm32/periph/gpio_all.c
+++ b/cpu/stm32/periph/gpio_all.c
@@ -47,7 +47,7 @@ static gpio_isr_ctx_t isr_ctx[EXTI_NUMOF];
 #if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
     defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
     defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
-    defined(CPU_FAM_STM32WL)
+    defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32C0)
 #define EXTI_REG_RTSR       (EXTI->RTSR1)
 #define EXTI_REG_FTSR       (EXTI->FTSR1)
 #define EXTI_REG_PR         (EXTI->PR1)
@@ -100,7 +100,8 @@ static inline void port_init_clock(GPIO_TypeDef *port, gpio_t pin)
     (void)port; /* <-- Only used for when port G requires special handling */
 #if defined(CPU_FAM_STM32F0) || defined (CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L1)
     periph_clk_en(AHB, (RCC_AHBENR_GPIOAEN << _port_num(pin)));
-#elif defined (CPU_FAM_STM32L0) || defined(CPU_FAM_STM32G0)
+#elif defined (CPU_FAM_STM32L0) || defined(CPU_FAM_STM32G0) || \
+    defined(CPU_FAM_STM32C0)
     periph_clk_en(IOP, (RCC_IOPENR_GPIOAEN << _port_num(pin)));
 #elif defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
       defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32L5) || \
@@ -173,7 +174,8 @@ void gpio_init_analog(gpio_t pin)
      * gpio_init first */
 #if defined(CPU_FAM_STM32F0) || defined (CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L1)
     periph_clk_en(AHB, (RCC_AHBENR_GPIOAEN << _port_num(pin)));
-#elif defined (CPU_FAM_STM32L0) || defined(CPU_FAM_STM32G0)
+#elif defined (CPU_FAM_STM32L0) || defined(CPU_FAM_STM32G0) || \
+    defined(CPU_FAM_STM32C0)
     periph_clk_en(IOP, (RCC_IOPENR_GPIOAEN << _port_num(pin)));
 #elif defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
       defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32L5) || \
@@ -250,7 +252,7 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
     !defined(CPU_FAM_STM32WL)
 #ifdef CPU_FAM_STM32F0
     periph_clk_en(APB2, RCC_APB2ENR_SYSCFGCOMPEN);
-#elif defined(CPU_FAM_STM32G0)
+#elif defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32C0)
     periph_clk_en(APB12, RCC_APBENR2_SYSCFGEN);
 #elif defined(CPU_FAM_STM32U5)
     periph_clk_en(APB3, RCC_APB3ENR_SYSCFGEN);
@@ -266,7 +268,7 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
 #if defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5)
     NVIC_EnableIRQ(EXTI0_IRQn + pin_num);
 #elif defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32L0) || \
-    defined(CPU_FAM_STM32G0)
+    defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32C0)
     if (pin_num < 2) {
         NVIC_EnableIRQ(EXTI0_1_IRQn);
     }
@@ -319,7 +321,7 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
     EXTI_REG_FTSR |=  ((flank >> 1) << pin_num);
 
 #if defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) || \
-    defined(CPU_FAM_STM32U5)
+    defined(CPU_FAM_STM32U5) || defined(CPU_FAM_STM32C0)
     /* enable specific pin as exti sources */
     EXTI->EXTICR[pin_num >> 2] &= ~(0xf << ((pin_num & 0x03) * 8));
     EXTI->EXTICR[pin_num >> 2] |= (port_num << ((pin_num & 0x03) * 8));
@@ -334,7 +336,8 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
 #endif
 
 #if defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) || \
-    defined(CPU_FAM_STM32U5) || defined(CPU_FAM_STM32MP1)
+    defined(CPU_FAM_STM32U5) || defined(CPU_FAM_STM32MP1) || \
+    defined(CPU_FAM_STM32C0)
     /* clear any pending requests */
     EXTI->RPR1 = (1 << pin_num);
     EXTI->FPR1 = (1 << pin_num);
@@ -351,7 +354,8 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
 void isr_exti(void)
 {
 #if defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) || \
-    defined(CPU_FAM_STM32U5) || defined(CPU_FAM_STM32MP1)
+    defined(CPU_FAM_STM32U5) || defined(CPU_FAM_STM32MP1) || \
+    defined(CPU_FAM_STM32C0)
     /* get all interrupts handled by this ISR */
     uint32_t pending_rising_isr = (EXTI->RPR1 & EXTI_MASK);
     uint32_t pending_falling_isr = (EXTI->FPR1 & EXTI_MASK);
diff --git a/cpu/stm32/periph/gpio_ll_irq.c b/cpu/stm32/periph/gpio_ll_irq.c
index 046f370978..f908ded8c8 100644
--- a/cpu/stm32/periph/gpio_ll_irq.c
+++ b/cpu/stm32/periph/gpio_ll_irq.c
@@ -149,7 +149,7 @@ static IRQn_Type get_irqn(uint8_t pin)
 #if defined(CPU_FAM_STM32L5) ||  defined(CPU_FAM_STM32U5)
     return EXTI0_IRQn + pin;
 #elif defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32L0) || \
-    defined(CPU_FAM_STM32G0)
+    defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32C0)
     if (pin < 2) {
         return EXTI0_1_IRQn;
     }
diff --git a/cpu/stm32/periph/pm.c b/cpu/stm32/periph/pm.c
index 81bfdeeb4f..b1072a9b12 100644
--- a/cpu/stm32/periph/pm.c
+++ b/cpu/stm32/periph/pm.c
@@ -51,7 +51,7 @@
       defined(CPU_FAM_STM32L5)
 #define PM_STOP_CONFIG  (PWR_CR1_LPMS_STOP1)
 #elif defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G0) || \
-      defined(CPU_FAM_STM32WL)
+      defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32C0)
 #define PM_STOP_CONFIG  (PWR_CR1_LPMS_0)
 #elif defined(CPU_FAM_STM32F7)
 #define PM_STOP_CONFIG  (PWR_CR1_LPDS | PWR_CR1_FPDS | PWR_CR1_LPUDS)
@@ -76,7 +76,7 @@
       defined(CPU_FAM_STM32L5)
 #define PM_STANDBY_CONFIG   (PWR_CR1_LPMS_STANDBY)
 #elif defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G0) || \
-      defined(CPU_FAM_STM32WL)
+      defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32C0)
 #define PM_STANDBY_CONFIG   (PWR_CR1_LPMS_0 | PWR_CR1_LPMS_1)
 #elif defined(CPU_FAM_STM32F7)
 #define PM_STANDBY_CONFIG   (PWR_CR1_PDDS | PWR_CR1_CSBF)
@@ -92,7 +92,7 @@
 #if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
     defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
     defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
-    defined(CPU_FAM_STM32WL)
+    defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32C0)
 #define PWR_CR_REG     PWR->CR1
 #define PWR_WUP_REG    PWR->CR3
 /* Allow overridable SRAM2 retention mode using CFLAGS */
@@ -199,7 +199,7 @@ void pm_backup_regulator_on(void)
         stmclk_dbp_unlock();
     }
     PWR_BACKUP_REGULATOR_REG |= BKPREG_CONFIG;
-    while (!(PWR_BACKUP_REGULATOR_REG & BKPREG_READY));
+    while (!(PWR_BACKUP_REGULATOR_REG & BKPREG_READY)){}
     if (locked) {
         stmclk_dbp_lock();
     }
diff --git a/cpu/stm32/periph/rtt_all.c b/cpu/stm32/periph/rtt_all.c
index fce7c3c4d1..389a8ff799 100644
--- a/cpu/stm32/periph/rtt_all.c
+++ b/cpu/stm32/periph/rtt_all.c
@@ -86,7 +86,8 @@ register. */
 #if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32L5)
 #define IMR_REG             IMR2
 #define EXTI_IMR_BIT        EXTI_IMR2_IM32
-#elif defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32WL)
+#elif defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32WL) || \
+    defined(CPU_FAM_STM32C0)
 #define IMR_REG             IMR1
 #define EXTI_IMR_BIT        EXTI_IMR1_IM29
 #elif defined(CPU_FAM_STM32G4)
@@ -137,7 +138,7 @@ void rtt_init(void)
 #if !defined(CPU_FAM_STM32L4) && !defined(CPU_FAM_STM32L0) && \
     !defined(CPU_FAM_STM32WB) && !defined(CPU_FAM_STM32G4) && \
     !defined(CPU_FAM_STM32G0) && !defined(CPU_FAM_STM32WL) && \
-    !defined(CPU_FAM_STM32L5)
+    !defined(CPU_FAM_STM32L5) && !defined(CPU_FAM_STM32C0)
     EXTI->FTSR_REG &= ~(EXTI_FTSR_BIT);
     EXTI->RTSR_REG |= EXTI_RTSR_BIT;
     EXTI->PR_REG = EXTI_PR_BIT;
@@ -249,7 +250,7 @@ void isr_lptim1(void)
 #if !defined(CPU_FAM_STM32L4) && !defined(CPU_FAM_STM32L0) && \
     !defined(CPU_FAM_STM32WB) && !defined(CPU_FAM_STM32G4) && \
     !defined(CPU_FAM_STM32G0) && !defined(CPU_FAM_STM32WL) && \
-    !defined(CPU_FAM_STM32L5)
+    !defined(CPU_FAM_STM32L5) && !defined(CPU_FAM_STM32C0)
     EXTI->PR_REG = EXTI_PR_BIT; /* only clear the associated bit */
 #endif
 
diff --git a/cpu/stm32/periph/uart.c b/cpu/stm32/periph/uart.c
index 09484842b8..b1a54e554d 100644
--- a/cpu/stm32/periph/uart.c
+++ b/cpu/stm32/periph/uart.c
@@ -36,7 +36,7 @@
 
 #if defined(CPU_LINE_STM32L4R5xx) || defined(CPU_FAM_STM32G0) || \
     defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
-    defined(CPU_FAM_STM32WL)
+    defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32C0)
 #define ISR_REG     ISR
 #define ISR_TXE     USART_ISR_TXE_TXFNF
 #define ISR_RXNE    USART_ISR_RXNE_RXFNE
@@ -64,7 +64,7 @@
 
 #if defined(CPU_LINE_STM32L4R5xx) || defined(CPU_FAM_STM32G0) || \
     defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
-    defined(CPU_FAM_STM32WL)
+    defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32C0)
 #define RXENABLE            (USART_CR1_RE | USART_CR1_RXNEIE_RXFNEIE)
 #else
 #define RXENABLE            (USART_CR1_RE | USART_CR1_RXNEIE)
diff --git a/cpu/stm32/stm32_info.mk b/cpu/stm32/stm32_info.mk
index 348bebb283..3bbf17b74a 100644
--- a/cpu/stm32/stm32_info.mk
+++ b/cpu/stm32/stm32_info.mk
@@ -8,7 +8,7 @@
 #  - STM32_PINCOUNT: R (64)
 #  - STM32_ROMSIZE: G (1024K)
 CPU_MODEL_UPPERCASE = $(call uppercase,$(CPU_MODEL))
-STM32_INFO     := $(shell echo $(CPU_MODEL_UPPERCASE) | sed -E -e 's/^STM32(F|L|W|G|MP|U)([0-7]|B|L)([A-Z0-9])([0-9])(.)(.)?(_A)?/\1 \2 \2\3\4 \3 \4 \5 \6 \7/')
+STM32_INFO     := $(shell echo $(CPU_MODEL_UPPERCASE) | sed -E -e 's/^STM32(F|L|W|G|MP|U|C)([0-7]|B|L)([A-Z0-9])([0-9])(.)(.)?(_A)?/\1 \2 \2\3\4 \3 \4 \5 \6 \7/')
 STM32_TYPE     = $(word 1, $(STM32_INFO))
 STM32_FAMILY   = $(word 2, $(STM32_INFO))
 STM32_MODEL    = $(word 3, $(STM32_INFO))
@@ -40,10 +40,10 @@ else ifneq (,$(filter $(CPU_FAM),g4 wb wl))
   CPU_CORE = cortex-m4
 else ifeq (f7,$(CPU_FAM))
   CPU_CORE = cortex-m7
-else ifneq (,$(filter $(CPU_FAM),g0 l0))
+else ifneq (,$(filter $(CPU_FAM),g0 l0 c0))
   CPU_CORE = cortex-m0plus
 else ifneq (,$(filter $(CPU_FAM),l5 u5))
   CPU_CORE = cortex-m33
 else
-  $(error Not supported CPU family: 'stm32$(CPU_FAM)')
+  $(error Not supported CPU family: '$(CPU_FAM)')
 endif
diff --git a/cpu/stm32/stm32_line.mk b/cpu/stm32/stm32_line.mk
index 094cb40e00..a7b4e49d49 100644
--- a/cpu/stm32/stm32_line.mk
+++ b/cpu/stm32/stm32_line.mk
@@ -95,6 +95,13 @@ ifeq (G,$(STM32_TYPE))
     endif
   endif
 endif
+ifeq (C,$(STM32_TYPE))
+  ifeq (0,$(STM32_FAMILY))  # STM32C0
+    ifneq (,$(filter $(STM32_MODEL), 011 031 071 091))
+      CPU_LINE = STM32C$(STM32_MODEL)xx
+    endif
+  endif
+endif
 ifeq (L,$(STM32_TYPE))
   ifeq (0,$(STM32_FAMILY))  # STM32L0
     ifneq (,$(filter $(STM32_MODEL), 010))
diff --git a/cpu/stm32/stm32_mem_lengths.mk b/cpu/stm32/stm32_mem_lengths.mk
index 2e6471d793..e6c9805cbe 100644
--- a/cpu/stm32/stm32_mem_lengths.mk
+++ b/cpu/stm32/stm32_mem_lengths.mk
@@ -318,6 +318,22 @@ else ifeq ($(STM32_TYPE), MP)
       RAM_LEN = 384K
     endif
   endif
+else ifeq ($(STM32_TYPE), C)
+  ifeq ($(STM32_FAMILY), 0)
+    ifneq (, $(filter $(STM32_MODEL2), 1))
+      RAM_LEN = 6K
+    else ifneq (, $(filter $(STM32_MODEL2), 7))
+      ifeq ($(STM32_ROMSIZE), 8)
+        RAM_LEN = 12K
+      else ifeq ($(STM32_ROMSIZE), B)
+        RAM_LEN = 24K
+      endif
+    else ifneq (, $(filter $(STM32_MODEL2), 9))
+      RAM_LEN = 36K
+    else ifneq (, $(filter $(STM32_MODEL2), 3))
+      RAM_LEN = 12K
+    endif
+  endif
 endif
 
 ifeq ($(RAM_LEN), )
@@ -414,6 +430,10 @@ else ifeq ($(STM32_PINCOUNT), Z)
   STM32_PIN = 144
 else ifeq ($(STM32_PINCOUNT), AC)
   STM32_PIN = 361
+else ifeq ($(STM32_PINCOUNT), J)
+  STM32_PIN = 8
+else ifeq ($(STM32_PINCOUNT), D)
+  STM32_PIN = 12
 endif
 
 # Set the common memory addresses for stm32 MCU family
diff --git a/cpu/stm32/stmclk/Makefile b/cpu/stm32/stmclk/Makefile
index 37ea80c3e8..b8d2bf1794 100644
--- a/cpu/stm32/stmclk/Makefile
+++ b/cpu/stm32/stmclk/Makefile
@@ -18,6 +18,8 @@ else ifneq (,$(filter $(CPU_FAM),u5))
   SRC += stmclk_u5.c
 else ifneq (,$(filter $(CPU_FAM),g0 g4))
   SRC += stmclk_gx.c
+else ifneq (,$(filter $(CPU_FAM),c0))
+  SRC += stmclk_c0.c
 else ifneq (,$(filter $(CPU_FAM),mp1))
   ifneq (,$(filter stm32mp1_eng_mode,$(USEMODULE)))
     SRC = stmclk_mp1.c
diff --git a/cpu/stm32/stmclk/stmclk_c0.c b/cpu/stm32/stmclk/stmclk_c0.c
new file mode 100644
index 0000000000..85503f29e9
--- /dev/null
+++ b/cpu/stm32/stmclk/stmclk_c0.c
@@ -0,0 +1,292 @@
+/*
+ * Copyright (C) 2024 BISSELL Homecare, Inc.
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     cpu_stm32
+ * @{
+ *
+ * @file
+ * @brief       Implementation of STM32 clock configuration for the C0 family
+ *
+ * @author      Jason Parker <Jason.Parker@bissell.com>
+ * @}
+ */
+
+#include "cpu.h"
+#include "stmclk.h"
+#include "periph_conf.h"
+#include "periph/gpio.h"
+
+#if defined(CPU_FAM_STM32C0)
+#define RCC_CFGR_SW_HSI             (0)
+#define RCC_CFGR_SW_HSE             (RCC_CFGR_SW_0)
+
+#if CONFIG_CLOCK_HSISYS_DIV == 1
+#define CLOCK_HSI_DIV               (0)
+#elif CONFIG_CLOCK_HSISYS_DIV == 2
+#define CLOCK_HSI_DIV               (RCC_CR_HSIDIV_0)
+#elif CONFIG_CLOCK_HSISYS_DIV == 4
+#define CLOCK_HSI_DIV               (RCC_CR_HSIDIV_1)
+#elif CONFIG_CLOCK_HSISYS_DIV == 8
+#define CLOCK_HSI_DIV               (RCC_CR_HSIDIV_1 | RCC_CR_HSIDIV_0)
+#elif CONFIG_CLOCK_HSISYS_DIV == 16
+#define CLOCK_HSI_DIV               (RCC_CR_HSIDIV_2)
+#elif CONFIG_CLOCK_HSISYS_DIV == 32
+#define CLOCK_HSI_DIV               (RCC_CR_HSIDIV_2 | RCC_CR_HSIDIV_0)
+#elif CONFIG_CLOCK_HSISYS_DIV == 64
+#define CLOCK_HSI_DIV               (RCC_CR_HSIDIV_2 | RCC_CR_HSIDIV_1)
+#elif CONFIG_CLOCK_HSISYS_DIV == 128
+#define CLOCK_HSI_DIV               (RCC_CR_HSIDIV_2 | RCC_CR_HSIDIV_1 | RCC_CR_HSIDIV_0)
+#endif
+
+#define CLOCK_AHB_DIV               (0)
+
+#if CONFIG_CLOCK_APB1_DIV == 1
+#define CLOCK_APB1_DIV              (0)
+#elif CONFIG_CLOCK_APB1_DIV == 2
+#define CLOCK_APB1_DIV              (RCC_CFGR_PPRE_2)
+#elif CONFIG_CLOCK_APB1_DIV == 4
+#define CLOCK_APB1_DIV              (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_0)
+#elif CONFIG_CLOCK_APB1_DIV == 8
+#define CLOCK_APB1_DIV              (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1)
+#elif CONFIG_CLOCK_APB1_DIV == 16
+#define CLOCK_APB1_DIV              (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1 | RCC_CFGR_PPRE_0)
+#endif
+#endif /* CPU_FAM_STM32C0 */
+
+/* Configure MCO */
+#ifndef CONFIG_CLOCK_ENABLE_MCO
+#define CONFIG_CLOCK_ENABLE_MCO     0   /* Don't enable MCO by default */
+#endif
+
+/* Configure the MCO clock source: options are HSE, HSI (default), LSE, LSI or SYSCLK*/
+#define CONFIG_CLOCK_MCO_USE_PLLCLK 0   // PLL not supported in STM32C0
+
+#ifndef CONFIG_CLOCK_MCO_USE_HSE
+#define CONFIG_CLOCK_MCO_USE_HSE    0
+#endif /* CONFIG_CLOCK_MCO_USE_HSE */
+
+#ifndef CONFIG_CLOCK_MCO_USE_HSI
+#define CONFIG_CLOCK_MCO_USE_HSI    1
+#endif /* CONFIG_CLOCK_MCO_USE_HSI */
+
+#ifndef CONFIG_CLOCK_MCO_USE_LSE
+#define CONFIG_CLOCK_MCO_USE_LSE    0
+#endif /* CONFIG_CLOCK_MCO_USE_LSE */
+
+#ifndef CONFIG_CLOCK_MCO_USE_LSI
+#define CONFIG_CLOCK_MCO_USE_LSI    0
+#endif /* CONFIG_CLOCK_MCO_USE_LSI */
+
+#ifndef CONFIG_CLOCK_MCO_USE_SYSCLK
+#define CONFIG_CLOCK_MCO_USE_SYSCLK 0
+#endif /* CONFIG_CLOCK_MCO_USE_SYSCLK */
+
+#if IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSE) && \
+    (IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSI) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSE) || \
+     IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSI) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_SYSCLK))
+#error "Cannot use HSE as MCO clock source with other clocks"
+#endif
+
+#if IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSI) && \
+    (IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSE) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSE) || \
+     IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSI) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_SYSCLK))
+#error "Cannot use HSI as MCO clock source with other clocks"
+#endif
+
+#if IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSE) && \
+    (IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSE) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSI) || \
+     IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSI) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_SYSCLK))
+#error "Cannot use LSE as MCO clock source with other clocks"
+#endif
+
+#if IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSI) && \
+    (IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSE) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSI) || \
+     IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSE) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_SYSCLK))
+#error "Cannot use LSI as MCO clock source with other clocks"
+#endif
+
+#if IS_ACTIVE(CONFIG_CLOCK_MCO_USE_SYSCLK) && \
+    (IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSE) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSI) || \
+     IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSE) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSI))
+#error "Cannot use SYSCLK as MCO clock source with other clocks"
+#endif
+
+#if IS_ACTIVE(CONFIG_CLOCK_MCO_USE_SYSCLK)
+#define CLOCK_MCO_SRC               (RCC_CFGR_MCOSEL_0)
+#elif IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSI)
+#define CLOCK_MCO_SRC               (RCC_CFGR_MCOSEL_1 | RCC_CFGR_MCOSEL_0)
+#elif IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSE)
+#define CLOCK_MCO_SRC               (RCC_CFGR_MCOSEL_2)
+#elif IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSI)
+#define CLOCK_MCO_SRC               (RCC_CFGR_MCOSEL_2 | RCC_CFGR_MCOSEL_1)
+#elif IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSE)
+#define CLOCK_MCO_SRC               (RCC_CFGR_MCOSEL_2 | RCC_CFGR_MCOSEL_1 | RCC_CFGR_MCOSEL_0)
+#else
+#error "Invalid MCO clock source selection"
+#endif
+
+/* Configure the MCO prescaler */
+#ifndef CONFIG_CLOCK_MCO_PRE
+#define CONFIG_CLOCK_MCO_PRE        (1)
+#endif
+
+/* Define MCO prescalers */
+#if CONFIG_CLOCK_MCO_PRE == 1
+#define CLOCK_MCO_PRE               (0)
+#elif CONFIG_CLOCK_MCO_PRE == 2
+#define CLOCK_MCO_PRE               (RCC_CFGR_MCOPRE_0)
+#elif CONFIG_CLOCK_MCO_PRE == 4
+#define CLOCK_MCO_PRE               (RCC_CFGR_MCOPRE_1)
+#elif CONFIG_CLOCK_MCO_PRE == 8
+#define CLOCK_MCO_PRE               (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0)
+#elif CONFIG_CLOCK_MCO_PRE == 16
+#define CLOCK_MCO_PRE               (RCC_CFGR_MCOPRE_2)
+#elif CONFIG_CLOCK_MCO_PRE == 32
+#define CLOCK_MCO_PRE               (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_0)
+#elif CONFIG_CLOCK_MCO_PRE == 64
+#define CLOCK_MCO_PRE               (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1)
+#elif CONFIG_CLOCK_MCO_PRE == 128
+#define CLOCK_MCO_PRE               (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0)
+#else
+#error "Invalid MCO prescaler"
+#endif
+
+/* PLL not supported in STM32C0 */
+#define CLOCK_ENABLE_PLL            0
+
+/* Check whether HSE is required:
+  - When HSE is used as SYSCLK
+  - When HSE is used as MCO clock source
+*/
+#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || \
+    (IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO) && IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSE))
+#define CLOCK_ENABLE_HSE            1
+#else
+#define CLOCK_ENABLE_HSE            0
+#endif
+
+/* Check whether HSI is required:
+  - When HSI is used as SYSCLK
+  - When HSI is used as MCO clock source
+*/
+#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) || \
+    (IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO) && IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSI))
+#define CLOCK_ENABLE_HSI            1
+#else
+#define CLOCK_ENABLE_HSI            0
+#endif
+
+/* Check whether LSE must be enabled */
+#if IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO) && IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSE)
+#define CLOCK_ENABLE_LSE            1
+#else
+#define CLOCK_ENABLE_LSE            0
+#endif
+
+/* Check whether LSI must be enabled */
+#if IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO) && IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSI)
+#define CLOCK_ENABLE_LSI            1
+#else
+#define CLOCK_ENABLE_LSI            0
+#endif
+
+/** Determine the required flash wait states from the core clock frequency */
+#if CLOCK_CORECLOCK >= 24000000
+#define FLASH_WAITSTATES            (FLASH_ACR_LATENCY_0)   /* 1 wait states */
+#else
+#define FLASH_WAITSTATES            (0)                     /* 0 wait states */
+#endif
+
+void stmclk_init_sysclk(void)
+{
+    /* disable any interrupts. Global interrupts could be enabled if this is
+     * called from some kind of bootloader...  */
+    unsigned is = irq_disable();
+    /* enable HSI clock for the duration of initialization */
+    stmclk_enable_hsi();
+
+    RCC->CIER = 0;
+
+    /* use HSI as system clock while we do any further configuration and
+     * configure the AHB and APB clock dividers as configured by the board */
+    RCC->CFGR = (RCC_CFGR_SW_HSI | CLOCK_AHB_DIV | CLOCK_APB1_DIV);
+
+    while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) {}
+
+    /* we enable instruction cache, pre-fetch, and we set the required flash wait states */
+    FLASH->ACR |= (FLASH_ACR_ICEN | FLASH_ACR_PRFTEN | FLASH_WAITSTATES);
+
+    /* disable all active clocks except HSI -> resets the clk configuration */
+    RCC->CR = RCC_CR_HSION;
+
+    if (IS_ACTIVE(CONFIG_USE_CLOCK_HSI) && CONFIG_CLOCK_HSISYS_DIV != 1) {
+        /* configure HSISYS divider */
+        RCC->CR |= CLOCK_HSI_DIV;
+        while (!(RCC->CR & RCC_CR_HSIRDY)) {}
+    }
+
+    /* Enable HSE if required */
+    if (IS_ACTIVE(CLOCK_ENABLE_HSE)) {
+        RCC->CR |= RCC_CR_HSEON;
+        while (!(RCC->CR & RCC_CR_HSERDY)) {}
+    }
+
+    /* Configure SYSCLK */
+    if (IS_ACTIVE(CONFIG_USE_CLOCK_HSE)) {
+        RCC->CFGR = (RCC_CFGR_SW_HSE | CLOCK_AHB_DIV | CLOCK_APB1_DIV);
+
+        RCC->CFGR |= RCC_CFGR_SW_HSE;
+        while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSE) {}
+    }
+
+    if (!IS_ACTIVE(CLOCK_ENABLE_HSI)) {
+        /* Disable HSI only if not used */
+        stmclk_disable_hsi();
+    }
+
+    /* Enable the LSE if required for MCO
+     * If available on the board, LSE might also be initialized for RTT/RTC
+     * peripherals. For the monent, this initialization is done in the
+     * corresponding peripheral drivers. */
+    if (IS_ACTIVE(CLOCK_ENABLE_LSE)) {
+        stmclk_dbp_unlock();
+        RCC->CSR1 |= RCC_CSR1_LSEON;
+        while (!(RCC->CSR1 & RCC_CSR1_LSERDY)) {}
+        stmclk_dbp_lock();
+    }
+
+    /* Enable the LSI if required for MCO
+     * If no LSE is available on the board, LSI might also be initialized for
+     * RTT/RTC peripherals. For the monent, this initialization is done in the
+     * corresponding peripheral drivers. */
+    if (IS_ACTIVE(CLOCK_ENABLE_LSI)) {
+        RCC->CSR2 |= RCC_CSR2_LSION;
+        while (!(RCC->CSR2 & RCC_CSR2_LSIRDY)) {}
+    }
+
+    /* Configure MCO */
+    if (IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO)) {
+        /* As stated in the manual, it is highly recommended to change the MCO
+           prescaler before enabling the MCO */
+        RCC->CFGR |= CLOCK_MCO_PRE;
+        RCC->CFGR |= CLOCK_MCO_SRC;
+
+        /* Configure MCO pin (PA8 with AF0) */
+        gpio_init(GPIO_PIN(PORT_A, 8), GPIO_OUT);
+        gpio_init_af(GPIO_PIN(PORT_A, 8), GPIO_AF0);
+    }
+
+#if IS_USED(MODULE_PERIPH_HWRNG)
+    /* HWRNG is clocked by HSI48 so enable this clock when the peripheral is used */
+    RCC->CRRCR |= RCC_CRRCR_HSI48ON;
+    while (!(RCC->CRRCR & RCC_CRRCR_HSI48RDY)) {}
+#endif
+
+    irq_restore(is);
+}
diff --git a/cpu/stm32/stmclk/stmclk_common.c b/cpu/stm32/stmclk/stmclk_common.c
index 413b4eef97..7ba57c69f9 100644
--- a/cpu/stm32/stmclk/stmclk_common.c
+++ b/cpu/stm32/stmclk/stmclk_common.c
@@ -41,6 +41,10 @@
 #define REG_LSE             CSR
 #define BIT_LSEON           RCC_CSR_LSEON
 #define BIT_LSERDY          RCC_CSR_LSERDY
+#elif defined(CPU_FAM_STM32C0)
+#define REG_LSE             CSR1
+#define BIT_LSEON           RCC_CSR1_LSEON
+#define BIT_LSERDY          RCC_CSR1_LSERDY
 #else
 #define REG_LSE             BDCR
 #define BIT_LSEON           RCC_BDCR_LSEON
@@ -90,8 +94,13 @@ void stmclk_enable_lfclk(void)
         stmclk_dbp_lock();
     }
     else {
+#if defined(CPU_FAM_STM32C0)
+        RCC->CSR2 |= RCC_CSR2_LSION;
+        while (!(RCC->CSR2 & RCC_CSR2_LSIRDY)) {}
+#else
         RCC->CSR |= RCC_CSR_LSION;
         while (!(RCC->CSR & RCC_CSR_LSIRDY)) {}
+#endif
     }
 }
 
@@ -104,25 +113,37 @@ void stmclk_disable_lfclk(void)
         stmclk_dbp_lock();
     }
     else {
+#if defined(CPU_FAM_STM32C0)
+        RCC->CSR2 &= ~(RCC_CSR2_LSION);
+#else
         RCC->CSR &= ~(RCC_CSR_LSION);
+#endif
     }
 }
 
 void stmclk_dbp_unlock(void)
 {
+#if !defined(CPU_FAM_STM32C0) /* CPU_FAM_STM32C0 does not support DBP */
     PWR->REG_PWR_CR |= BIT_CR_DBP;
+#endif
 }
 
 void stmclk_dbp_lock(void)
 {
+#if !defined(CPU_FAM_STM32C0) /* CPU_FAM_STM32C0 does not support DBP */
     if (!IS_ACTIVE(CPU_HAS_BACKUP_RAM)) {
 /*  The DBP must be unlocked all the time, if we modify
     backup RAM content by comfortable BACKUP_RAM variables */
         PWR->REG_PWR_CR &= ~(BIT_CR_DBP);
     }
+#endif
 }
 
 bool stmclk_dbp_is_locked(void)
 {
+#if !defined(CPU_FAM_STM32C0) /* CPU_FAM_STM32C0 does not support DBP */
     return !(PWR->REG_PWR_CR & BIT_CR_DBP);
+#else
+    return 0;
+#endif
 }
diff --git a/dist/tools/doccheck/exclude_simple b/dist/tools/doccheck/exclude_simple
index 362f0057dc..ebbd216432 100644
--- a/dist/tools/doccheck/exclude_simple
+++ b/dist/tools/doccheck/exclude_simple
@@ -1545,12 +1545,12 @@ warning: Member CONFIG_CLOCK_APB3_DIV (macro definition) of file cfg_clock_defau
 warning: Member CONFIG_CLOCK_DESIRED_FREQUENCY (macro definition) of file clk_conf.h is not documented.
 warning: Member CONFIG_CLOCK_HFROSC_DIV (macro definition) of file clk_conf.h is not documented.
 warning: Member CONFIG_CLOCK_HFROSC_TRIM (macro definition) of file clk_conf.h is not documented.
-warning: Member CONFIG_CLOCK_HSE (macro definition) of file cfg_clock_common_fx_gx_mp1.h is not documented.
+warning: Member CONFIG_CLOCK_HSE (macro definition) of file cfg_clock_common_fx_gx_mp1_c0.h is not documented.
 warning: Member CONFIG_CLOCK_HSE (macro definition) of file cfg_clock_common_lx_u5_wx.h is not documented.
 warning: Member CONFIG_CLOCK_HSE (macro definition) of file cfg_clock_common_lx_wx.h is not documented.
 warning: Member CONFIG_CLOCK_HSE (macro definition) of file periph_conf_common.h is not documented.
 warning: Member CONFIG_CLOCK_HSE (macro definition) of file periph_conf.h is not documented.
-warning: Member CONFIG_CLOCK_HSI (macro definition) of file cfg_clock_common_fx_gx_mp1.h is not documented.
+warning: Member CONFIG_CLOCK_HSI (macro definition) of file cfg_clock_common_fx_gx_mp1_c0.h is not documented.
 warning: Member CONFIG_CLOCK_HSI (macro definition) of file cfg_clock_common_lx_u5_wx.h is not documented.
 warning: Member CONFIG_CLOCK_HSI (macro definition) of file cfg_clock_common_lx_wx.h is not documented.
 warning: Member CONFIG_CLOCK_MCU_DIV (macro definition) of file cfg_clock_default.h is not documented.
@@ -1608,7 +1608,7 @@ warning: Member CONFIG_USE_CLOCK_HFROSC (macro definition) of file clk_conf.h is
 warning: Member CONFIG_USE_CLOCK_HFROSC_PLL (macro definition) of file clk_conf.h is not documented.
 warning: Member CONFIG_USE_CLOCK_HFXOSC (macro definition) of file clk_conf.h is not documented.
 warning: Member CONFIG_USE_CLOCK_HFXOSC_PLL (macro definition) of file clk_conf.h is not documented.
-warning: Member CONFIG_USE_CLOCK_PLL (macro definition) of file cfg_clock_common_fx_gx_mp1.h is not documented.
+warning: Member CONFIG_USE_CLOCK_PLL (macro definition) of file cfg_clock_common_fx_gx_mp1_c0.h is not documented.
 warning: Member CONFIG_USE_CLOCK_PLL (macro definition) of file cfg_clock_common_lx_u5_wx.h is not documented.
 warning: Member CONFIG_USE_CLOCK_PLL (macro definition) of file cfg_clock_common_lx_wx.h is not documented.
 warning: Member CONFIG_ZTIMER_LPTIMER_BLOCK_PM_MODE (macro definition) of file board.h is not documented.