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cpu/sam0_common: fix vendor header files

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Ran the `fix_headers.sh` to fix the vendor header files and removed
the no longer needed work around for them.
This commit is contained in:
Marian Buschsieweke 2024-01-31 14:44:26 +01:00
parent 1425dc0652
commit b42b1998ec
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GPG Key ID: 77AA882EC78084E6
10 changed files with 0 additions and 24 deletions
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15
cpu/sam0_common/include/cpu_conf.h
View File

@ -23,12 +23,6 @@
#include "cpu_conf_common.h"
/* Workaround redefinition of LITTLE_ENDIAN macro (part1) */
#ifdef LITTLE_ENDIAN
#define __TMP_LITTLE_ENDIAN LITTLE_ENDIAN
#undef LITTLE_ENDIAN
#endif
#if defined(CPU_SAMD10)
#include "vendor/samd10/include/samd10.h"
#elif defined(CPU_SAMD20)
@ -63,15 +57,6 @@
#include "vendor/samr34/include/samr34.h"
#endif
/* Workaround redefinition of LITTLE_ENDIAN macro (part2) */
#ifdef LITTLE_ENDIAN
#undef LITTLE_ENDIAN
#endif
#ifdef __TMP_LITTLE_ENDIAN
#define LITTLE_ENDIAN __TMP_LITTLE_ENDIAN
#endif
#ifdef __cplusplus
extern "C" {
#endif

1
cpu/sam0_common/include/vendor/samr21/include/samr21e16a.h vendored
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@ -216,7 +216,6 @@ void PTC_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */

1
cpu/sam0_common/include/vendor/samr21/include/samr21e17a.h vendored
View File

@ -216,7 +216,6 @@ void PTC_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */

1
cpu/sam0_common/include/vendor/samr21/include/samr21e18a.h vendored
View File

@ -216,7 +216,6 @@ void PTC_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */

1
cpu/sam0_common/include/vendor/samr21/include/samr21e19a.h vendored
View File

@ -216,7 +216,6 @@ void PTC_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */

1
cpu/sam0_common/include/vendor/samr21/include/samr21g16a.h vendored
View File

@ -216,7 +216,6 @@ void PTC_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */

1
cpu/sam0_common/include/vendor/samr21/include/samr21g17a.h vendored
View File

@ -216,7 +216,6 @@ void PTC_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */

1
cpu/sam0_common/include/vendor/samr21/include/samr21g18a.h vendored
View File

@ -216,7 +216,6 @@ void PTC_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */

1
cpu/sam0_common/include/vendor/samr30/include/samr30e18a.h vendored
View File

@ -234,7 +234,6 @@ void PTC_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */

1
cpu/sam0_common/include/vendor/samr30/include/samr30g18a.h vendored
View File

@ -234,7 +234,6 @@ void PTC_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */