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boards: add WeAct-f411ce board
The WeAct-F411CE is a blackpill-like board with a STM32F411CE. It can be flashed using the vendor-provided bootloader.
This commit is contained in:
Benjamin Valentin
Benjamin Valentin
parent
a3f8a381ab
commit
b20ec93991
66
boards/common/stm32/include/f4/cfg_clock_96_25_1.h
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66
boards/common/stm32/include/f4/cfg_clock_96_25_1.h
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@ -0,0 +1,66 @@
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/*
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* Copyright (C) 2018 Freie Universität Berlin
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* 2017 OTA keys S.A.
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* 2018 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_common_stm32
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* @{
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*
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* @file
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* @brief Configure STM32F4 clock to 96MHz using PLL
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Vincent Dupont <vincent@otakeys.com>
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*/
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#ifndef F4_CFG_CLOCK_96_25_1_H
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#define F4_CFG_CLOCK_96_25_1_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock settings
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*
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* @note This is auto-generated from
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* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
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* @{
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*/
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/* give the target core clock (HCLK) frequency [in Hz],
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* maximum: 100MHz */
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#define CLOCK_CORECLOCK (96000000U)
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/* 0: no external high speed crystal available
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* else: actual crystal frequency [in Hz] */
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#define CLOCK_HSE (25000000U)
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/* 0: no external low speed crystal available,
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* 1: external crystal available (always 32.768kHz) */
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#define CLOCK_LSE (1U)
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/* peripheral clock setup */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 50MHz */
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 100MHz */
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
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/* Main PLL factors */
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#define CLOCK_PLL_M (25)
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#define CLOCK_PLL_N (384)
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#define CLOCK_PLL_P (4)
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#define CLOCK_PLL_Q (8)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* F4_CFG_CLOCK_96_25_1_H */
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/** @} */
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3
boards/weact-f411ce/Makefile
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3
boards/weact-f411ce/Makefile
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@ -0,0 +1,3 @@
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MODULE = board
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include $(RIOTBASE)/Makefile.base
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11
boards/weact-f411ce/Makefile.dep
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11
boards/weact-f411ce/Makefile.dep
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@ -0,0 +1,11 @@
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ifneq (,$(filter saul_default,$(USEMODULE)))
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USEMODULE += saul_gpio
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endif
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ifeq (,$(filter stdio_% slipdev_stdio,$(USEMODULE)))
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USEMODULE += stdio_cdc_acm
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endif
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ifneq (,$(filter mtd,$(USEMODULE)))
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USEMODULE += mtd_spi_nor
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endif
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12
boards/weact-f411ce/Makefile.features
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12
boards/weact-f411ce/Makefile.features
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@ -0,0 +1,12 @@
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CPU = stm32
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CPU_MODEL = stm32f411ceu6
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# Put defined MCU peripherals here (in alphabetical order)
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FEATURES_PROVIDED += periph_adc
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FEATURES_PROVIDED += periph_i2c
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FEATURES_PROVIDED += periph_pwm
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FEATURES_PROVIDED += periph_rtc
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FEATURES_PROVIDED += periph_spi
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FEATURES_PROVIDED += periph_timer
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FEATURES_PROVIDED += periph_uart
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FEATURES_PROVIDED += periph_usbdev
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10
boards/weact-f411ce/Makefile.include
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10
boards/weact-f411ce/Makefile.include
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INCLUDES += -I$(RIOTBOARD)/common/stm32/include
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# default to flashing over USB
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PROGRAMMER ?= dfu-util
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DFU_USB_ID ?= 0483:df11
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DFU_FLAGS ?= -a 0 -s 0x08000000:leave
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ROM_OFFSET ?= 0x0
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# Setup of programmer and serial is shared between STM32 based boards
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include $(RIOTMAKE)/boards/stm32.inc.mk
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63
boards/weact-f411ce/board.c
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63
boards/weact-f411ce/board.c
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@ -0,0 +1,63 @@
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/*
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* Copyright (C) 2019 Benjamin Valentin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_weact-f411ce
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* @{
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*
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* @file
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* @brief Board initialization code for the WeAct-F411CE board.
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*
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* @author Benjamin Valentin <benpicco@googlemail.com>
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*
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* @}
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*/
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#include "board.h"
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#include "cpu.h"
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#include "mtd.h"
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#include "mtd_spi_nor.h"
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#include "periph/gpio.h"
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#ifdef MODULE_MTD
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/* AT25SF041 */
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static const mtd_spi_nor_params_t _weact_nor_params = {
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.opcode = &mtd_spi_nor_opcode_default,
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.wait_chip_erase = 4800LU * US_PER_MS,
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.wait_32k_erase = 300LU * US_PER_MS,
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.wait_sector_erase = 70LU * US_PER_MS,
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.wait_4k_erase = 70LU * US_PER_MS,
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.wait_chip_wake_up = 1LU * US_PER_MS,
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.clk = WEACT_411CE_NOR_SPI_CLK,
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.flag = WEACT_411CE_NOR_FLAGS,
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.spi = WEACT_411CE_NOR_SPI_DEV,
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.mode = WEACT_411CE_NOR_SPI_MODE,
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.cs = WEACT_411CE_NOR_SPI_CS,
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.addr_width = 3,
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};
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static mtd_spi_nor_t weact_nor_dev = {
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.base = {
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.driver = &mtd_spi_nor_driver,
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.page_size = WEACT_411CE_NOR_PAGE_SIZE,
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.pages_per_sector = WEACT_411CE_NOR_PAGES_PER_SECTOR,
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.sector_count = WEACT_411CE_NOR_SECTOR_COUNT,
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},
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.params = &_weact_nor_params,
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};
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mtd_dev_t *mtd0 = (mtd_dev_t *)&weact_nor_dev;
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#endif /* MODULE_MTD */
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void board_init(void)
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{
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cpu_init();
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gpio_init(LED0_PIN, GPIO_OUT);
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LED0_OFF;
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}
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66
boards/weact-f411ce/doc.txt
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66
boards/weact-f411ce/doc.txt
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@ -0,0 +1,66 @@
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/**
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@defgroup boards_weact-f411ce WeAct-F411CE board
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@ingroup boards
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@brief Support for the WeAct-F411CE Board
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## Overview
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WeAct-F411CE is a board with the same form-factor as the blue/blackpill,
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but with an STM32F411CEU6 and a USB-C connector.
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It is available on sites like AliExpress for less than 4€.
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## Hardware
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### MCU
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| MCU | STM32F411CE |
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|:---------------- |:--------------------- |
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| Family | ARM Cortex-M4F |
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| Vendor | ST Microelectronics |
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| RAM | 128KiB |
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| Flash | 512KiB |
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| Frequency | up to 100MHz |
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| FPU | yes |
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| Timers | 8 (2x watchdog, 1 SysTick, 6x 16-bit) |
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| ADCs | 1x 12-bit |
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| UARTs | 3 |
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| SPIs | 5 |
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| I2Cs | 3 |
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| RTC | 1 |
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| Vcc | 2.0V - 3.6V |
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| Datasheet | [Datasheet](https://www.st.com/resource/en/datasheet/stm32f411ce.pdf) |
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| Reference Manual | [Reference Manual](https://www.st.com/content/ccc/resource/technical/document/reference_manual/9b/53/39/1c/f7/01/4a/79/DM00119316.pdf/files/DM00119316.pdf/jcr:content/translations/en.DM00119316.pdf) |
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## Flashing the device
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The device comes with a bootloader that allows flashing via `dfu-util`.
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There are two buttons on the board labeled `BOOT0` and `NRST`.
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- Press and hold down `NRST` to reset the CPU
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- Press `BOOT0` while keeping `NRST` held down
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- Release `NRST`, afterwards release `BOOT0`
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The board will now show up as `0483:df11` - `STM32 BOOTLOADER` and will accept
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firmware using the DFU protocol.
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You can upload your RIOT-firmware by typing
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```
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make BOARD=weact-f411ce flash
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```
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*Note:* You need to have write permissions to the device.
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On Linux you could add yourself to the `plugdev` group and store the following as `/etc/udev/rules.d/99-weact-f411ce.rules`:
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```
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SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="df11", GROUP="plugdev", MODE="660"
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```
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## UART
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stdio is provided through USB CDC ACM so the board can be used
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without any extra hardware, save for a USB-C cable.
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*/
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105
boards/weact-f411ce/include/board.h
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105
boards/weact-f411ce/include/board.h
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@ -0,0 +1,105 @@
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/*
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* Copyright (C) 2019 Benjamin Valentin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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||||
* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_weact-f411ce
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*
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* @brief Support for the WeAct-F411CE Board
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* @{
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*
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* @file
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* @brief Pin definitions and board configuration options
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*
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* @author Benjamin Valentin <benpicco@googlemail.com>
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*/
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#ifndef BOARD_H
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#define BOARD_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "mtd.h"
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#include "periph_cpu.h"
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#include "timex.h"
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/**
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* @name Xtimer configuration
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* @{
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*/
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#define XTIMER_BACKOFF (8)
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#define XTIMER_OVERHEAD (6)
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/** @} */
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/**
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* @brief Product & Vendor ID taken from example firmware
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* that the board was shipped with.
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* @{
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*/
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#define INTERNAL_PERIPHERAL_VID (0x0483)
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#define INTERNAL_PERIPHERAL_PID (0x5740)
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/** @} */
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/**
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* @name LED pin definition and handlers
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* @{
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*/
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#define LED0_PORT GPIOC
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#define LED0_PIN GPIO_PIN(PORT_C, 13)
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#define LED0_MASK (1 << 13)
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#define LED0_ON (LED0_PORT->BSRR = (LED0_MASK << 16))
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#define LED0_OFF (LED0_PORT->BSRR = (LED0_MASK << 0))
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#define LED0_TOGGLE (LED0_PORT->ODR ^= LED0_MASK)
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/** @} */
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/**
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* @name User button pin definition
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* @{
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*/
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#define BTN0_PIN GPIO_PIN(PORT_A, 0)
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#define BTN0_MODE GPIO_IN_PU
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/** @} */
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/**
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* @name WeAct-F411CE NOR flash hardware configuration
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*
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* The pad for the NOR Flash (U3) is not populated.
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* You have to solder a serial flash yourself and adjust the parameters.
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* @{
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*/
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#define WEACT_411CE_NOR_PAGE_SIZE (256)
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#define WEACT_411CE_NOR_PAGES_PER_SECTOR (16)
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#define WEACT_411CE_NOR_SECTOR_COUNT (128)
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#define WEACT_411CE_NOR_FLAGS (SPI_NOR_F_SECT_4K | SPI_NOR_F_SECT_32K)
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#define WEACT_411CE_NOR_SPI_DEV SPI_DEV(0)
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#define WEACT_411CE_NOR_SPI_CLK SPI_CLK_10MHZ
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#define WEACT_411CE_NOR_SPI_CS GPIO_PIN(PORT_A, 4)
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#define WEACT_411CE_NOR_SPI_MODE SPI_MODE_0
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/** @} */
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/**
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* @name MTD configuration
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* @{
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*/
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extern mtd_dev_t *mtd0;
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#define MTD_0 mtd0
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/** @} */
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/**
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* @brief Initialize board specific hardware, including clock, LEDs and std-IO
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*/
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void board_init(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* BOARD_H */
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/** @} */
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53
boards/weact-f411ce/include/gpio_params.h
Normal file
53
boards/weact-f411ce/include/gpio_params.h
Normal file
@ -0,0 +1,53 @@
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/*
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* Copyright (C) 2019 Benjamin Valentin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
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*/
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/**
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* @ingroup boards_weact-f411ce
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* @{
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*
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* @file
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* @brief Board specific configuration of direct mapped GPIOs
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*
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* @author Benjamin Valentin <benpicco@googlemail.com>
|
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*/
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#ifndef GPIO_PARAMS_H
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#define GPIO_PARAMS_H
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#include "board.h"
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#include "saul/periph.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief GPIO pin configuration
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*/
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static const saul_gpio_params_t saul_gpio_params[] =
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{
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{
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.name = "LED",
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.pin = LED0_PIN,
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.mode = GPIO_OUT,
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.flags = (SAUL_GPIO_INVERTED | SAUL_GPIO_INIT_CLEAR)
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},
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{
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.name = "KEY",
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.pin = BTN0_PIN,
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.mode = BTN0_MODE,
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.flags = SAUL_GPIO_INVERTED
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},
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /* GPIO_PARAMS_H */
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/** @} */
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201
boards/weact-f411ce/include/periph_conf.h
Normal file
201
boards/weact-f411ce/include/periph_conf.h
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/*
|
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* Copyright (C) 2019 Benjamin Valentin
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||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
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|
||||
/**
|
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* @ingroup boards_weact-f411ce
|
||||
* @{
|
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*
|
||||
* @file
|
||||
* @brief Peripheral MCU configuration for the WeAct-F411CE Board
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
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* @author José Ignacio Alamos <jialamos@uc.cl>
|
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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* @author Benjamin Valentin <benpicco@googlemail.com>
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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#include "f4/cfg_clock_96_25_1.h"
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#include "cfg_i2c1_pb8_pb9.h"
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#include "cfg_timer_tim5.h"
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#include "cfg_usb_otg_fs.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name UART configuration
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* @{
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*/
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static const uart_conf_t uart_config[] = {
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{
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.dev = USART2,
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.rcc_mask = RCC_APB1ENR_USART2EN,
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.rx_pin = GPIO_PIN(PORT_A, 3),
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.tx_pin = GPIO_PIN(PORT_A, 2),
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.rx_af = GPIO_AF7,
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.tx_af = GPIO_AF7,
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.bus = APB1,
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.irqn = USART2_IRQn,
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#ifdef MODULE_PERIPH_DMA
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.dma = DMA_STREAM_UNDEF,
|
||||
.dma_chan = UINT8_MAX,
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#endif
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},
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{
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.dev = USART1,
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.rcc_mask = RCC_APB2ENR_USART1EN,
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||||
.rx_pin = GPIO_PIN(PORT_A, 10),
|
||||
.tx_pin = GPIO_PIN(PORT_A, 9),
|
||||
.rx_af = GPIO_AF7,
|
||||
.tx_af = GPIO_AF7,
|
||||
.bus = APB2,
|
||||
.irqn = USART1_IRQn,
|
||||
#ifdef MODULE_PERIPH_DMA
|
||||
.dma = DMA_STREAM_UNDEF,
|
||||
.dma_chan = UINT8_MAX,
|
||||
#endif
|
||||
},
|
||||
};
|
||||
|
||||
/* assign ISR vector names */
|
||||
#define UART_0_ISR isr_usart2
|
||||
#define UART_1_ISR isr_usart1
|
||||
|
||||
/* deduct number of defined UART interfaces */
|
||||
#define UART_NUMOF ARRAY_SIZE(uart_config)
|
||||
/** @} */
|
||||
|
||||
/** @name PWM configuration
|
||||
* @{
|
||||
*/
|
||||
static const pwm_conf_t pwm_config[] = {
|
||||
{
|
||||
.dev = TIM2,
|
||||
.rcc_mask = RCC_APB1ENR_TIM2EN,
|
||||
.chan = { { .pin = GPIO_PIN(PORT_A, 15), .cc_chan = 0 },
|
||||
{ .pin = GPIO_PIN(PORT_B, 3), /* D3 */ .cc_chan = 1 },
|
||||
{ .pin = GPIO_PIN(PORT_B, 10), /* D6 */ .cc_chan = 2 },
|
||||
{ .pin = GPIO_UNDEF, .cc_chan = 0 } },
|
||||
.af = GPIO_AF1,
|
||||
.bus = APB1
|
||||
},
|
||||
{
|
||||
.dev = TIM3,
|
||||
.rcc_mask = RCC_APB1ENR_TIM3EN,
|
||||
.chan = { { .pin = GPIO_PIN(PORT_B, 4), /* D5 */ .cc_chan = 0 },
|
||||
{ .pin = GPIO_PIN(PORT_C, 7), /* D9 */ .cc_chan = 1 },
|
||||
{ .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2 },
|
||||
{ .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3 } },
|
||||
.af = GPIO_AF2,
|
||||
.bus = APB1
|
||||
},
|
||||
};
|
||||
|
||||
#define PWM_NUMOF ARRAY_SIZE(pwm_config)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name SPI configuration
|
||||
*
|
||||
* @note The spi_divtable is auto-generated from
|
||||
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
|
||||
* @{
|
||||
*/
|
||||
static const uint8_t spi_divtable[2][5] = {
|
||||
{ /* for APB1 @ 48000000Hz */
|
||||
7, /* -> 187500Hz */
|
||||
6, /* -> 375000Hz */
|
||||
5, /* -> 750000Hz */
|
||||
2, /* -> 6000000Hz */
|
||||
1 /* -> 12000000Hz */
|
||||
},
|
||||
{ /* for APB2 @ 96000000Hz */
|
||||
7, /* -> 375000Hz */
|
||||
7, /* -> 375000Hz */
|
||||
6, /* -> 750000Hz */
|
||||
3, /* -> 6000000Hz */
|
||||
2 /* -> 12000000Hz */
|
||||
}
|
||||
};
|
||||
|
||||
static const spi_conf_t spi_config[] = {
|
||||
{ /* U3 - SPI flash */
|
||||
.dev = SPI1,
|
||||
.mosi_pin = GPIO_PIN(PORT_A, 7),
|
||||
.miso_pin = GPIO_PIN(PORT_A, 6),
|
||||
.sclk_pin = GPIO_PIN(PORT_A, 5),
|
||||
.cs_pin = GPIO_PIN(PORT_A, 4),
|
||||
.mosi_af = GPIO_AF5,
|
||||
.miso_af = GPIO_AF5,
|
||||
.sclk_af = GPIO_AF5,
|
||||
.cs_af = GPIO_AF5,
|
||||
.rccmask = RCC_APB2ENR_SPI1EN,
|
||||
.apbbus = APB2
|
||||
},
|
||||
{
|
||||
.dev = SPI2,
|
||||
.mosi_pin = GPIO_PIN(PORT_B, 15),
|
||||
.miso_pin = GPIO_PIN(PORT_B, 14),
|
||||
.sclk_pin = GPIO_PIN(PORT_B, 13),
|
||||
.cs_pin = GPIO_PIN(PORT_B, 12),
|
||||
.mosi_af = GPIO_AF5,
|
||||
.miso_af = GPIO_AF5,
|
||||
.sclk_af = GPIO_AF5,
|
||||
.cs_af = GPIO_AF5,
|
||||
.rccmask = RCC_APB1ENR_SPI2EN,
|
||||
.apbbus = APB1
|
||||
},
|
||||
{
|
||||
.dev = SPI3,
|
||||
.mosi_pin = GPIO_PIN(PORT_B, 5),
|
||||
.miso_pin = GPIO_PIN(PORT_B, 4),
|
||||
.sclk_pin = GPIO_PIN(PORT_B, 3),
|
||||
.cs_pin = GPIO_PIN(PORT_A, 15),
|
||||
.mosi_af = GPIO_AF6,
|
||||
.miso_af = GPIO_AF6,
|
||||
.sclk_af = GPIO_AF6,
|
||||
.cs_af = GPIO_AF6,
|
||||
.rccmask = RCC_APB1ENR_SPI3EN,
|
||||
.apbbus = APB1
|
||||
},
|
||||
};
|
||||
|
||||
#define SPI_NUMOF ARRAY_SIZE(spi_config)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name ADC configuration
|
||||
*
|
||||
* Note that we do not configure all ADC channels,
|
||||
* and not in the STM32F411 order.
|
||||
* Feel free to add more if needed.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_CONFIG { \
|
||||
{GPIO_PIN(PORT_A, 0), 0, 0}, \
|
||||
{GPIO_PIN(PORT_A, 1), 0, 1}, \
|
||||
{GPIO_PIN(PORT_A, 4), 0, 4}, \
|
||||
{GPIO_PIN(PORT_B, 0), 0, 8}, \
|
||||
}
|
||||
|
||||
#define ADC_NUMOF (4)
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PERIPH_CONF_H */
|
||||
/** @} */
|
||||
Loading…
Reference in New Issue
Block a user