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boards/spark-core: adapted UART configuration

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This commit is contained in:
Hauke Petersen 2016-03-16 10:33:17 +01:00
parent b458b9af88
commit b0606a7e11
1 changed files with 15 additions and 11 deletions
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26
boards/spark-core/include/periph_conf.h
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@ -39,6 +39,9 @@
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 72MHz */
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 72MHz */
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* APB1 clock -> 36MHz */
/* resulting bus clocks */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2 (CLOCK_CORECLOCK)
/* configuration of flash access cycles */
#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_2
/** @} */
@ -70,19 +73,20 @@ static const timer_conf_t timer_config[] = {
* @brief UART configuration
* @{
*/
#define UART_NUMOF (1U)
#define UART_0_EN 1
#define UART_IRQ_PRIO 1
static const uart_conf_t uart_config[] = {
{
.dev = USART2,
.rx_pin = GPIO_PIN(PORT_A, 3),
.tx_pin = GPIO_PIN(PORT_A, 2),
.rcc_pin = RCC_APB1ENR_USART2EN,
.bus = APB1,
.irqn = USART2_IRQn
}
};
/* UART 0 device configuration */
#define UART_0_DEV USART2
#define UART_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_USART2EN)
#define UART_0_IRQ USART2_IRQn
#define UART_0_ISR isr_usart2
#define UART_0_BUS_FREQ (CLOCK_CORECLOCK/2)
/* UART 0 pin configuration */
#define UART_0_RX_PIN GPIO_PIN(PORT_A,3)
#define UART_0_TX_PIN GPIO_PIN(PORT_A,2)
#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
/** @} */
/**