From afd3de20431038ef624137b54541a85bbc87f51d Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Mon, 28 Sep 2020 17:01:55 +0200 Subject: [PATCH] boards/nucleo-l552ze-q: add initial support --- boards/nucleo-l552ze-q/Kconfig | 30 +++++ boards/nucleo-l552ze-q/Makefile | 4 + boards/nucleo-l552ze-q/Makefile.dep | 3 + boards/nucleo-l552ze-q/Makefile.features | 14 +++ boards/nucleo-l552ze-q/Makefile.include | 2 + boards/nucleo-l552ze-q/doc.txt | 26 +++++ boards/nucleo-l552ze-q/include/periph_conf.h | 110 +++++++++++++++++++ 7 files changed, 189 insertions(+) create mode 100644 boards/nucleo-l552ze-q/Kconfig create mode 100644 boards/nucleo-l552ze-q/Makefile create mode 100644 boards/nucleo-l552ze-q/Makefile.dep create mode 100644 boards/nucleo-l552ze-q/Makefile.features create mode 100644 boards/nucleo-l552ze-q/Makefile.include create mode 100644 boards/nucleo-l552ze-q/doc.txt create mode 100644 boards/nucleo-l552ze-q/include/periph_conf.h diff --git a/boards/nucleo-l552ze-q/Kconfig b/boards/nucleo-l552ze-q/Kconfig new file mode 100644 index 0000000000..bc415b5b3a --- /dev/null +++ b/boards/nucleo-l552ze-q/Kconfig @@ -0,0 +1,30 @@ +# Copyright (c) 2020 Inria +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +config BOARD + default "nucleo-l552ze-q" if BOARD_NUCLEO_L552ZE_Q + +config BOARD_NUCLEO_L552ZE_Q + bool + default y + select BOARD_COMMON_NUCLEO144 + select CPU_MODEL_STM32L552ZE + + # Put defined MCU peripherals here (in alphabetical order) + select HAS_PERIPH_I2C + select HAS_PERIPH_LPUART + select HAS_PERIPH_SPI + select HAS_PERIPH_TIMER + select HAS_PERIPH_UART + + # Put other features for this board (in alphabetical order) + select HAS_RIOTBOOT + + # Clock configuration + select BOARD_HAS_LSE + +source "$(RIOTBOARD)/common/nucleo144/Kconfig" diff --git a/boards/nucleo-l552ze-q/Makefile b/boards/nucleo-l552ze-q/Makefile new file mode 100644 index 0000000000..4dd17b1d0c --- /dev/null +++ b/boards/nucleo-l552ze-q/Makefile @@ -0,0 +1,4 @@ +MODULE = board +DIRS = $(RIOTBOARD)/common/nucleo + +include $(RIOTBASE)/Makefile.base diff --git a/boards/nucleo-l552ze-q/Makefile.dep b/boards/nucleo-l552ze-q/Makefile.dep new file mode 100644 index 0000000000..f41bf0f86b --- /dev/null +++ b/boards/nucleo-l552ze-q/Makefile.dep @@ -0,0 +1,3 @@ +FEATURES_REQUIRED += periph_lpuart + +include $(RIOTBOARD)/common/nucleo/Makefile.dep diff --git a/boards/nucleo-l552ze-q/Makefile.features b/boards/nucleo-l552ze-q/Makefile.features new file mode 100644 index 0000000000..80cb0a23bd --- /dev/null +++ b/boards/nucleo-l552ze-q/Makefile.features @@ -0,0 +1,14 @@ +CPU = stm32 +CPU_MODEL = stm32l552ze + +# Put defined MCU peripherals here (in alphabetical order) +FEATURES_PROVIDED += periph_i2c +FEATURES_PROVIDED += periph_spi +FEATURES_PROVIDED += periph_timer +FEATURES_PROVIDED += periph_uart periph_lpuart + +# Put other features for this board (in alphabetical order) +FEATURES_PROVIDED += riotboot + +# load the common Makefile.features for Nucleo boards +include $(RIOTBOARD)/common/nucleo144/Makefile.features diff --git a/boards/nucleo-l552ze-q/Makefile.include b/boards/nucleo-l552ze-q/Makefile.include new file mode 100644 index 0000000000..a7e3adb0d8 --- /dev/null +++ b/boards/nucleo-l552ze-q/Makefile.include @@ -0,0 +1,2 @@ +# load the common Makefile.include for Nucleo boards +include $(RIOTBOARD)/common/nucleo144/Makefile.include diff --git a/boards/nucleo-l552ze-q/doc.txt b/boards/nucleo-l552ze-q/doc.txt new file mode 100644 index 0000000000..74394eea4e --- /dev/null +++ b/boards/nucleo-l552ze-q/doc.txt @@ -0,0 +1,26 @@ +/** +@defgroup boards_nucleo-l552ze-q STM32 Nucleo-L552ZE-Q +@ingroup boards_common_nucleo144 +@brief Support for the STM32 Nucleo-L552ZE-Q + +## Flashing the device + +The ST Nucleo-L552ZE-Q board includes an on-board ST-LINK V2.1 programmer. The +easiest way to program the board is to use OpenOCD. Once you have installed +OpenOCD (look [here](https://github.com/RIOT-OS/RIOT/wiki/OpenOCD) for +installation instructions), you can flash the board simply by typing + +``` +make BOARD=nucleo-l552ze-q flash +``` +and debug via GDB by simply typing +``` +make BOARD=nucleo-l552ze-q debug +``` + +## Supported Toolchains + +For using the ST Nucleo-L552ZE-Q board we recommend the usage of the +[GNU Tools for ARM Embedded Processors](https://launchpad.net/gcc-arm-embedded) +toolchain. + */ diff --git a/boards/nucleo-l552ze-q/include/periph_conf.h b/boards/nucleo-l552ze-q/include/periph_conf.h new file mode 100644 index 0000000000..985c14a895 --- /dev/null +++ b/boards/nucleo-l552ze-q/include/periph_conf.h @@ -0,0 +1,110 @@ +/* + * Copyright (C) 2020 Inria + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup boards_nucleo-l552ze-q + * @{ + * + * @file + * @brief Peripheral MCU configuration for the nucleo-l552ze-q board + * + * @author Alexandre Abadie + */ + +#ifndef PERIPH_CONF_H +#define PERIPH_CONF_H + +/* Add specific clock configuration (HSE, LSE) for this board here */ +#define CLOCK_CORECLOCK_MAX MHZ(110) + +/* Reach 108MHz by by default setting custom PLL_N factor */ +#ifndef CONFIG_CLOCK_PLL_N +#define CONFIG_CLOCK_PLL_N 27 +#endif + +/* Add specific clock configuration (HSE, LSE) for this board here */ +#ifndef CONFIG_BOARD_HAS_LSE +#define CONFIG_BOARD_HAS_LSE 1 +#endif + +#include "periph_cpu.h" +#include "l4/cfg_clock_default.h" +#include "cfg_i2c1_pb8_pb9.h" +#include "cfg_rtt_default.h" +#include "cfg_timer_tim5.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name UART configuration + * @{ + */ +static const uart_conf_t uart_config[] = { + { + .dev = LPUART1, + .rcc_mask = RCC_APB1ENR2_LPUART1EN, + .rx_pin = GPIO_PIN(PORT_G, 8), + .tx_pin = GPIO_PIN(PORT_G, 7), + .rx_af = GPIO_AF8, + .tx_af = GPIO_AF8, + .bus = APB12, + .irqn = LPUART1_IRQn, + .type = STM32_LPUART, + .clk_src = 0, /* Use APB clock */ + }, + { /* Connected to Arduino D0/D1 */ + .dev = USART3, + .rcc_mask = RCC_APB1ENR1_USART3EN, + .rx_pin = GPIO_PIN(PORT_D, 9), + .tx_pin = GPIO_PIN(PORT_D, 8), + .rx_af = GPIO_AF7, + .tx_af = GPIO_AF7, + .bus = APB1, + .irqn = USART3_IRQn, + .type = STM32_USART, + .clk_src = 0, /* Use APB clock */ + }, +}; + +#define UART_0_ISR (isr_lpuart1) +#define UART_1_ISR (isr_usart3) + +#define UART_NUMOF ARRAY_SIZE(uart_config) +/** @} */ + +/** + * @name SPI configuration + * @{ + */ +static const spi_conf_t spi_config[] = { + { + .dev = SPI1, + .mosi_pin = GPIO_PIN(PORT_A, 7), /* Arduino D11 */ + .miso_pin = GPIO_PIN(PORT_A, 6), /* Arduino D12 */ + .sclk_pin = GPIO_PIN(PORT_A, 5), /* Arduino D13 */ + .cs_pin = GPIO_UNDEF, + .mosi_af = GPIO_AF5, + .miso_af = GPIO_AF5, + .sclk_af = GPIO_AF5, + .cs_af = GPIO_AF5, + .rccmask = RCC_APB2ENR_SPI1EN, + .apbbus = APB2, + }, +}; + +#define SPI_NUMOF ARRAY_SIZE(spi_config) +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* PERIPH_CONF_H */ +/** @} */