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cpu/stm32/l4: add ADC support for l496zg
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@ -27,7 +27,8 @@ extern "C" {
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/**
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/**
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* @brief Available number of ADC devices
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* @brief Available number of ADC devices
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*/
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*/
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#if defined(CPU_MODEL_STM32L476RG) || defined(CPU_MODEL_STM32L475VG)
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#if defined(CPU_MODEL_STM32L476RG) || defined(CPU_MODEL_STM32L475VG) || \
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defined(CPU_MODEL_STM32L496ZG)
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#define ADC_DEVS (3U)
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#define ADC_DEVS (3U)
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#elif defined(CPU_MODEL_STM32L452RE) || defined(CPU_MODEL_STM32L432KC) || \
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#elif defined(CPU_MODEL_STM32L452RE) || defined(CPU_MODEL_STM32L432KC) || \
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defined(CPU_MODEL_STM32L4R5ZI)
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defined(CPU_MODEL_STM32L4R5ZI)
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@ -36,7 +37,7 @@ extern "C" {
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#if defined(CPU_MODEL_STM32L476RG) || defined(CPU_MODEL_STM32L475VG) || \
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#if defined(CPU_MODEL_STM32L476RG) || defined(CPU_MODEL_STM32L475VG) || \
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defined(CPU_MODEL_STM32L452RE) || defined(CPU_MODEL_STM32L432KC) || \
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defined(CPU_MODEL_STM32L452RE) || defined(CPU_MODEL_STM32L432KC) || \
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defined(CPU_MODEL_STM32L4R5ZI)
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defined(CPU_MODEL_STM32L496ZG) || defined(CPU_MODEL_STM32L4R5ZI)
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/**
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/**
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* @brief ADC voltage regulator start-up time [us]
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* @brief ADC voltage regulator start-up time [us]
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*/
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*/
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@ -42,7 +42,8 @@
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/**
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/**
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* @brief map CPU specific register/value names
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* @brief map CPU specific register/value names
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*/
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*/
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#if defined(CPU_MODEL_STM32L476RG) || defined(CPU_MODEL_STM32L4R5ZI)
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#if defined(CPU_MODEL_STM32L476RG) || defined(CPU_MODEL_STM32L4R5ZI) || \
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defined(CPU_MODEL_STM32L496ZG)
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#define ADC_CR_REG CR
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#define ADC_CR_REG CR
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#define ADC_ISR_REG ISR
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#define ADC_ISR_REG ISR
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#define ADC_PERIPH_CLK AHB2
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#define ADC_PERIPH_CLK AHB2
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