cpu/efm32: add EFM32GG12 family (generated with EFM2RIOT)

cpu/efm32/Makefile

@@ -7,6 +7,9 @@ DIRS += $(RIOTCPU)/cortexm_common
 ifneq (,$(filter cpu_efm32gg,$(USEMODULE)))
   DIRS += families/efm32gg
 endif
+ifneq (,$(filter cpu_efm32gg12b,$(USEMODULE)))
+  DIRS += families/efm32gg12b
+endif
 ifneq (,$(filter cpu_efm32hg,$(USEMODULE)))
   DIRS += families/efm32hg
 endif

cpu/efm32/families/efm32gg12b/Kconfig

@@ -0,0 +1,398 @@
+# Copyright (c) 2020 HAW Hamburg
+#
+# This file is subject to the terms and conditions of the GNU Lesser
+# General Public License v2.1. See the file LICENSE in the top level
+# directory for more details.
+
+config CPU_FAM_EFM32GG12B
+    bool
+    select CPU_CORE_CORTEX_M4F
+    select CPU_COMMON_EFM32
+    select CPU_EFM32_SERIES1
+    select HAS_PERIPH_HWRNG
+    select HAS_CORTEXM_MPU
+
+config MODULE_CPU_EFM32GG12B
+    bool
+    depends on CPU_FAM_EFM32GG12B
+    depends on TEST_KCONFIG
+    default y
+    help
+        EFM32GG12B family-specific code.
+
+## CPU Models
+config CPU_MODEL_EFM32GG12B810F1024GL112
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B830F512GM64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B430F512IQ100
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B830F512IQ64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B830F512IL120
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B390F1024GL112
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B410F1024IM64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B410F1024GQ64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B130F512IQ64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B130F512GM64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B530F512IL112
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B110F1024IQ64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B110F1024GM64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B530F512IQ100
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B410F1024IL120
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B510F1024GL120
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B430F512GM64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B430F512IQ64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B510F1024GQ64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B510F1024IM64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B430F512IL112
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B810F1024GQ100
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B510F1024GL112
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B530F512GQ64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B530F512IM64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B410F1024IL112
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B810F1024IM64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B810F1024GQ64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B830F512IQ100
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B430F512IL120
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B830F512IL112
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B810F1024GL120
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B530F512IL120
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B410F1024IQ100
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B510F1024GQ100
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B830F512GL112
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B810F1024IL120
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B530F512GL120
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B310F1024GL112
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B810F1024GM64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B810F1024IQ64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B530F512IQ64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B530F512GM64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B410F1024GQ100
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B510F1024IQ100
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B510F1024IL112
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B410F1024GL112
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B310F1024GQ100
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B390F512GL112
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B430F512GL120
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B830F512GQ100
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B530F512GQ100
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B130F512GQ64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B410F1024GL120
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B130F512IM64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B410F1024GM64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B410F1024IQ64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B510F1024IL120
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B430F512GL112
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B830F512IM64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B330F512GL112
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B830F512GQ64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B810F1024IQ100
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B810F1024IL112
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B830F512GL120
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B430F512GQ100
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B330F512GQ100
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B510F1024IQ64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B510F1024GM64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B430F512IM64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B430F512GQ64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B110F1024GQ64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B110F1024IM64
+    bool
+    select CPU_FAM_EFM32GG12B
+
+config CPU_MODEL_EFM32GG12B530F512GL112
+    bool
+    select CPU_FAM_EFM32GG12B
+
+## Common CPU symbols
+config CPU_FAM
+    default "efm32gg12b" if CPU_FAM_EFM32GG12B
+
+config CPU_MODEL
+    default "efm32gg12b810f1024gl112" if CPU_MODEL_EFM32GG12B810F1024GL112
+    default "efm32gg12b830f512gm64"   if CPU_MODEL_EFM32GG12B830F512GM64
+    default "efm32gg12b430f512iq100"  if CPU_MODEL_EFM32GG12B430F512IQ100
+    default "efm32gg12b830f512iq64"   if CPU_MODEL_EFM32GG12B830F512IQ64
+    default "efm32gg12b830f512il120"  if CPU_MODEL_EFM32GG12B830F512IL120
+    default "efm32gg12b390f1024gl112" if CPU_MODEL_EFM32GG12B390F1024GL112
+    default "efm32gg12b410f1024im64"  if CPU_MODEL_EFM32GG12B410F1024IM64
+    default "efm32gg12b410f1024gq64"  if CPU_MODEL_EFM32GG12B410F1024GQ64
+    default "efm32gg12b130f512iq64"   if CPU_MODEL_EFM32GG12B130F512IQ64
+    default "efm32gg12b130f512gm64"   if CPU_MODEL_EFM32GG12B130F512GM64
+    default "efm32gg12b530f512il112"  if CPU_MODEL_EFM32GG12B530F512IL112
+    default "efm32gg12b110f1024iq64"  if CPU_MODEL_EFM32GG12B110F1024IQ64
+    default "efm32gg12b110f1024gm64"  if CPU_MODEL_EFM32GG12B110F1024GM64
+    default "efm32gg12b530f512iq100"  if CPU_MODEL_EFM32GG12B530F512IQ100
+    default "efm32gg12b410f1024il120" if CPU_MODEL_EFM32GG12B410F1024IL120
+    default "efm32gg12b510f1024gl120" if CPU_MODEL_EFM32GG12B510F1024GL120
+    default "efm32gg12b430f512gm64"   if CPU_MODEL_EFM32GG12B430F512GM64
+    default "efm32gg12b430f512iq64"   if CPU_MODEL_EFM32GG12B430F512IQ64
+    default "efm32gg12b510f1024gq64"  if CPU_MODEL_EFM32GG12B510F1024GQ64
+    default "efm32gg12b510f1024im64"  if CPU_MODEL_EFM32GG12B510F1024IM64
+    default "efm32gg12b430f512il112"  if CPU_MODEL_EFM32GG12B430F512IL112
+    default "efm32gg12b810f1024gq100" if CPU_MODEL_EFM32GG12B810F1024GQ100
+    default "efm32gg12b510f1024gl112" if CPU_MODEL_EFM32GG12B510F1024GL112
+    default "efm32gg12b530f512gq64"   if CPU_MODEL_EFM32GG12B530F512GQ64
+    default "efm32gg12b530f512im64"   if CPU_MODEL_EFM32GG12B530F512IM64
+    default "efm32gg12b410f1024il112" if CPU_MODEL_EFM32GG12B410F1024IL112
+    default "efm32gg12b810f1024im64"  if CPU_MODEL_EFM32GG12B810F1024IM64
+    default "efm32gg12b810f1024gq64"  if CPU_MODEL_EFM32GG12B810F1024GQ64
+    default "efm32gg12b830f512iq100"  if CPU_MODEL_EFM32GG12B830F512IQ100
+    default "efm32gg12b430f512il120"  if CPU_MODEL_EFM32GG12B430F512IL120
+    default "efm32gg12b830f512il112"  if CPU_MODEL_EFM32GG12B830F512IL112
+    default "efm32gg12b810f1024gl120" if CPU_MODEL_EFM32GG12B810F1024GL120
+    default "efm32gg12b530f512il120"  if CPU_MODEL_EFM32GG12B530F512IL120
+    default "efm32gg12b410f1024iq100" if CPU_MODEL_EFM32GG12B410F1024IQ100
+    default "efm32gg12b510f1024gq100" if CPU_MODEL_EFM32GG12B510F1024GQ100
+    default "efm32gg12b830f512gl112"  if CPU_MODEL_EFM32GG12B830F512GL112
+    default "efm32gg12b810f1024il120" if CPU_MODEL_EFM32GG12B810F1024IL120
+    default "efm32gg12b530f512gl120"  if CPU_MODEL_EFM32GG12B530F512GL120
+    default "efm32gg12b310f1024gl112" if CPU_MODEL_EFM32GG12B310F1024GL112
+    default "efm32gg12b810f1024gm64"  if CPU_MODEL_EFM32GG12B810F1024GM64
+    default "efm32gg12b810f1024iq64"  if CPU_MODEL_EFM32GG12B810F1024IQ64
+    default "efm32gg12b530f512iq64"   if CPU_MODEL_EFM32GG12B530F512IQ64
+    default "efm32gg12b530f512gm64"   if CPU_MODEL_EFM32GG12B530F512GM64
+    default "efm32gg12b410f1024gq100" if CPU_MODEL_EFM32GG12B410F1024GQ100
+    default "efm32gg12b510f1024iq100" if CPU_MODEL_EFM32GG12B510F1024IQ100
+    default "efm32gg12b510f1024il112" if CPU_MODEL_EFM32GG12B510F1024IL112
+    default "efm32gg12b410f1024gl112" if CPU_MODEL_EFM32GG12B410F1024GL112
+    default "efm32gg12b310f1024gq100" if CPU_MODEL_EFM32GG12B310F1024GQ100
+    default "efm32gg12b390f512gl112"  if CPU_MODEL_EFM32GG12B390F512GL112
+    default "efm32gg12b430f512gl120"  if CPU_MODEL_EFM32GG12B430F512GL120
+    default "efm32gg12b830f512gq100"  if CPU_MODEL_EFM32GG12B830F512GQ100
+    default "efm32gg12b530f512gq100"  if CPU_MODEL_EFM32GG12B530F512GQ100
+    default "efm32gg12b130f512gq64"   if CPU_MODEL_EFM32GG12B130F512GQ64
+    default "efm32gg12b410f1024gl120" if CPU_MODEL_EFM32GG12B410F1024GL120
+    default "efm32gg12b130f512im64"   if CPU_MODEL_EFM32GG12B130F512IM64
+    default "efm32gg12b410f1024gm64"  if CPU_MODEL_EFM32GG12B410F1024GM64
+    default "efm32gg12b410f1024iq64"  if CPU_MODEL_EFM32GG12B410F1024IQ64
+    default "efm32gg12b510f1024il120" if CPU_MODEL_EFM32GG12B510F1024IL120
+    default "efm32gg12b430f512gl112"  if CPU_MODEL_EFM32GG12B430F512GL112
+    default "efm32gg12b830f512im64"   if CPU_MODEL_EFM32GG12B830F512IM64
+    default "efm32gg12b330f512gl112"  if CPU_MODEL_EFM32GG12B330F512GL112
+    default "efm32gg12b830f512gq64"   if CPU_MODEL_EFM32GG12B830F512GQ64
+    default "efm32gg12b810f1024iq100" if CPU_MODEL_EFM32GG12B810F1024IQ100
+    default "efm32gg12b810f1024il112" if CPU_MODEL_EFM32GG12B810F1024IL112
+    default "efm32gg12b830f512gl120"  if CPU_MODEL_EFM32GG12B830F512GL120
+    default "efm32gg12b430f512gq100"  if CPU_MODEL_EFM32GG12B430F512GQ100
+    default "efm32gg12b330f512gq100"  if CPU_MODEL_EFM32GG12B330F512GQ100
+    default "efm32gg12b510f1024iq64"  if CPU_MODEL_EFM32GG12B510F1024IQ64
+    default "efm32gg12b510f1024gm64"  if CPU_MODEL_EFM32GG12B510F1024GM64
+    default "efm32gg12b430f512im64"   if CPU_MODEL_EFM32GG12B430F512IM64
+    default "efm32gg12b430f512gq64"   if CPU_MODEL_EFM32GG12B430F512GQ64
+    default "efm32gg12b110f1024gq64"  if CPU_MODEL_EFM32GG12B110F1024GQ64
+    default "efm32gg12b110f1024im64"  if CPU_MODEL_EFM32GG12B110F1024IM64
+    default "efm32gg12b530f512gl112"  if CPU_MODEL_EFM32GG12B530F512GL112

cpu/efm32/families/efm32gg12b/Makefile

@@ -0,0 +1,6 @@
+MODULE = cpu_efm32gg12b
+
+# (file triggers compiler bug. see #5775)
+SRC_NOLTO += vectors.c
+
+include $(RIOTBASE)/Makefile.base

cpu/efm32/families/efm32gg12b/Makefile.include

@@ -0,0 +1,7 @@
+# Find the header file that should exist if the CPU is supported. Only headers
+# for supported boards are included, but to support another CPU, it should be
+# as easy as adding the header file only.
+EFM32_HEADER = $(wildcard $(RIOTCPU)/efm32/families/efm32gg12b/include/vendor/$(CPU_MODEL).h)
+
+# include vendor device headers
+INCLUDES += -I$(RIOTCPU)/efm32/families/efm32gg12b/include/vendor

cpu/efm32/families/efm32gg12b/efm32-info.mk

@@ -0,0 +1,79 @@
+# This file is automatically generated, and should not be changed. There is
+# probably little reason to edit this file anyway, since it should already
+# contain all information for the EFM32GG12B family of CPUs.
+
+# Series - Architecture - Flash base - Flash size - SRAM base - SRAM size - Crypto? - TRNG? - Radio?
+EFM32_INFO_efm32gg12b810f1024gl112 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b830f512gm64   = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b430f512iq100  = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b830f512iq64   = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b830f512il120  = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b390f1024gl112 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b410f1024im64  = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b410f1024gq64  = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b130f512iq64   = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b130f512gm64   = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b530f512il112  = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b110f1024iq64  = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b110f1024gm64  = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b530f512iq100  = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b410f1024il120 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b510f1024gl120 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b430f512gm64   = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b430f512iq64   = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b510f1024gq64  = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b510f1024im64  = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b430f512il112  = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b810f1024gq100 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b510f1024gl112 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b530f512gq64   = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b530f512im64   = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b410f1024il112 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b810f1024im64  = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b810f1024gq64  = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b830f512iq100  = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b430f512il120  = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b830f512il112  = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b810f1024gl120 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b530f512il120  = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b410f1024iq100 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b510f1024gq100 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b830f512gl112  = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b810f1024il120 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b530f512gl120  = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b310f1024gl112 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b810f1024gm64  = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b810f1024iq64  = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b530f512iq64   = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b530f512gm64   = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b410f1024gq100 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b510f1024iq100 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b510f1024il112 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b410f1024gl112 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b310f1024gq100 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b390f512gl112  = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b430f512gl120  = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b830f512gq100  = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b530f512gq100  = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b130f512gq64   = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b410f1024gl120 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b130f512im64   = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b410f1024gm64  = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b410f1024iq64  = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b510f1024il120 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b430f512gl112  = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b830f512im64   = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b330f512gl112  = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b830f512gq64   = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b810f1024iq100 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b810f1024il112 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b830f512gl120  = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b430f512gq100  = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b330f512gq100  = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b510f1024iq64  = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b510f1024gm64  = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b430f512im64   = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b430f512gq64   = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b110f1024gq64  = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b110f1024im64  = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00030000 1 1 0
+EFM32_INFO_efm32gg12b530f512gl112  = 1 cortex-m4f 0x00000000 0x00080000 0x20000000 0x00030000 1 1 0

cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b_af_pins.h

@@ -0,0 +1,325 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32GG12B_AF_PINS register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @addtogroup EFM32GG12B_Alternate_Function Alternate Function
+ * @{
+ * @defgroup EFM32GG12B_AF_Pins Alternate Function Pins
+ * @{
+ ******************************************************************************/
+
+#define AF_CMU_CLK0_PIN(i)          ((i) == 0 ? 2 : (i) == 1 ? 12 : (i) == 2 ? 7 : (i) == 3 ? -1 : (i) == 4 ? 2 : (i) == 5 ? 12 :  -1)                                /**< Pin number for AF_CMU_CLK0 location number i */
+#define AF_CMU_CLK1_PIN(i)          ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? -1 : (i) == 4 ? 3 : (i) == 5 ? 11 :  -1)                                /**< Pin number for AF_CMU_CLK1 location number i */
+#define AF_CMU_CLK2_PIN(i)          ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? -1 : (i) == 4 ? 3 : (i) == 5 ? 10 :  -1)                                 /**< Pin number for AF_CMU_CLK2 location number i */
+#define AF_CMU_CLKI0_PIN(i)         ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 10 : (i) == 6 ? 12 : (i) == 7 ? 11 :  -1) /**< Pin number for AF_CMU_CLKI0 location number i */
+#define AF_CMU_DIGEXTCLK_PIN(i)     ((i) == 0 ? 14 :  -1)                                                                                                             /**< Pin number for AF_CMU_DIGEXTCLK location number i */
+#define AF_CMU_IOPOVR_PIN(i)        ((i) == 0 ? 13 :  -1)                                                                                                             /**< Pin number for AF_CMU_IOPOVR location number i */
+#define AF_CMU_IONOVR_PIN(i)        ((i) == 0 ? 14 :  -1)                                                                                                             /**< Pin number for AF_CMU_IONOVR location number i */
+#define AF_LESENSE_CH0_PIN(i)       ((i) == 0 ? 0 :  -1)                                                                                                              /**< Pin number for AF_LESENSE_CH0 location number i */
+#define AF_LESENSE_CH1_PIN(i)       ((i) == 0 ? 1 :  -1)                                                                                                              /**< Pin number for AF_LESENSE_CH1 location number i */
+#define AF_LESENSE_CH2_PIN(i)       ((i) == 0 ? 2 :  -1)                                                                                                              /**< Pin number for AF_LESENSE_CH2 location number i */
+#define AF_LESENSE_CH3_PIN(i)       ((i) == 0 ? 3 :  -1)                                                                                                              /**< Pin number for AF_LESENSE_CH3 location number i */
+#define AF_LESENSE_CH4_PIN(i)       ((i) == 0 ? 4 :  -1)                                                                                                              /**< Pin number for AF_LESENSE_CH4 location number i */
+#define AF_LESENSE_CH5_PIN(i)       ((i) == 0 ? 5 :  -1)                                                                                                              /**< Pin number for AF_LESENSE_CH5 location number i */
+#define AF_LESENSE_CH6_PIN(i)       ((i) == 0 ? 6 :  -1)                                                                                                              /**< Pin number for AF_LESENSE_CH6 location number i */
+#define AF_LESENSE_CH7_PIN(i)       ((i) == 0 ? 7 :  -1)                                                                                                              /**< Pin number for AF_LESENSE_CH7 location number i */
+#define AF_LESENSE_CH8_PIN(i)       ((i) == 0 ? 8 :  -1)                                                                                                              /**< Pin number for AF_LESENSE_CH8 location number i */
+#define AF_LESENSE_CH9_PIN(i)       ((i) == 0 ? 9 :  -1)                                                                                                              /**< Pin number for AF_LESENSE_CH9 location number i */
+#define AF_LESENSE_CH10_PIN(i)      ((i) == 0 ? 10 :  -1)                                                                                                             /**< Pin number for AF_LESENSE_CH10 location number i */
+#define AF_LESENSE_CH11_PIN(i)      ((i) == 0 ? 11 :  -1)                                                                                                             /**< Pin number for AF_LESENSE_CH11 location number i */
+#define AF_LESENSE_CH12_PIN(i)      ((i) == 0 ? 12 :  -1)                                                                                                             /**< Pin number for AF_LESENSE_CH12 location number i */
+#define AF_LESENSE_CH13_PIN(i)      ((i) == 0 ? 13 :  -1)                                                                                                             /**< Pin number for AF_LESENSE_CH13 location number i */
+#define AF_LESENSE_CH14_PIN(i)      ((i) == 0 ? 14 :  -1)                                                                                                             /**< Pin number for AF_LESENSE_CH14 location number i */
+#define AF_LESENSE_CH15_PIN(i)      ((i) == 0 ? 15 :  -1)                                                                                                             /**< Pin number for AF_LESENSE_CH15 location number i */
+#define AF_LESENSE_ALTEX0_PIN(i)    ((i) == 0 ? 6 :  -1)                                                                                                              /**< Pin number for AF_LESENSE_ALTEX0 location number i */
+#define AF_LESENSE_ALTEX1_PIN(i)    ((i) == 0 ? 7 :  -1)                                                                                                              /**< Pin number for AF_LESENSE_ALTEX1 location number i */
+#define AF_LESENSE_ALTEX2_PIN(i)    ((i) == 0 ? 3 :  -1)                                                                                                              /**< Pin number for AF_LESENSE_ALTEX2 location number i */
+#define AF_LESENSE_ALTEX3_PIN(i)    ((i) == 0 ? 4 :  -1)                                                                                                              /**< Pin number for AF_LESENSE_ALTEX3 location number i */
+#define AF_LESENSE_ALTEX4_PIN(i)    ((i) == 0 ? 5 :  -1)                                                                                                              /**< Pin number for AF_LESENSE_ALTEX4 location number i */
+#define AF_LESENSE_ALTEX5_PIN(i)    ((i) == 0 ? 11 :  -1)                                                                                                             /**< Pin number for AF_LESENSE_ALTEX5 location number i */
+#define AF_LESENSE_ALTEX6_PIN(i)    ((i) == 0 ? 12 :  -1)                                                                                                             /**< Pin number for AF_LESENSE_ALTEX6 location number i */
+#define AF_LESENSE_ALTEX7_PIN(i)    ((i) == 0 ? 13 :  -1)                                                                                                             /**< Pin number for AF_LESENSE_ALTEX7 location number i */
+#define AF_EBI_AD00_PIN(i)          ((i) == 0 ? 8 : (i) == 1 ? 0 :  -1)                                                                                               /**< Pin number for AF_EBI_AD00 location number i */
+#define AF_EBI_AD01_PIN(i)          ((i) == 0 ? 9 : (i) == 1 ? 1 :  -1)                                                                                               /**< Pin number for AF_EBI_AD01 location number i */
+#define AF_EBI_AD02_PIN(i)          ((i) == 0 ? 10 : (i) == 1 ? 2 :  -1)                                                                                              /**< Pin number for AF_EBI_AD02 location number i */
+#define AF_EBI_AD03_PIN(i)          ((i) == 0 ? 11 : (i) == 1 ? 3 :  -1)                                                                                              /**< Pin number for AF_EBI_AD03 location number i */
+#define AF_EBI_AD04_PIN(i)          ((i) == 0 ? 12 : (i) == 1 ? 4 :  -1)                                                                                              /**< Pin number for AF_EBI_AD04 location number i */
+#define AF_EBI_AD05_PIN(i)          ((i) == 0 ? 13 : (i) == 1 ? 5 :  -1)                                                                                              /**< Pin number for AF_EBI_AD05 location number i */
+#define AF_EBI_AD06_PIN(i)          ((i) == 0 ? 14 : (i) == 1 ? 6 :  -1)                                                                                              /**< Pin number for AF_EBI_AD06 location number i */
+#define AF_EBI_AD07_PIN(i)          ((i) == 0 ? 15 : (i) == 1 ? 0 :  -1)                                                                                              /**< Pin number for AF_EBI_AD07 location number i */
+#define AF_EBI_AD08_PIN(i)          ((i) == 0 ? 15 : (i) == 1 ? 1 :  -1)                                                                                              /**< Pin number for AF_EBI_AD08 location number i */
+#define AF_EBI_AD09_PIN(i)          ((i) == 0 ? 0 : (i) == 1 ? 2 :  -1)                                                                                               /**< Pin number for AF_EBI_AD09 location number i */
+#define AF_EBI_AD10_PIN(i)          ((i) == 0 ? 1 : (i) == 1 ? 3 :  -1)                                                                                               /**< Pin number for AF_EBI_AD10 location number i */
+#define AF_EBI_AD11_PIN(i)          ((i) == 0 ? 2 : (i) == 1 ? 4 :  -1)                                                                                               /**< Pin number for AF_EBI_AD11 location number i */
+#define AF_EBI_AD12_PIN(i)          ((i) == 0 ? 3 : (i) == 1 ? 5 :  -1)                                                                                               /**< Pin number for AF_EBI_AD12 location number i */
+#define AF_EBI_AD13_PIN(i)          ((i) == 0 ? 4 : (i) == 1 ? 7 :  -1)                                                                                               /**< Pin number for AF_EBI_AD13 location number i */
+#define AF_EBI_AD14_PIN(i)          ((i) == 0 ? 5 : (i) == 1 ? 8 :  -1)                                                                                               /**< Pin number for AF_EBI_AD14 location number i */
+#define AF_EBI_AD15_PIN(i)          ((i) == 0 ? 6 : (i) == 1 ? 9 :  -1)                                                                                               /**< Pin number for AF_EBI_AD15 location number i */
+#define AF_EBI_CS0_PIN(i)           ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 :  -1)                                                 /**< Pin number for AF_EBI_CS0 location number i */
+#define AF_EBI_CS1_PIN(i)           ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 9 :  -1)                                                /**< Pin number for AF_EBI_CS1 location number i */
+#define AF_EBI_CS2_PIN(i)           ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 10 :  -1)                                               /**< Pin number for AF_EBI_CS2 location number i */
+#define AF_EBI_CS3_PIN(i)           ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 11 :  -1)                                               /**< Pin number for AF_EBI_CS3 location number i */
+#define AF_EBI_ARDY_PIN(i)          ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 10 :  -1)                               /**< Pin number for AF_EBI_ARDY location number i */
+#define AF_EBI_ALE_PIN(i)           ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 11 :  -1)                                 /**< Pin number for AF_EBI_ALE location number i */
+#define AF_EBI_WEn_PIN(i)           ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 8 : (i) == 5 ? 4 :  -1)                                  /**< Pin number for AF_EBI_WEn location number i */
+#define AF_EBI_REn_PIN(i)           ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 0 : (i) == 4 ? 9 : (i) == 5 ? 5 :  -1)                                 /**< Pin number for AF_EBI_REn location number i */
+#define AF_EBI_BL0_PIN(i)           ((i) == 0 ? 6 : (i) == 1 ? 8 : (i) == 2 ? 10 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 6 :  -1)                                  /**< Pin number for AF_EBI_BL0 location number i */
+#define AF_EBI_BL1_PIN(i)           ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 3 : (i) == 4 ? 7 : (i) == 5 ? 7 :  -1)                                  /**< Pin number for AF_EBI_BL1 location number i */
+#define AF_EBI_NANDWEn_PIN(i)       ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 13 : (i) == 3 ? 2 : (i) == 4 ? 14 : (i) == 5 ? 11 :  -1)                               /**< Pin number for AF_EBI_NANDWEn location number i */
+#define AF_EBI_NANDREn_PIN(i)       ((i) == 0 ? 3 : (i) == 1 ? 15 : (i) == 2 ? 9 : (i) == 3 ? 4 : (i) == 4 ? 15 : (i) == 5 ? 12 :  -1)                                /**< Pin number for AF_EBI_NANDREn location number i */
+#define AF_EBI_A00_PIN(i)           ((i) == 0 ? 12 : (i) == 1 ? 9 : (i) == 2 ? -1 : (i) == 3 ? 5 :  -1)                                                               /**< Pin number for AF_EBI_A00 location number i */
+#define AF_EBI_A01_PIN(i)           ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? -1 : (i) == 3 ? 7 :  -1)                                                              /**< Pin number for AF_EBI_A01 location number i */
+#define AF_EBI_A02_PIN(i)           ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? -1 : (i) == 3 ? 8 :  -1)                                                              /**< Pin number for AF_EBI_A02 location number i */
+#define AF_EBI_A03_PIN(i)           ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? -1 : (i) == 3 ? 9 :  -1)                                                               /**< Pin number for AF_EBI_A03 location number i */
+#define AF_EBI_A04_PIN(i)           ((i) == 0 ? 10 : (i) == 1 ? 0 : (i) == 2 ? -1 : (i) == 3 ? 10 :  -1)                                                              /**< Pin number for AF_EBI_A04 location number i */
+#define AF_EBI_A05_PIN(i)           ((i) == 0 ? 6 : (i) == 1 ? 1 : (i) == 2 ? -1 : (i) == 3 ? 11 :  -1)                                                               /**< Pin number for AF_EBI_A05 location number i */
+#define AF_EBI_A06_PIN(i)           ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? -1 : (i) == 3 ? 12 :  -1)                                                               /**< Pin number for AF_EBI_A06 location number i */
+#define AF_EBI_A07_PIN(i)           ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? 13 :  -1)                                                               /**< Pin number for AF_EBI_A07 location number i */
+#define AF_EBI_A08_PIN(i)           ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? -1 : (i) == 3 ? 14 :  -1)                                                               /**< Pin number for AF_EBI_A08 location number i */
+#define AF_EBI_A09_PIN(i)           ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? -1 : (i) == 3 ? 9 :  -1)                                                                /**< Pin number for AF_EBI_A09 location number i */
+#define AF_EBI_A10_PIN(i)           ((i) == 0 ? 3 : (i) == 1 ? 6 : (i) == 2 ? -1 : (i) == 3 ? 10 :  -1)                                                               /**< Pin number for AF_EBI_A10 location number i */
+#define AF_EBI_A11_PIN(i)           ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? -1 : (i) == 3 ? 11 :  -1)                                                               /**< Pin number for AF_EBI_A11 location number i */
+#define AF_EBI_A12_PIN(i)           ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? -1 : (i) == 3 ? 12 :  -1)                                                               /**< Pin number for AF_EBI_A12 location number i */
+#define AF_EBI_A13_PIN(i)           ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? -1 : (i) == 3 ? 0 :  -1)                                                                /**< Pin number for AF_EBI_A13 location number i */
+#define AF_EBI_A14_PIN(i)           ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? -1 : (i) == 3 ? 1 :  -1)                                                                /**< Pin number for AF_EBI_A14 location number i */
+#define AF_EBI_A15_PIN(i)           ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? 2 :  -1)                                                                /**< Pin number for AF_EBI_A15 location number i */
+#define AF_EBI_A16_PIN(i)           ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? -1 : (i) == 3 ? 3 :  -1)                                                                /**< Pin number for AF_EBI_A16 location number i */
+#define AF_EBI_A17_PIN(i)           ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? -1 : (i) == 3 ? 4 :  -1)                                                                /**< Pin number for AF_EBI_A17 location number i */
+#define AF_EBI_A18_PIN(i)           ((i) == 0 ? 2 : (i) == 1 ? 6 : (i) == 2 ? -1 : (i) == 3 ? 5 :  -1)                                                                /**< Pin number for AF_EBI_A18 location number i */
+#define AF_EBI_A19_PIN(i)           ((i) == 0 ? 3 : (i) == 1 ? 7 : (i) == 2 ? -1 : (i) == 3 ? 6 :  -1)                                                                /**< Pin number for AF_EBI_A19 location number i */
+#define AF_EBI_A20_PIN(i)           ((i) == 0 ? 4 : (i) == 1 ? 8 : (i) == 2 ? -1 : (i) == 3 ? 7 :  -1)                                                                /**< Pin number for AF_EBI_A20 location number i */
+#define AF_EBI_A21_PIN(i)           ((i) == 0 ? 5 : (i) == 1 ? 9 : (i) == 2 ? -1 : (i) == 3 ? 7 :  -1)                                                                /**< Pin number for AF_EBI_A21 location number i */
+#define AF_EBI_A22_PIN(i)           ((i) == 0 ? 6 : (i) == 1 ? 10 : (i) == 2 ? -1 : (i) == 3 ? 4 :  -1)                                                               /**< Pin number for AF_EBI_A22 location number i */
+#define AF_EBI_A23_PIN(i)           ((i) == 0 ? 0 : (i) == 1 ? 11 : (i) == 2 ? -1 : (i) == 3 ? 5 :  -1)                                                               /**< Pin number for AF_EBI_A23 location number i */
+#define AF_EBI_A24_PIN(i)           ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? -1 : (i) == 3 ? 6 :  -1)                                                                /**< Pin number for AF_EBI_A24 location number i */
+#define AF_EBI_A25_PIN(i)           ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? -1 : (i) == 3 ? 7 :  -1)                                                                /**< Pin number for AF_EBI_A25 location number i */
+#define AF_EBI_A26_PIN(i)           ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? -1 : (i) == 3 ? 8 :  -1)                                                                /**< Pin number for AF_EBI_A26 location number i */
+#define AF_EBI_A27_PIN(i)           ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? -1 : (i) == 3 ? 9 :  -1)                                                                /**< Pin number for AF_EBI_A27 location number i */
+#define AF_EBI_CSTFT_PIN(i)         ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? -1 : (i) == 3 ? 0 :  -1)                                                                /**< Pin number for AF_EBI_CSTFT location number i */
+#define AF_EBI_DCLK_PIN(i)          ((i) == 0 ? 8 : (i) == 1 ? 7 : (i) == 2 ? -1 : (i) == 3 ? 1 :  -1)                                                                /**< Pin number for AF_EBI_DCLK location number i */
+#define AF_EBI_DTEN_PIN(i)          ((i) == 0 ? 9 : (i) == 1 ? 9 : (i) == 2 ? -1 : (i) == 3 ? 2 :  -1)                                                                /**< Pin number for AF_EBI_DTEN location number i */
+#define AF_EBI_VSNC_PIN(i)          ((i) == 0 ? 10 : (i) == 1 ? 10 : (i) == 2 ? -1 : (i) == 3 ? 3 :  -1)                                                              /**< Pin number for AF_EBI_VSNC location number i */
+#define AF_EBI_HSNC_PIN(i)          ((i) == 0 ? 11 : (i) == 1 ? 11 : (i) == 2 ? -1 : (i) == 3 ? 4 :  -1)                                                              /**< Pin number for AF_EBI_HSNC location number i */
+#define AF_SDIO_CLK_PIN(i)          ((i) == 0 ? 13 : (i) == 1 ? 14 :  -1)                                                                                             /**< Pin number for AF_SDIO_CLK location number i */
+#define AF_SDIO_CMD_PIN(i)          ((i) == 0 ? 12 : (i) == 1 ? 15 :  -1)                                                                                             /**< Pin number for AF_SDIO_CMD location number i */
+#define AF_SDIO_DAT0_PIN(i)         ((i) == 0 ? 11 : (i) == 1 ? 0 :  -1)                                                                                              /**< Pin number for AF_SDIO_DAT0 location number i */
+#define AF_SDIO_DAT1_PIN(i)         ((i) == 0 ? 10 : (i) == 1 ? 1 :  -1)                                                                                              /**< Pin number for AF_SDIO_DAT1 location number i */
+#define AF_SDIO_DAT2_PIN(i)         ((i) == 0 ? 9 : (i) == 1 ? 2 :  -1)                                                                                               /**< Pin number for AF_SDIO_DAT2 location number i */
+#define AF_SDIO_DAT3_PIN(i)         ((i) == 0 ? 8 : (i) == 1 ? 3 :  -1)                                                                                               /**< Pin number for AF_SDIO_DAT3 location number i */
+#define AF_SDIO_DAT4_PIN(i)         ((i) == 0 ? 12 : (i) == 1 ? 4 :  -1)                                                                                              /**< Pin number for AF_SDIO_DAT4 location number i */
+#define AF_SDIO_DAT5_PIN(i)         ((i) == 0 ? 11 : (i) == 1 ? 5 :  -1)                                                                                              /**< Pin number for AF_SDIO_DAT5 location number i */
+#define AF_SDIO_DAT6_PIN(i)         ((i) == 0 ? 10 : (i) == 1 ? 3 :  -1)                                                                                              /**< Pin number for AF_SDIO_DAT6 location number i */
+#define AF_SDIO_DAT7_PIN(i)         ((i) == 0 ? 9 : (i) == 1 ? 4 :  -1)                                                                                               /**< Pin number for AF_SDIO_DAT7 location number i */
+#define AF_SDIO_CD_PIN(i)           ((i) == 0 ? 8 : (i) == 1 ? 4 : (i) == 2 ? 6 : (i) == 3 ? 10 :  -1)                                                                /**< Pin number for AF_SDIO_CD location number i */
+#define AF_SDIO_WP_PIN(i)           ((i) == 0 ? 9 : (i) == 1 ? 5 : (i) == 2 ? 15 : (i) == 3 ? 9 :  -1)                                                                /**< Pin number for AF_SDIO_WP location number i */
+#define AF_PDM_CLK_PIN(i)           ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 0 :  -1)                                                 /**< Pin number for AF_PDM_CLK location number i */
+#define AF_PDM_DAT0_PIN(i)          ((i) == 0 ? 1 : (i) == 1 ? 9 : (i) == 2 ? 7 : (i) == 3 ? 11 : (i) == 4 ? 1 :  -1)                                                 /**< Pin number for AF_PDM_DAT0 location number i */
+#define AF_PDM_DAT1_PIN(i)          ((i) == 0 ? 2 : (i) == 1 ? 10 : (i) == 2 ? 8 : (i) == 3 ? 10 : (i) == 4 ? 2 :  -1)                                                /**< Pin number for AF_PDM_DAT1 location number i */
+#define AF_PDM_DAT2_PIN(i)          ((i) == 0 ? 3 : (i) == 1 ? 11 : (i) == 2 ? 9 : (i) == 3 ? 9 : (i) == 4 ? 3 :  -1)                                                 /**< Pin number for AF_PDM_DAT2 location number i */
+#define AF_PDM_DAT3_PIN(i)          ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 9 : (i) == 3 ? 13 : (i) == 4 ? 4 :  -1)                                                /**< Pin number for AF_PDM_DAT3 location number i */
+#define AF_PRS_CH0_PIN(i)           ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 14 : (i) == 3 ? 2 :  -1)                                                                /**< Pin number for AF_PRS_CH0 location number i */
+#define AF_PRS_CH1_PIN(i)           ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 15 : (i) == 3 ? 12 :  -1)                                                               /**< Pin number for AF_PRS_CH1 location number i */
+#define AF_PRS_CH2_PIN(i)           ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 10 : (i) == 3 ? 13 :  -1)                                                               /**< Pin number for AF_PRS_CH2 location number i */
+#define AF_PRS_CH3_PIN(i)           ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 0 :  -1)                                                                /**< Pin number for AF_PRS_CH3 location number i */
+#define AF_PRS_CH4_PIN(i)           ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 :  -1)                                                                                /**< Pin number for AF_PRS_CH4 location number i */
+#define AF_PRS_CH5_PIN(i)           ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 6 :  -1)                                                                                /**< Pin number for AF_PRS_CH5 location number i */
+#define AF_PRS_CH6_PIN(i)           ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 6 :  -1)                                                                               /**< Pin number for AF_PRS_CH6 location number i */
+#define AF_PRS_CH7_PIN(i)           ((i) == 0 ? 13 : (i) == 1 ? 7 : (i) == 2 ? 7 :  -1)                                                                               /**< Pin number for AF_PRS_CH7 location number i */
+#define AF_PRS_CH8_PIN(i)           ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 9 :  -1)                                                                                /**< Pin number for AF_PRS_CH8 location number i */
+#define AF_PRS_CH9_PIN(i)           ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 10 :  -1)                                                                               /**< Pin number for AF_PRS_CH9 location number i */
+#define AF_PRS_CH10_PIN(i)          ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 4 :  -1)                                                                               /**< Pin number for AF_PRS_CH10 location number i */
+#define AF_PRS_CH11_PIN(i)          ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 5 :  -1)                                                                               /**< Pin number for AF_PRS_CH11 location number i */
+#define AF_PRS_CH12_PIN(i)          ((i) == 0 ? 12 : (i) == 1 ? 6 : (i) == 2 ? 8 :  -1)                                                                               /**< Pin number for AF_PRS_CH12 location number i */
+#define AF_PRS_CH13_PIN(i)          ((i) == 0 ? 13 : (i) == 1 ? 9 : (i) == 2 ? 14 :  -1)                                                                              /**< Pin number for AF_PRS_CH13 location number i */
+#define AF_PRS_CH14_PIN(i)          ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 15 :  -1)                                                                              /**< Pin number for AF_PRS_CH14 location number i */
+#define AF_PRS_CH15_PIN(i)          ((i) == 0 ? 15 : (i) == 1 ? 7 : (i) == 2 ? 0 :  -1)                                                                               /**< Pin number for AF_PRS_CH15 location number i */
+#define AF_CAN0_RX_PIN(i)           ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 9 : (i) == 4 ? -1 : (i) == 5 ? 14 : (i) == 6 ? 0 :  -1)                  /**< Pin number for AF_CAN0_RX location number i */
+#define AF_CAN0_TX_PIN(i)           ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : (i) == 3 ? 10 : (i) == 4 ? -1 : (i) == 5 ? 15 : (i) == 6 ? 1 :  -1)                 /**< Pin number for AF_CAN0_TX location number i */
+#define AF_CAN1_RX_PIN(i)           ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 12 : (i) == 5 ? 12 :  -1)                                 /**< Pin number for AF_CAN1_RX location number i */
+#define AF_CAN1_TX_PIN(i)           ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 13 :  -1)                                /**< Pin number for AF_CAN1_TX location number i */
+#define AF_TIMER0_CC0_PIN(i)        ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 8 : (i) == 7 ? 1 :  -1)     /**< Pin number for AF_TIMER0_CC0 location number i */
+#define AF_TIMER0_CC1_PIN(i)        ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 5 : (i) == 6 ? 9 : (i) == 7 ? 0 :  -1)     /**< Pin number for AF_TIMER0_CC1 location number i */
+#define AF_TIMER0_CC2_PIN(i)        ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 10 : (i) == 7 ? 13 :  -1)   /**< Pin number for AF_TIMER0_CC2 location number i */
+#define AF_TIMER0_CC3_PIN(i)        (-1)                                                                                                                              /**< Pin number for AF_TIMER0_CC3 location number i */
+#define AF_TIMER0_CDTI0_PIN(i)      ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 7 :  -1)                                                 /**< Pin number for AF_TIMER0_CDTI0 location number i */
+#define AF_TIMER0_CDTI1_PIN(i)      ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 8 :  -1)                                                 /**< Pin number for AF_TIMER0_CDTI1 location number i */
+#define AF_TIMER0_CDTI2_PIN(i)      ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : (i) == 3 ? 4 : (i) == 4 ? 11 :  -1)                                                /**< Pin number for AF_TIMER0_CDTI2 location number i */
+#define AF_TIMER0_CDTI3_PIN(i)      (-1)                                                                                                                              /**< Pin number for AF_TIMER0_CDTI3 location number i */
+#define AF_TIMER1_CC0_PIN(i)        ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 7 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 13 :  -1)                 /**< Pin number for AF_TIMER1_CC0 location number i */
+#define AF_TIMER1_CC1_PIN(i)        ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 8 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 14 :  -1)                 /**< Pin number for AF_TIMER1_CC1 location number i */
+#define AF_TIMER1_CC2_PIN(i)        ((i) == 0 ? 15 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 4 :  -1)                               /**< Pin number for AF_TIMER1_CC2 location number i */
+#define AF_TIMER1_CC3_PIN(i)        ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 12 : (i) == 6 ? 5 :  -1)               /**< Pin number for AF_TIMER1_CC3 location number i */
+#define AF_TIMER1_CDTI0_PIN(i)      (-1)                                                                                                                              /**< Pin number for AF_TIMER1_CDTI0 location number i */
+#define AF_TIMER1_CDTI1_PIN(i)      (-1)                                                                                                                              /**< Pin number for AF_TIMER1_CDTI1 location number i */
+#define AF_TIMER1_CDTI2_PIN(i)      (-1)                                                                                                                              /**< Pin number for AF_TIMER1_CDTI2 location number i */
+#define AF_TIMER1_CDTI3_PIN(i)      (-1)                                                                                                                              /**< Pin number for AF_TIMER1_CDTI3 location number i */
+#define AF_TIMER2_CC0_PIN(i)        ((i) == 0 ? 8 : (i) == 1 ? 12 : (i) == 2 ? 8 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 :  -1)                                  /**< Pin number for AF_TIMER2_CC0 location number i */
+#define AF_TIMER2_CC1_PIN(i)        ((i) == 0 ? 9 : (i) == 1 ? 13 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 0 : (i) == 5 ? 3 :  -1)                                 /**< Pin number for AF_TIMER2_CC1 location number i */
+#define AF_TIMER2_CC2_PIN(i)        ((i) == 0 ? 10 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 4 :  -1)                               /**< Pin number for AF_TIMER2_CC2 location number i */
+#define AF_TIMER2_CC3_PIN(i)        (-1)                                                                                                                              /**< Pin number for AF_TIMER2_CC3 location number i */
+#define AF_TIMER2_CDTI0_PIN(i)      ((i) == 0 ? 0 : (i) == 1 ? 13 : (i) == 2 ? 8 :  -1)                                                                               /**< Pin number for AF_TIMER2_CDTI0 location number i */
+#define AF_TIMER2_CDTI1_PIN(i)      ((i) == 0 ? 1 : (i) == 1 ? 14 : (i) == 2 ? 14 :  -1)                                                                              /**< Pin number for AF_TIMER2_CDTI1 location number i */
+#define AF_TIMER2_CDTI2_PIN(i)      ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 15 :  -1)                                                                              /**< Pin number for AF_TIMER2_CDTI2 location number i */
+#define AF_TIMER2_CDTI3_PIN(i)      (-1)                                                                                                                              /**< Pin number for AF_TIMER2_CDTI3 location number i */
+#define AF_TIMER3_CC0_PIN(i)        ((i) == 0 ? 14 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 15 :  -1)   /**< Pin number for AF_TIMER3_CC0 location number i */
+#define AF_TIMER3_CC1_PIN(i)        ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 13 : (i) == 7 ? 15 :  -1)  /**< Pin number for AF_TIMER3_CC1 location number i */
+#define AF_TIMER3_CC2_PIN(i)        ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 14 : (i) == 7 ? 0 :  -1)   /**< Pin number for AF_TIMER3_CC2 location number i */
+#define AF_TIMER3_CC3_PIN(i)        (-1)                                                                                                                              /**< Pin number for AF_TIMER3_CC3 location number i */
+#define AF_TIMER3_CDTI0_PIN(i)      (-1)                                                                                                                              /**< Pin number for AF_TIMER3_CDTI0 location number i */
+#define AF_TIMER3_CDTI1_PIN(i)      (-1)                                                                                                                              /**< Pin number for AF_TIMER3_CDTI1 location number i */
+#define AF_TIMER3_CDTI2_PIN(i)      (-1)                                                                                                                              /**< Pin number for AF_TIMER3_CDTI2 location number i */
+#define AF_TIMER3_CDTI3_PIN(i)      (-1)                                                                                                                              /**< Pin number for AF_TIMER3_CDTI3 location number i */
+#define AF_WTIMER0_CC0_PIN(i)       ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? 15 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 :  -1)  /**< Pin number for AF_WTIMER0_CC0 location number i */
+#define AF_WTIMER0_CC1_PIN(i)       ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 4 : (i) == 7 ? 2 :  -1)  /**< Pin number for AF_WTIMER0_CC1 location number i */
+#define AF_WTIMER0_CC2_PIN(i)       ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 3 :  -1)  /**< Pin number for AF_WTIMER0_CC2 location number i */
+#define AF_WTIMER0_CC3_PIN(i)       (-1)                                                                                                                              /**< Pin number for AF_WTIMER0_CC3 location number i */
+#define AF_WTIMER0_CDTI0_PIN(i)     ((i) == 0 ? 10 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? -1 : (i) == 4 ? 4 :  -1)                                              /**< Pin number for AF_WTIMER0_CDTI0 location number i */
+#define AF_WTIMER0_CDTI1_PIN(i)     ((i) == 0 ? 11 : (i) == 1 ? -1 : (i) == 2 ? 13 : (i) == 3 ? -1 : (i) == 4 ? 5 :  -1)                                              /**< Pin number for AF_WTIMER0_CDTI1 location number i */
+#define AF_WTIMER0_CDTI2_PIN(i)     ((i) == 0 ? 12 : (i) == 1 ? -1 : (i) == 2 ? 14 : (i) == 3 ? -1 : (i) == 4 ? 6 :  -1)                                              /**< Pin number for AF_WTIMER0_CDTI2 location number i */
+#define AF_WTIMER0_CDTI3_PIN(i)     (-1)                                                                                                                              /**< Pin number for AF_WTIMER0_CDTI3 location number i */
+#define AF_WTIMER1_CC0_PIN(i)       ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 3 : (i) == 5 ? 7 :  -1)                                  /**< Pin number for AF_WTIMER1_CC0 location number i */
+#define AF_WTIMER1_CC1_PIN(i)       ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : (i) == 4 ? 4 :  -1)                                                 /**< Pin number for AF_WTIMER1_CC1 location number i */
+#define AF_WTIMER1_CC2_PIN(i)       ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 1 : (i) == 4 ? 5 :  -1)                                                  /**< Pin number for AF_WTIMER1_CC2 location number i */
+#define AF_WTIMER1_CC3_PIN(i)       ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 2 : (i) == 4 ? 6 :  -1)                                                  /**< Pin number for AF_WTIMER1_CC3 location number i */
+#define AF_WTIMER1_CDTI0_PIN(i)     (-1)                                                                                                                              /**< Pin number for AF_WTIMER1_CDTI0 location number i */
+#define AF_WTIMER1_CDTI1_PIN(i)     (-1)                                                                                                                              /**< Pin number for AF_WTIMER1_CDTI1 location number i */
+#define AF_WTIMER1_CDTI2_PIN(i)     (-1)                                                                                                                              /**< Pin number for AF_WTIMER1_CDTI2 location number i */
+#define AF_WTIMER1_CDTI3_PIN(i)     (-1)                                                                                                                              /**< Pin number for AF_WTIMER1_CDTI3 location number i */
+#define AF_USART0_TX_PIN(i)         ((i) == 0 ? 10 : (i) == 1 ? 7 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 0 :  -1)                                /**< Pin number for AF_USART0_TX location number i */
+#define AF_USART0_RX_PIN(i)         ((i) == 0 ? 11 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 1 :  -1)                                /**< Pin number for AF_USART0_RX location number i */
+#define AF_USART0_CLK_PIN(i)        ((i) == 0 ? 12 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 13 : (i) == 5 ? 12 :  -1)                               /**< Pin number for AF_USART0_CLK location number i */
+#define AF_USART0_CS_PIN(i)         ((i) == 0 ? 13 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 14 : (i) == 5 ? 13 :  -1)                               /**< Pin number for AF_USART0_CS location number i */
+#define AF_USART0_CTS_PIN(i)        ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 11 :  -1)                                /**< Pin number for AF_USART0_CTS location number i */
+#define AF_USART0_RTS_PIN(i)        ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 5 : (i) == 5 ? 6 :  -1)                                 /**< Pin number for AF_USART0_RTS location number i */
+#define AF_USART1_TX_PIN(i)         ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 7 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 14 :  -1)                   /**< Pin number for AF_USART1_TX location number i */
+#define AF_USART1_RX_PIN(i)         ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 2 :  -1)                    /**< Pin number for AF_USART1_RX location number i */
+#define AF_USART1_CLK_PIN(i)        ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 15 : (i) == 4 ? 3 : (i) == 5 ? 11 : (i) == 6 ? 5 :  -1)                  /**< Pin number for AF_USART1_CLK location number i */
+#define AF_USART1_CS_PIN(i)         ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 2 :  -1)                   /**< Pin number for AF_USART1_CS location number i */
+#define AF_USART1_CTS_PIN(i)        ((i) == 0 ? 9 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 12 : (i) == 5 ? 13 :  -1)                                 /**< Pin number for AF_USART1_CTS location number i */
+#define AF_USART1_RTS_PIN(i)        ((i) == 0 ? 10 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 7 : (i) == 4 ? 13 : (i) == 5 ? 14 :  -1)                                /**< Pin number for AF_USART1_RTS location number i */
+#define AF_USART2_TX_PIN(i)         ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 0 :  -1)                                  /**< Pin number for AF_USART2_TX location number i */
+#define AF_USART2_RX_PIN(i)         ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 7 : (i) == 5 ? 1 :  -1)                                  /**< Pin number for AF_USART2_RX location number i */
+#define AF_USART2_CLK_PIN(i)        ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 8 : (i) == 5 ? 2 :  -1)                                  /**< Pin number for AF_USART2_CLK location number i */
+#define AF_USART2_CS_PIN(i)         ((i) == 0 ? 5 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 5 :  -1)                                 /**< Pin number for AF_USART2_CS location number i */
+#define AF_USART2_CTS_PIN(i)        ((i) == 0 ? 1 : (i) == 1 ? 12 : (i) == 2 ? 11 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 6 :  -1)                               /**< Pin number for AF_USART2_CTS location number i */
+#define AF_USART2_RTS_PIN(i)        ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 14 : (i) == 4 ? 13 : (i) == 5 ? 8 :  -1)                               /**< Pin number for AF_USART2_RTS location number i */
+#define AF_USART3_TX_PIN(i)         ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 3 :  -1)                                                                                /**< Pin number for AF_USART3_TX location number i */
+#define AF_USART3_RX_PIN(i)         ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 :  -1)                                                                                /**< Pin number for AF_USART3_RX location number i */
+#define AF_USART3_CLK_PIN(i)        ((i) == 0 ? 2 : (i) == 1 ? 7 : (i) == 2 ? 4 :  -1)                                                                                /**< Pin number for AF_USART3_CLK location number i */
+#define AF_USART3_CS_PIN(i)         ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 14 : (i) == 3 ? 0 :  -1)                                                                /**< Pin number for AF_USART3_CS location number i */
+#define AF_USART3_CTS_PIN(i)        ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 6 :  -1)                                                                                /**< Pin number for AF_USART3_CTS location number i */
+#define AF_USART3_RTS_PIN(i)        ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 15 :  -1)                                                               /**< Pin number for AF_USART3_RTS location number i */
+#define AF_USART4_TX_PIN(i)         ((i) == 0 ? 7 : (i) == 1 ? 9 :  -1)                                                                                               /**< Pin number for AF_USART4_TX location number i */
+#define AF_USART4_RX_PIN(i)         ((i) == 0 ? 8 : (i) == 1 ? 10 :  -1)                                                                                              /**< Pin number for AF_USART4_RX location number i */
+#define AF_USART4_CLK_PIN(i)        ((i) == 0 ? 4 : (i) == 1 ? 11 :  -1)                                                                                              /**< Pin number for AF_USART4_CLK location number i */
+#define AF_USART4_CS_PIN(i)         ((i) == 0 ? 5 : (i) == 1 ? 12 :  -1)                                                                                              /**< Pin number for AF_USART4_CS location number i */
+#define AF_USART4_CTS_PIN(i)        ((i) == 0 ? 7 : (i) == 1 ? 13 :  -1)                                                                                              /**< Pin number for AF_USART4_CTS location number i */
+#define AF_USART4_RTS_PIN(i)        ((i) == 0 ? 8 : (i) == 1 ? 14 :  -1)                                                                                              /**< Pin number for AF_USART4_RTS location number i */
+#define AF_UART0_TX_PIN(i)          ((i) == 0 ? 6 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 14 : (i) == 4 ? 4 : (i) == 5 ? 1 : (i) == 6 ? 7 :  -1)                   /**< Pin number for AF_UART0_TX location number i */
+#define AF_UART0_RX_PIN(i)          ((i) == 0 ? 7 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 4 :  -1)                   /**< Pin number for AF_UART0_RX location number i */
+#define AF_UART0_CLK_PIN(i)         (-1)                                                                                                                              /**< Pin number for AF_UART0_CLK location number i */
+#define AF_UART0_CS_PIN(i)          (-1)                                                                                                                              /**< Pin number for AF_UART0_CS location number i */
+#define AF_UART0_CTS_PIN(i)         ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 5 :  -1)                                  /**< Pin number for AF_UART0_CTS location number i */
+#define AF_UART0_RTS_PIN(i)         ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 6 :  -1)                                  /**< Pin number for AF_UART0_RTS location number i */
+#define AF_UART1_TX_PIN(i)          ((i) == 0 ? 12 : (i) == 1 ? 10 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 12 :  -1)                                               /**< Pin number for AF_UART1_TX location number i */
+#define AF_UART1_RX_PIN(i)          ((i) == 0 ? 13 : (i) == 1 ? 11 : (i) == 2 ? 10 : (i) == 3 ? 3 : (i) == 4 ? 13 :  -1)                                              /**< Pin number for AF_UART1_RX location number i */
+#define AF_UART1_CLK_PIN(i)         (-1)                                                                                                                              /**< Pin number for AF_UART1_CLK location number i */
+#define AF_UART1_CS_PIN(i)          (-1)                                                                                                                              /**< Pin number for AF_UART1_CS location number i */
+#define AF_UART1_CTS_PIN(i)         ((i) == 0 ? 14 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 4 : (i) == 4 ? 4 :  -1)                                                /**< Pin number for AF_UART1_CTS location number i */
+#define AF_UART1_RTS_PIN(i)         ((i) == 0 ? 15 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 5 : (i) == 4 ? 5 :  -1)                                                /**< Pin number for AF_UART1_RTS location number i */
+#define AF_QSPI0_SCLK_PIN(i)        ((i) == 0 ? 6 : (i) == 1 ? 14 :  -1)                                                                                              /**< Pin number for AF_QSPI0_SCLK location number i */
+#define AF_QSPI0_DQ0_PIN(i)         ((i) == 0 ? 9 : (i) == 1 ? 2 :  -1)                                                                                               /**< Pin number for AF_QSPI0_DQ0 location number i */
+#define AF_QSPI0_DQ1_PIN(i)         ((i) == 0 ? 10 : (i) == 1 ? 3 :  -1)                                                                                              /**< Pin number for AF_QSPI0_DQ1 location number i */
+#define AF_QSPI0_DQ2_PIN(i)         ((i) == 0 ? 11 : (i) == 1 ? 4 :  -1)                                                                                              /**< Pin number for AF_QSPI0_DQ2 location number i */
+#define AF_QSPI0_DQ3_PIN(i)         ((i) == 0 ? 12 : (i) == 1 ? 5 :  -1)                                                                                              /**< Pin number for AF_QSPI0_DQ3 location number i */
+#define AF_QSPI0_DQ4_PIN(i)         ((i) == 0 ? 8 : (i) == 1 ? 3 :  -1)                                                                                               /**< Pin number for AF_QSPI0_DQ4 location number i */
+#define AF_QSPI0_DQ5_PIN(i)         ((i) == 0 ? 9 : (i) == 1 ? 4 :  -1)                                                                                               /**< Pin number for AF_QSPI0_DQ5 location number i */
+#define AF_QSPI0_DQ6_PIN(i)         ((i) == 0 ? 10 : (i) == 1 ? 5 :  -1)                                                                                              /**< Pin number for AF_QSPI0_DQ6 location number i */
+#define AF_QSPI0_DQ7_PIN(i)         ((i) == 0 ? 11 : (i) == 1 ? 6 :  -1)                                                                                              /**< Pin number for AF_QSPI0_DQ7 location number i */
+#define AF_QSPI0_CS0_PIN(i)         ((i) == 0 ? 7 : (i) == 1 ? 0 :  -1)                                                                                               /**< Pin number for AF_QSPI0_CS0 location number i */
+#define AF_QSPI0_CS1_PIN(i)         ((i) == 0 ? 8 : (i) == 1 ? 1 :  -1)                                                                                               /**< Pin number for AF_QSPI0_CS1 location number i */
+#define AF_QSPI0_DQS_PIN(i)         ((i) == 0 ? 9 : (i) == 1 ? 15 :  -1)                                                                                              /**< Pin number for AF_QSPI0_DQS location number i */
+#define AF_QSPI0_RST0_PIN(i)        ((i) == 0 ? 14 : (i) == 1 ? 2 :  -1)                                                                                              /**< Pin number for AF_QSPI0_RST0 location number i */
+#define AF_QSPI0_RST1_PIN(i)        ((i) == 0 ? 15 : (i) == 1 ? 3 :  -1)                                                                                              /**< Pin number for AF_QSPI0_RST1 location number i */
+#define AF_LEUART0_TX_PIN(i)        ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 2 : (i) == 5 ? 14 :  -1)                                /**< Pin number for AF_LEUART0_TX location number i */
+#define AF_LEUART0_RX_PIN(i)        ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 15 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 15 :  -1)                                /**< Pin number for AF_LEUART0_RX location number i */
+#define AF_LEUART1_TX_PIN(i)        ((i) == 0 ? 6 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 :  -1)                                                  /**< Pin number for AF_LEUART1_TX location number i */
+#define AF_LEUART1_RX_PIN(i)        ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 :  -1)                                                  /**< Pin number for AF_LEUART1_RX location number i */
+#define AF_LETIMER0_OUT0_PIN(i)     ((i) == 0 ? 6 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 12 : (i) == 5 ? 14 : (i) == 6 ? 8 : (i) == 7 ? 9 :  -1)  /**< Pin number for AF_LETIMER0_OUT0 location number i */
+#define AF_LETIMER0_OUT1_PIN(i)     ((i) == 0 ? 7 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 9 : (i) == 7 ? 10 :  -1) /**< Pin number for AF_LETIMER0_OUT1 location number i */
+#define AF_LETIMER1_OUT0_PIN(i)     ((i) == 0 ? 7 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 :  -1)                                 /**< Pin number for AF_LETIMER1_OUT0 location number i */
+#define AF_LETIMER1_OUT1_PIN(i)     ((i) == 0 ? 6 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 3 : (i) == 4 ? 6 : (i) == 5 ? 1 :  -1)                                 /**< Pin number for AF_LETIMER1_OUT1 location number i */
+#define AF_PCNT0_S0IN_PIN(i)        ((i) == 0 ? 13 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 5 : (i) == 7 ? 12 :  -1)   /**< Pin number for AF_PCNT0_S0IN location number i */
+#define AF_PCNT0_S1IN_PIN(i)        ((i) == 0 ? 14 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 11 :  -1)   /**< Pin number for AF_PCNT0_S1IN location number i */
+#define AF_PCNT1_S0IN_PIN(i)        ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 7 : (i) == 5 ? 12 : (i) == 6 ? 11 :  -1)                 /**< Pin number for AF_PCNT1_S0IN location number i */
+#define AF_PCNT1_S1IN_PIN(i)        ((i) == 0 ? 6 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 12 :  -1)                  /**< Pin number for AF_PCNT1_S1IN location number i */
+#define AF_PCNT2_S0IN_PIN(i)        ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 13 : (i) == 3 ? 10 : (i) == 4 ? 12 :  -1)                                               /**< Pin number for AF_PCNT2_S0IN location number i */
+#define AF_PCNT2_S1IN_PIN(i)        ((i) == 0 ? 1 : (i) == 1 ? 9 : (i) == 2 ? 14 : (i) == 3 ? 11 : (i) == 4 ? 13 :  -1)                                               /**< Pin number for AF_PCNT2_S1IN location number i */
+#define AF_I2C0_SDA_PIN(i)          ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 12 : (i) == 7 ? 4 :  -1)   /**< Pin number for AF_I2C0_SDA location number i */
+#define AF_I2C0_SCL_PIN(i)          ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 15 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 13 : (i) == 7 ? 5 :  -1)   /**< Pin number for AF_I2C0_SCL location number i */
+#define AF_I2C1_SDA_PIN(i)          ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 11 :  -1)                                                /**< Pin number for AF_I2C1_SDA location number i */
+#define AF_I2C1_SCL_PIN(i)          ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 :  -1)                                                 /**< Pin number for AF_I2C1_SCL location number i */
+#define AF_ACMP0_OUT_PIN(i)         ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 6 : (i) == 5 ? 0 : (i) == 6 ? 2 : (i) == 7 ? 3 :  -1)   /**< Pin number for AF_ACMP0_OUT location number i */
+#define AF_ACMP1_OUT_PIN(i)         ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 9 : (i) == 6 ? 10 : (i) == 7 ? 5 :  -1)  /**< Pin number for AF_ACMP1_OUT location number i */
+#define AF_ACMP2_OUT_PIN(i)         ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 :  -1)                                                                                /**< Pin number for AF_ACMP2_OUT location number i */
+#define AF_USB_VBUSEN_PIN(i)        ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 :  -1)                                                                                /**< Pin number for AF_USB_VBUSEN location number i */
+#define AF_DBG_TDI_PIN(i)           ((i) == 0 ? 5 :  -1)                                                                                                              /**< Pin number for AF_DBG_TDI location number i */
+#define AF_DBG_TDO_PIN(i)           ((i) == 0 ? 2 :  -1)                                                                                                              /**< Pin number for AF_DBG_TDO location number i */
+#define AF_DBG_SWV_PIN(i)           ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 1 : (i) == 3 ? 2 :  -1)                                                                /**< Pin number for AF_DBG_SWV location number i */
+#define AF_DBG_SWDIOTMS_PIN(i)      ((i) == 0 ? 1 :  -1)                                                                                                              /**< Pin number for AF_DBG_SWDIOTMS location number i */
+#define AF_DBG_SWCLKTCK_PIN(i)      ((i) == 0 ? 0 :  -1)                                                                                                              /**< Pin number for AF_DBG_SWCLKTCK location number i */
+#define AF_ETM_TCLK_PIN(i)          ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 11 :  -1)                                                 /**< Pin number for AF_ETM_TCLK location number i */
+#define AF_ETM_TD0_PIN(i)           ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 12 :  -1)                                                 /**< Pin number for AF_ETM_TD0 location number i */
+#define AF_ETM_TD1_PIN(i)           ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 13 :  -1)                                                /**< Pin number for AF_ETM_TD1 location number i */
+#define AF_ETM_TD2_PIN(i)           ((i) == 0 ? 4 : (i) == 1 ? 15 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 14 :  -1)                                                /**< Pin number for AF_ETM_TD2 location number i */
+#define AF_ETM_TD3_PIN(i)           ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 15 :  -1)                                                 /**< Pin number for AF_ETM_TD3 location number i */
+
+/** @} */
+/** @} End of group EFM32GG12B_AF_Pins */
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+

cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b_af_ports.h

@@ -0,0 +1,325 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32GG12B_AF_PORTS register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @addtogroup EFM32GG12B_Alternate_Function Alternate Function
+ * @{
+ * @defgroup EFM32GG12B_AF_Ports Alternate Function Ports
+ * @{
+ ******************************************************************************/
+
+#define AF_CMU_CLK0_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? -1 : (i) == 4 ? 5 : (i) == 5 ? 0 :  -1)                                /**< Port number for AF_CMU_CLK0 location number i */
+#define AF_CMU_CLK1_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? -1 : (i) == 4 ? 5 : (i) == 5 ? 1 :  -1)                                /**< Port number for AF_CMU_CLK1 location number i */
+#define AF_CMU_CLK2_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? -1 : (i) == 4 ? 0 : (i) == 5 ? 3 :  -1)                                /**< Port number for AF_CMU_CLK2 location number i */
+#define AF_CMU_CLKI0_PORT(i)         ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 4 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 1 :  -1)   /**< Port number for AF_CMU_CLKI0 location number i */
+#define AF_CMU_DIGEXTCLK_PORT(i)     ((i) == 0 ? 1 :  -1)                                                                                                            /**< Port number for AF_CMU_DIGEXTCLK location number i */
+#define AF_CMU_IOPOVR_PORT(i)        ((i) == 0 ? 1 :  -1)                                                                                                            /**< Port number for AF_CMU_IOPOVR location number i */
+#define AF_CMU_IONOVR_PORT(i)        ((i) == 0 ? 1 :  -1)                                                                                                            /**< Port number for AF_CMU_IONOVR location number i */
+#define AF_LESENSE_CH0_PORT(i)       ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH0 location number i */
+#define AF_LESENSE_CH1_PORT(i)       ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH1 location number i */
+#define AF_LESENSE_CH2_PORT(i)       ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH2 location number i */
+#define AF_LESENSE_CH3_PORT(i)       ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH3 location number i */
+#define AF_LESENSE_CH4_PORT(i)       ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH4 location number i */
+#define AF_LESENSE_CH5_PORT(i)       ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH5 location number i */
+#define AF_LESENSE_CH6_PORT(i)       ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH6 location number i */
+#define AF_LESENSE_CH7_PORT(i)       ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH7 location number i */
+#define AF_LESENSE_CH8_PORT(i)       ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH8 location number i */
+#define AF_LESENSE_CH9_PORT(i)       ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH9 location number i */
+#define AF_LESENSE_CH10_PORT(i)      ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH10 location number i */
+#define AF_LESENSE_CH11_PORT(i)      ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH11 location number i */
+#define AF_LESENSE_CH12_PORT(i)      ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH12 location number i */
+#define AF_LESENSE_CH13_PORT(i)      ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH13 location number i */
+#define AF_LESENSE_CH14_PORT(i)      ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH14 location number i */
+#define AF_LESENSE_CH15_PORT(i)      ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH15 location number i */
+#define AF_LESENSE_ALTEX0_PORT(i)    ((i) == 0 ? 3 :  -1)                                                                                                            /**< Port number for AF_LESENSE_ALTEX0 location number i */
+#define AF_LESENSE_ALTEX1_PORT(i)    ((i) == 0 ? 3 :  -1)                                                                                                            /**< Port number for AF_LESENSE_ALTEX1 location number i */
+#define AF_LESENSE_ALTEX2_PORT(i)    ((i) == 0 ? 0 :  -1)                                                                                                            /**< Port number for AF_LESENSE_ALTEX2 location number i */
+#define AF_LESENSE_ALTEX3_PORT(i)    ((i) == 0 ? 0 :  -1)                                                                                                            /**< Port number for AF_LESENSE_ALTEX3 location number i */
+#define AF_LESENSE_ALTEX4_PORT(i)    ((i) == 0 ? 0 :  -1)                                                                                                            /**< Port number for AF_LESENSE_ALTEX4 location number i */
+#define AF_LESENSE_ALTEX5_PORT(i)    ((i) == 0 ? 4 :  -1)                                                                                                            /**< Port number for AF_LESENSE_ALTEX5 location number i */
+#define AF_LESENSE_ALTEX6_PORT(i)    ((i) == 0 ? 4 :  -1)                                                                                                            /**< Port number for AF_LESENSE_ALTEX6 location number i */
+#define AF_LESENSE_ALTEX7_PORT(i)    ((i) == 0 ? 4 :  -1)                                                                                                            /**< Port number for AF_LESENSE_ALTEX7 location number i */
+#define AF_EBI_AD00_PORT(i)          ((i) == 0 ? 4 : (i) == 1 ? 1 :  -1)                                                                                             /**< Port number for AF_EBI_AD00 location number i */
+#define AF_EBI_AD01_PORT(i)          ((i) == 0 ? 4 : (i) == 1 ? 1 :  -1)                                                                                             /**< Port number for AF_EBI_AD01 location number i */
+#define AF_EBI_AD02_PORT(i)          ((i) == 0 ? 4 : (i) == 1 ? 1 :  -1)                                                                                             /**< Port number for AF_EBI_AD02 location number i */
+#define AF_EBI_AD03_PORT(i)          ((i) == 0 ? 4 : (i) == 1 ? 1 :  -1)                                                                                             /**< Port number for AF_EBI_AD03 location number i */
+#define AF_EBI_AD04_PORT(i)          ((i) == 0 ? 4 : (i) == 1 ? 1 :  -1)                                                                                             /**< Port number for AF_EBI_AD04 location number i */
+#define AF_EBI_AD05_PORT(i)          ((i) == 0 ? 4 : (i) == 1 ? 1 :  -1)                                                                                             /**< Port number for AF_EBI_AD05 location number i */
+#define AF_EBI_AD06_PORT(i)          ((i) == 0 ? 4 : (i) == 1 ? 1 :  -1)                                                                                             /**< Port number for AF_EBI_AD06 location number i */
+#define AF_EBI_AD07_PORT(i)          ((i) == 0 ? 4 : (i) == 1 ? 2 :  -1)                                                                                             /**< Port number for AF_EBI_AD07 location number i */
+#define AF_EBI_AD08_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 2 :  -1)                                                                                             /**< Port number for AF_EBI_AD08 location number i */
+#define AF_EBI_AD09_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 2 :  -1)                                                                                             /**< Port number for AF_EBI_AD09 location number i */
+#define AF_EBI_AD10_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 2 :  -1)                                                                                             /**< Port number for AF_EBI_AD10 location number i */
+#define AF_EBI_AD11_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 2 :  -1)                                                                                             /**< Port number for AF_EBI_AD11 location number i */
+#define AF_EBI_AD12_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 2 :  -1)                                                                                             /**< Port number for AF_EBI_AD12 location number i */
+#define AF_EBI_AD13_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 0 :  -1)                                                                                             /**< Port number for AF_EBI_AD13 location number i */
+#define AF_EBI_AD14_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 0 :  -1)                                                                                             /**< Port number for AF_EBI_AD14 location number i */
+#define AF_EBI_AD15_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 0 :  -1)                                                                                             /**< Port number for AF_EBI_AD15 location number i */
+#define AF_EBI_CS0_PORT(i)           ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 :  -1)                                                /**< Port number for AF_EBI_CS0 location number i */
+#define AF_EBI_CS1_PORT(i)           ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 :  -1)                                                /**< Port number for AF_EBI_CS1 location number i */
+#define AF_EBI_CS2_PORT(i)           ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 :  -1)                                                /**< Port number for AF_EBI_CS2 location number i */
+#define AF_EBI_CS3_PORT(i)           ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 :  -1)                                                /**< Port number for AF_EBI_CS3 location number i */
+#define AF_EBI_ARDY_PORT(i)          ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 :  -1)                                 /**< Port number for AF_EBI_ARDY location number i */
+#define AF_EBI_ALE_PORT(i)           ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 2 :  -1)                                 /**< Port number for AF_EBI_ALE location number i */
+#define AF_EBI_WEn_PORT(i)           ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 :  -1)                                 /**< Port number for AF_EBI_WEn location number i */
+#define AF_EBI_REn_PORT(i)           ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 :  -1)                                 /**< Port number for AF_EBI_REn location number i */
+#define AF_EBI_BL0_PORT(i)           ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 :  -1)                                 /**< Port number for AF_EBI_BL0 location number i */
+#define AF_EBI_BL1_PORT(i)           ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 :  -1)                                 /**< Port number for AF_EBI_BL1 location number i */
+#define AF_EBI_NANDWEn_PORT(i)       ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 :  -1)                                 /**< Port number for AF_EBI_NANDWEn location number i */
+#define AF_EBI_NANDREn_PORT(i)       ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 :  -1)                                 /**< Port number for AF_EBI_NANDREn location number i */
+#define AF_EBI_A00_PORT(i)           ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? -1 : (i) == 3 ? 2 :  -1)                                                              /**< Port number for AF_EBI_A00 location number i */
+#define AF_EBI_A01_PORT(i)           ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? -1 : (i) == 3 ? 0 :  -1)                                                              /**< Port number for AF_EBI_A01 location number i */
+#define AF_EBI_A02_PORT(i)           ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? -1 : (i) == 3 ? 0 :  -1)                                                              /**< Port number for AF_EBI_A02 location number i */
+#define AF_EBI_A03_PORT(i)           ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? -1 : (i) == 3 ? 0 :  -1)                                                              /**< Port number for AF_EBI_A03 location number i */
+#define AF_EBI_A04_PORT(i)           ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? 0 :  -1)                                                              /**< Port number for AF_EBI_A04 location number i */
+#define AF_EBI_A05_PORT(i)           ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? 0 :  -1)                                                              /**< Port number for AF_EBI_A05 location number i */
+#define AF_EBI_A06_PORT(i)           ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? 0 :  -1)                                                              /**< Port number for AF_EBI_A06 location number i */
+#define AF_EBI_A07_PORT(i)           ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? 0 :  -1)                                                              /**< Port number for AF_EBI_A07 location number i */
+#define AF_EBI_A08_PORT(i)           ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? 0 :  -1)                                                              /**< Port number for AF_EBI_A08 location number i */
+#define AF_EBI_A09_PORT(i)           ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? 1 :  -1)                                                              /**< Port number for AF_EBI_A09 location number i */
+#define AF_EBI_A10_PORT(i)           ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? 1 :  -1)                                                              /**< Port number for AF_EBI_A10 location number i */
+#define AF_EBI_A11_PORT(i)           ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? 1 :  -1)                                                              /**< Port number for AF_EBI_A11 location number i */
+#define AF_EBI_A12_PORT(i)           ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? 1 :  -1)                                                              /**< Port number for AF_EBI_A12 location number i */
+#define AF_EBI_A13_PORT(i)           ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? -1 : (i) == 3 ? 3 :  -1)                                                              /**< Port number for AF_EBI_A13 location number i */
+#define AF_EBI_A14_PORT(i)           ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? -1 : (i) == 3 ? 3 :  -1)                                                              /**< Port number for AF_EBI_A14 location number i */
+#define AF_EBI_A15_PORT(i)           ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? -1 : (i) == 3 ? 3 :  -1)                                                              /**< Port number for AF_EBI_A15 location number i */
+#define AF_EBI_A16_PORT(i)           ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? -1 : (i) == 3 ? 3 :  -1)                                                              /**< Port number for AF_EBI_A16 location number i */
+#define AF_EBI_A17_PORT(i)           ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? -1 : (i) == 3 ? 3 :  -1)                                                              /**< Port number for AF_EBI_A17 location number i */
+#define AF_EBI_A18_PORT(i)           ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? -1 : (i) == 3 ? 3 :  -1)                                                              /**< Port number for AF_EBI_A18 location number i */
+#define AF_EBI_A19_PORT(i)           ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? -1 : (i) == 3 ? 3 :  -1)                                                              /**< Port number for AF_EBI_A19 location number i */
+#define AF_EBI_A20_PORT(i)           ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? -1 : (i) == 3 ? 3 :  -1)                                                              /**< Port number for AF_EBI_A20 location number i */
+#define AF_EBI_A21_PORT(i)           ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? -1 : (i) == 3 ? 2 :  -1)                                                              /**< Port number for AF_EBI_A21 location number i */
+#define AF_EBI_A22_PORT(i)           ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? -1 : (i) == 3 ? 4 :  -1)                                                              /**< Port number for AF_EBI_A22 location number i */
+#define AF_EBI_A23_PORT(i)           ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? -1 : (i) == 3 ? 4 :  -1)                                                              /**< Port number for AF_EBI_A23 location number i */
+#define AF_EBI_A24_PORT(i)           ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? -1 : (i) == 3 ? 4 :  -1)                                                              /**< Port number for AF_EBI_A24 location number i */
+#define AF_EBI_A25_PORT(i)           ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? -1 : (i) == 3 ? 4 :  -1)                                                              /**< Port number for AF_EBI_A25 location number i */
+#define AF_EBI_A26_PORT(i)           ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? -1 : (i) == 3 ? 2 :  -1)                                                              /**< Port number for AF_EBI_A26 location number i */
+#define AF_EBI_A27_PORT(i)           ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? -1 : (i) == 3 ? 2 :  -1)                                                              /**< Port number for AF_EBI_A27 location number i */
+#define AF_EBI_CSTFT_PORT(i)         ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? -1 : (i) == 3 ? 0 :  -1)                                                              /**< Port number for AF_EBI_CSTFT location number i */
+#define AF_EBI_DCLK_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? -1 : (i) == 3 ? 0 :  -1)                                                              /**< Port number for AF_EBI_DCLK location number i */
+#define AF_EBI_DTEN_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? 0 :  -1)                                                              /**< Port number for AF_EBI_DTEN location number i */
+#define AF_EBI_VSNC_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? 0 :  -1)                                                              /**< Port number for AF_EBI_VSNC location number i */
+#define AF_EBI_HSNC_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? 0 :  -1)                                                              /**< Port number for AF_EBI_HSNC location number i */
+#define AF_SDIO_CLK_PORT(i)          ((i) == 0 ? 4 : (i) == 1 ? 4 :  -1)                                                                                             /**< Port number for AF_SDIO_CLK location number i */
+#define AF_SDIO_CMD_PORT(i)          ((i) == 0 ? 4 : (i) == 1 ? 4 :  -1)                                                                                             /**< Port number for AF_SDIO_CMD location number i */
+#define AF_SDIO_DAT0_PORT(i)         ((i) == 0 ? 4 : (i) == 1 ? 0 :  -1)                                                                                             /**< Port number for AF_SDIO_DAT0 location number i */
+#define AF_SDIO_DAT1_PORT(i)         ((i) == 0 ? 4 : (i) == 1 ? 0 :  -1)                                                                                             /**< Port number for AF_SDIO_DAT1 location number i */
+#define AF_SDIO_DAT2_PORT(i)         ((i) == 0 ? 4 : (i) == 1 ? 0 :  -1)                                                                                             /**< Port number for AF_SDIO_DAT2 location number i */
+#define AF_SDIO_DAT3_PORT(i)         ((i) == 0 ? 4 : (i) == 1 ? 0 :  -1)                                                                                             /**< Port number for AF_SDIO_DAT3 location number i */
+#define AF_SDIO_DAT4_PORT(i)         ((i) == 0 ? 3 : (i) == 1 ? 0 :  -1)                                                                                             /**< Port number for AF_SDIO_DAT4 location number i */
+#define AF_SDIO_DAT5_PORT(i)         ((i) == 0 ? 3 : (i) == 1 ? 0 :  -1)                                                                                             /**< Port number for AF_SDIO_DAT5 location number i */
+#define AF_SDIO_DAT6_PORT(i)         ((i) == 0 ? 3 : (i) == 1 ? 1 :  -1)                                                                                             /**< Port number for AF_SDIO_DAT6 location number i */
+#define AF_SDIO_DAT7_PORT(i)         ((i) == 0 ? 3 : (i) == 1 ? 1 :  -1)                                                                                             /**< Port number for AF_SDIO_DAT7 location number i */
+#define AF_SDIO_CD_PORT(i)           ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 1 :  -1)                                                               /**< Port number for AF_SDIO_CD location number i */
+#define AF_SDIO_WP_PORT(i)           ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 1 : (i) == 3 ? 1 :  -1)                                                               /**< Port number for AF_SDIO_WP location number i */
+#define AF_PDM_CLK_PORT(i)           ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 1 : (i) == 4 ? 3 :  -1)                                                /**< Port number for AF_PDM_CLK location number i */
+#define AF_PDM_DAT0_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 1 : (i) == 4 ? 3 :  -1)                                                /**< Port number for AF_PDM_DAT0 location number i */
+#define AF_PDM_DAT1_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 1 : (i) == 4 ? 3 :  -1)                                                /**< Port number for AF_PDM_DAT1 location number i */
+#define AF_PDM_DAT2_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 1 : (i) == 4 ? 3 :  -1)                                                /**< Port number for AF_PDM_DAT2 location number i */
+#define AF_PDM_DAT3_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 3 :  -1)                                                /**< Port number for AF_PDM_DAT3 location number i */
+#define AF_PRS_CH0_PORT(i)           ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 5 :  -1)                                                               /**< Port number for AF_PRS_CH0 location number i */
+#define AF_PRS_CH1_PORT(i)           ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 4 :  -1)                                                               /**< Port number for AF_PRS_CH1 location number i */
+#define AF_PRS_CH2_PORT(i)           ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 4 :  -1)                                                               /**< Port number for AF_PRS_CH2 location number i */
+#define AF_PRS_CH3_PORT(i)           ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 0 :  -1)                                                               /**< Port number for AF_PRS_CH3 location number i */
+#define AF_PRS_CH4_PORT(i)           ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 5 :  -1)                                                                              /**< Port number for AF_PRS_CH4 location number i */
+#define AF_PRS_CH5_PORT(i)           ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 :  -1)                                                                              /**< Port number for AF_PRS_CH5 location number i */
+#define AF_PRS_CH6_PORT(i)           ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 :  -1)                                                                              /**< Port number for AF_PRS_CH6 location number i */
+#define AF_PRS_CH7_PORT(i)           ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 4 :  -1)                                                                              /**< Port number for AF_PRS_CH7 location number i */
+#define AF_PRS_CH8_PORT(i)           ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 4 :  -1)                                                                              /**< Port number for AF_PRS_CH8 location number i */
+#define AF_PRS_CH9_PORT(i)           ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 :  -1)                                                                              /**< Port number for AF_PRS_CH9 location number i */
+#define AF_PRS_CH10_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 :  -1)                                                                              /**< Port number for AF_PRS_CH10 location number i */
+#define AF_PRS_CH11_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 :  -1)                                                                              /**< Port number for AF_PRS_CH11 location number i */
+#define AF_PRS_CH12_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 :  -1)                                                                              /**< Port number for AF_PRS_CH12 location number i */
+#define AF_PRS_CH13_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 :  -1)                                                                              /**< Port number for AF_PRS_CH13 location number i */
+#define AF_PRS_CH14_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 4 :  -1)                                                                              /**< Port number for AF_PRS_CH14 location number i */
+#define AF_PRS_CH15_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 :  -1)                                                                              /**< Port number for AF_PRS_CH15 location number i */
+#define AF_CAN0_RX_PORT(i)           ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? -1 : (i) == 5 ? 3 : (i) == 6 ? 4 :  -1)                 /**< Port number for AF_CAN0_RX location number i */
+#define AF_CAN0_TX_PORT(i)           ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? -1 : (i) == 5 ? 3 : (i) == 6 ? 4 :  -1)                 /**< Port number for AF_CAN0_TX location number i */
+#define AF_CAN1_RX_PORT(i)           ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 :  -1)                                 /**< Port number for AF_CAN1_RX location number i */
+#define AF_CAN1_TX_PORT(i)           ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 :  -1)                                 /**< Port number for AF_CAN1_TX location number i */
+#define AF_TIMER0_CC0_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 :  -1)   /**< Port number for AF_TIMER0_CC0 location number i */
+#define AF_TIMER0_CC1_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 :  -1)   /**< Port number for AF_TIMER0_CC1 location number i */
+#define AF_TIMER0_CC2_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 :  -1)   /**< Port number for AF_TIMER0_CC2 location number i */
+#define AF_TIMER0_CC3_PORT(i)        (-1)                                                                                                                            /**< Port number for AF_TIMER0_CC3 location number i */
+#define AF_TIMER0_CDTI0_PORT(i)      ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 :  -1)                                                /**< Port number for AF_TIMER0_CDTI0 location number i */
+#define AF_TIMER0_CDTI1_PORT(i)      ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 :  -1)                                                /**< Port number for AF_TIMER0_CDTI1 location number i */
+#define AF_TIMER0_CDTI2_PORT(i)      ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 :  -1)                                                /**< Port number for AF_TIMER0_CDTI2 location number i */
+#define AF_TIMER0_CDTI3_PORT(i)      (-1)                                                                                                                            /**< Port number for AF_TIMER0_CDTI3 location number i */
+#define AF_TIMER1_CC0_PORT(i)        ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 :  -1)                  /**< Port number for AF_TIMER1_CC0 location number i */
+#define AF_TIMER1_CC1_PORT(i)        ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 :  -1)                  /**< Port number for AF_TIMER1_CC1 location number i */
+#define AF_TIMER1_CC2_PORT(i)        ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 :  -1)                                 /**< Port number for AF_TIMER1_CC2 location number i */
+#define AF_TIMER1_CC3_PORT(i)        ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 :  -1)                  /**< Port number for AF_TIMER1_CC3 location number i */
+#define AF_TIMER1_CDTI0_PORT(i)      (-1)                                                                                                                            /**< Port number for AF_TIMER1_CDTI0 location number i */
+#define AF_TIMER1_CDTI1_PORT(i)      (-1)                                                                                                                            /**< Port number for AF_TIMER1_CDTI1 location number i */
+#define AF_TIMER1_CDTI2_PORT(i)      (-1)                                                                                                                            /**< Port number for AF_TIMER1_CDTI2 location number i */
+#define AF_TIMER1_CDTI3_PORT(i)      (-1)                                                                                                                            /**< Port number for AF_TIMER1_CDTI3 location number i */
+#define AF_TIMER2_CC0_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 1 : (i) == 5 ? 2 :  -1)                                 /**< Port number for AF_TIMER2_CC0 location number i */
+#define AF_TIMER2_CC1_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 :  -1)                                 /**< Port number for AF_TIMER2_CC1 location number i */
+#define AF_TIMER2_CC2_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 :  -1)                                 /**< Port number for AF_TIMER2_CC2 location number i */
+#define AF_TIMER2_CC3_PORT(i)        (-1)                                                                                                                            /**< Port number for AF_TIMER2_CC3 location number i */
+#define AF_TIMER2_CDTI0_PORT(i)      ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 :  -1)                                                                              /**< Port number for AF_TIMER2_CDTI0 location number i */
+#define AF_TIMER2_CDTI1_PORT(i)      ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 :  -1)                                                                              /**< Port number for AF_TIMER2_CDTI1 location number i */
+#define AF_TIMER2_CDTI2_PORT(i)      ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 :  -1)                                                                              /**< Port number for AF_TIMER2_CDTI2 location number i */
+#define AF_TIMER2_CDTI3_PORT(i)      (-1)                                                                                                                            /**< Port number for AF_TIMER2_CDTI3 location number i */
+#define AF_TIMER3_CC0_PORT(i)        ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 3 :  -1)   /**< Port number for AF_TIMER3_CC0 location number i */
+#define AF_TIMER3_CC1_PORT(i)        ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 :  -1)   /**< Port number for AF_TIMER3_CC1 location number i */
+#define AF_TIMER3_CC2_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 :  -1)   /**< Port number for AF_TIMER3_CC2 location number i */
+#define AF_TIMER3_CC3_PORT(i)        (-1)                                                                                                                            /**< Port number for AF_TIMER3_CC3 location number i */
+#define AF_TIMER3_CDTI0_PORT(i)      (-1)                                                                                                                            /**< Port number for AF_TIMER3_CDTI0 location number i */
+#define AF_TIMER3_CDTI1_PORT(i)      (-1)                                                                                                                            /**< Port number for AF_TIMER3_CDTI1 location number i */
+#define AF_TIMER3_CDTI2_PORT(i)      (-1)                                                                                                                            /**< Port number for AF_TIMER3_CDTI2 location number i */
+#define AF_TIMER3_CDTI3_PORT(i)      (-1)                                                                                                                            /**< Port number for AF_TIMER3_CDTI3 location number i */
+#define AF_WTIMER0_CC0_PORT(i)       ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 :  -1) /**< Port number for AF_WTIMER0_CC0 location number i */
+#define AF_WTIMER0_CC1_PORT(i)       ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 :  -1) /**< Port number for AF_WTIMER0_CC1 location number i */
+#define AF_WTIMER0_CC2_PORT(i)       ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 :  -1) /**< Port number for AF_WTIMER0_CC2 location number i */
+#define AF_WTIMER0_CC3_PORT(i)       (-1)                                                                                                                            /**< Port number for AF_WTIMER0_CC3 location number i */
+#define AF_WTIMER0_CDTI0_PORT(i)     ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? -1 : (i) == 4 ? 3 :  -1)                                               /**< Port number for AF_WTIMER0_CDTI0 location number i */
+#define AF_WTIMER0_CDTI1_PORT(i)     ((i) == 0 ? 4 : (i) == 1 ? -1 : (i) == 2 ? 0 : (i) == 3 ? -1 : (i) == 4 ? 3 :  -1)                                              /**< Port number for AF_WTIMER0_CDTI1 location number i */
+#define AF_WTIMER0_CDTI2_PORT(i)     ((i) == 0 ? 4 : (i) == 1 ? -1 : (i) == 2 ? 0 : (i) == 3 ? -1 : (i) == 4 ? 3 :  -1)                                              /**< Port number for AF_WTIMER0_CDTI2 location number i */
+#define AF_WTIMER0_CDTI3_PORT(i)     (-1)                                                                                                                            /**< Port number for AF_WTIMER0_CDTI3 location number i */
+#define AF_WTIMER1_CC0_PORT(i)       ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 4 :  -1)                                 /**< Port number for AF_WTIMER1_CC0 location number i */
+#define AF_WTIMER1_CC1_PORT(i)       ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 :  -1)                                                /**< Port number for AF_WTIMER1_CC1 location number i */
+#define AF_WTIMER1_CC2_PORT(i)       ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 :  -1)                                                /**< Port number for AF_WTIMER1_CC2 location number i */
+#define AF_WTIMER1_CC3_PORT(i)       ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 4 :  -1)                                                /**< Port number for AF_WTIMER1_CC3 location number i */
+#define AF_WTIMER1_CDTI0_PORT(i)     (-1)                                                                                                                            /**< Port number for AF_WTIMER1_CDTI0 location number i */
+#define AF_WTIMER1_CDTI1_PORT(i)     (-1)                                                                                                                            /**< Port number for AF_WTIMER1_CDTI1 location number i */
+#define AF_WTIMER1_CDTI2_PORT(i)     (-1)                                                                                                                            /**< Port number for AF_WTIMER1_CDTI2 location number i */
+#define AF_WTIMER1_CDTI3_PORT(i)     (-1)                                                                                                                            /**< Port number for AF_WTIMER1_CDTI3 location number i */
+#define AF_USART0_TX_PORT(i)         ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 :  -1)                                 /**< Port number for AF_USART0_TX location number i */
+#define AF_USART0_RX_PORT(i)         ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 :  -1)                                 /**< Port number for AF_USART0_RX location number i */
+#define AF_USART0_CLK_PORT(i)        ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 :  -1)                                 /**< Port number for AF_USART0_CLK location number i */
+#define AF_USART0_CS_PORT(i)         ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 :  -1)                                 /**< Port number for AF_USART0_CS location number i */
+#define AF_USART0_CTS_PORT(i)        ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 :  -1)                                 /**< Port number for AF_USART0_CTS location number i */
+#define AF_USART0_RTS_PORT(i)        ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 :  -1)                                 /**< Port number for AF_USART0_RTS location number i */
+#define AF_USART1_TX_PORT(i)         ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 0 :  -1)                  /**< Port number for AF_USART1_TX location number i */
+#define AF_USART1_RX_PORT(i)         ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 0 :  -1)                  /**< Port number for AF_USART1_RX location number i */
+#define AF_USART1_CLK_PORT(i)        ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 4 :  -1)                  /**< Port number for AF_USART1_CLK location number i */
+#define AF_USART1_CS_PORT(i)         ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 4 : (i) == 6 ? 1 :  -1)                  /**< Port number for AF_USART1_CS location number i */
+#define AF_USART1_CTS_PORT(i)        ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 :  -1)                                 /**< Port number for AF_USART1_CTS location number i */
+#define AF_USART1_RTS_PORT(i)        ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 :  -1)                                 /**< Port number for AF_USART1_RTS location number i */
+#define AF_USART2_TX_PORT(i)         ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 :  -1)                                 /**< Port number for AF_USART2_TX location number i */
+#define AF_USART2_RX_PORT(i)         ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 :  -1)                                 /**< Port number for AF_USART2_RX location number i */
+#define AF_USART2_CLK_PORT(i)        ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 :  -1)                                 /**< Port number for AF_USART2_CLK location number i */
+#define AF_USART2_CS_PORT(i)         ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 :  -1)                                 /**< Port number for AF_USART2_CS location number i */
+#define AF_USART2_CTS_PORT(i)        ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 :  -1)                                 /**< Port number for AF_USART2_CTS location number i */
+#define AF_USART2_RTS_PORT(i)        ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 3 :  -1)                                 /**< Port number for AF_USART2_RTS location number i */
+#define AF_USART3_TX_PORT(i)         ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 :  -1)                                                                              /**< Port number for AF_USART3_TX location number i */
+#define AF_USART3_RX_PORT(i)         ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 :  -1)                                                                              /**< Port number for AF_USART3_RX location number i */
+#define AF_USART3_CLK_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 3 :  -1)                                                                              /**< Port number for AF_USART3_CLK location number i */
+#define AF_USART3_CS_PORT(i)         ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 :  -1)                                                               /**< Port number for AF_USART3_CS location number i */
+#define AF_USART3_CTS_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 3 :  -1)                                                                              /**< Port number for AF_USART3_CTS location number i */
+#define AF_USART3_RTS_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 2 :  -1)                                                               /**< Port number for AF_USART3_RTS location number i */
+#define AF_USART4_TX_PORT(i)         ((i) == 0 ? 1 : (i) == 1 ? 3 :  -1)                                                                                             /**< Port number for AF_USART4_TX location number i */
+#define AF_USART4_RX_PORT(i)         ((i) == 0 ? 1 : (i) == 1 ? 3 :  -1)                                                                                             /**< Port number for AF_USART4_RX location number i */
+#define AF_USART4_CLK_PORT(i)        ((i) == 0 ? 2 : (i) == 1 ? 3 :  -1)                                                                                             /**< Port number for AF_USART4_CLK location number i */
+#define AF_USART4_CS_PORT(i)         ((i) == 0 ? 2 : (i) == 1 ? 3 :  -1)                                                                                             /**< Port number for AF_USART4_CS location number i */
+#define AF_USART4_CTS_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 3 :  -1)                                                                                             /**< Port number for AF_USART4_CTS location number i */
+#define AF_USART4_RTS_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 3 :  -1)                                                                                             /**< Port number for AF_USART4_RTS location number i */
+#define AF_UART0_TX_PORT(i)          ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 3 :  -1)                  /**< Port number for AF_UART0_TX location number i */
+#define AF_UART0_RX_PORT(i)          ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 :  -1)                  /**< Port number for AF_UART0_RX location number i */
+#define AF_UART0_CLK_PORT(i)         (-1)                                                                                                                            /**< Port number for AF_UART0_CLK location number i */
+#define AF_UART0_CS_PORT(i)          (-1)                                                                                                                            /**< Port number for AF_UART0_CS location number i */
+#define AF_UART0_CTS_PORT(i)         ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 :  -1)                                 /**< Port number for AF_UART0_CTS location number i */
+#define AF_UART0_RTS_PORT(i)         ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 :  -1)                                 /**< Port number for AF_UART0_RTS location number i */
+#define AF_UART1_TX_PORT(i)          ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 :  -1)                                                /**< Port number for AF_UART1_TX location number i */
+#define AF_UART1_RX_PORT(i)          ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 :  -1)                                                /**< Port number for AF_UART1_RX location number i */
+#define AF_UART1_CLK_PORT(i)         (-1)                                                                                                                            /**< Port number for AF_UART1_CLK location number i */
+#define AF_UART1_CS_PORT(i)          (-1)                                                                                                                            /**< Port number for AF_UART1_CS location number i */
+#define AF_UART1_CTS_PORT(i)         ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 :  -1)                                                /**< Port number for AF_UART1_CTS location number i */
+#define AF_UART1_RTS_PORT(i)         ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 :  -1)                                                /**< Port number for AF_UART1_RTS location number i */
+#define AF_QSPI0_SCLK_PORT(i)        ((i) == 0 ? 5 : (i) == 1 ? 4 :  -1)                                                                                             /**< Port number for AF_QSPI0_SCLK location number i */
+#define AF_QSPI0_DQ0_PORT(i)         ((i) == 0 ? 3 : (i) == 1 ? 0 :  -1)                                                                                             /**< Port number for AF_QSPI0_DQ0 location number i */
+#define AF_QSPI0_DQ1_PORT(i)         ((i) == 0 ? 3 : (i) == 1 ? 0 :  -1)                                                                                             /**< Port number for AF_QSPI0_DQ1 location number i */
+#define AF_QSPI0_DQ2_PORT(i)         ((i) == 0 ? 3 : (i) == 1 ? 0 :  -1)                                                                                             /**< Port number for AF_QSPI0_DQ2 location number i */
+#define AF_QSPI0_DQ3_PORT(i)         ((i) == 0 ? 3 : (i) == 1 ? 0 :  -1)                                                                                             /**< Port number for AF_QSPI0_DQ3 location number i */
+#define AF_QSPI0_DQ4_PORT(i)         ((i) == 0 ? 4 : (i) == 1 ? 1 :  -1)                                                                                             /**< Port number for AF_QSPI0_DQ4 location number i */
+#define AF_QSPI0_DQ5_PORT(i)         ((i) == 0 ? 4 : (i) == 1 ? 1 :  -1)                                                                                             /**< Port number for AF_QSPI0_DQ5 location number i */
+#define AF_QSPI0_DQ6_PORT(i)         ((i) == 0 ? 4 : (i) == 1 ? 1 :  -1)                                                                                             /**< Port number for AF_QSPI0_DQ6 location number i */
+#define AF_QSPI0_DQ7_PORT(i)         ((i) == 0 ? 4 : (i) == 1 ? 1 :  -1)                                                                                             /**< Port number for AF_QSPI0_DQ7 location number i */
+#define AF_QSPI0_CS0_PORT(i)         ((i) == 0 ? 5 : (i) == 1 ? 0 :  -1)                                                                                             /**< Port number for AF_QSPI0_CS0 location number i */
+#define AF_QSPI0_CS1_PORT(i)         ((i) == 0 ? 5 : (i) == 1 ? 0 :  -1)                                                                                             /**< Port number for AF_QSPI0_CS1 location number i */
+#define AF_QSPI0_DQS_PORT(i)         ((i) == 0 ? 5 : (i) == 1 ? 4 :  -1)                                                                                             /**< Port number for AF_QSPI0_DQS location number i */
+#define AF_QSPI0_RST0_PORT(i)        ((i) == 0 ? 4 : (i) == 1 ? 2 :  -1)                                                                                             /**< Port number for AF_QSPI0_RST0 location number i */
+#define AF_QSPI0_RST1_PORT(i)        ((i) == 0 ? 4 : (i) == 1 ? 2 :  -1)                                                                                             /**< Port number for AF_QSPI0_RST1 location number i */
+#define AF_LEUART0_TX_PORT(i)        ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 2 :  -1)                                 /**< Port number for AF_LEUART0_TX location number i */
+#define AF_LEUART0_RX_PORT(i)        ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 2 :  -1)                                 /**< Port number for AF_LEUART0_RX location number i */
+#define AF_LEUART1_TX_PORT(i)        ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 :  -1)                                                /**< Port number for AF_LEUART1_TX location number i */
+#define AF_LEUART1_RX_PORT(i)        ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 :  -1)                                                /**< Port number for AF_LEUART1_RX location number i */
+#define AF_LETIMER0_OUT0_PORT(i)     ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 :  -1)   /**< Port number for AF_LETIMER0_OUT0 location number i */
+#define AF_LETIMER0_OUT1_PORT(i)     ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 :  -1)   /**< Port number for AF_LETIMER0_OUT1 location number i */
+#define AF_LETIMER1_OUT0_PORT(i)     ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 :  -1)                                 /**< Port number for AF_LETIMER1_OUT0 location number i */
+#define AF_LETIMER1_OUT1_PORT(i)     ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 :  -1)                                 /**< Port number for AF_LETIMER1_OUT1 location number i */
+#define AF_PCNT0_S0IN_PORT(i)        ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 :  -1)   /**< Port number for AF_PCNT0_S0IN location number i */
+#define AF_PCNT0_S1IN_PORT(i)        ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 :  -1)   /**< Port number for AF_PCNT0_S1IN location number i */
+#define AF_PCNT1_S0IN_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 :  -1)                  /**< Port number for AF_PCNT1_S0IN location number i */
+#define AF_PCNT1_S1IN_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 :  -1)                  /**< Port number for AF_PCNT1_S1IN location number i */
+#define AF_PCNT2_S0IN_PORT(i)        ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 :  -1)                                                /**< Port number for AF_PCNT2_S0IN location number i */
+#define AF_PCNT2_S1IN_PORT(i)        ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 :  -1)                                                /**< Port number for AF_PCNT2_S1IN location number i */
+#define AF_I2C0_SDA_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 :  -1)   /**< Port number for AF_I2C0_SDA location number i */
+#define AF_I2C0_SCL_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 :  -1)   /**< Port number for AF_I2C0_SCL location number i */
+#define AF_I2C1_SDA_PORT(i)          ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 2 :  -1)                                                /**< Port number for AF_I2C1_SDA location number i */
+#define AF_I2C1_SCL_PORT(i)          ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 5 :  -1)                                                /**< Port number for AF_I2C1_SCL location number i */
+#define AF_ACMP0_OUT_PORT(i)         ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 :  -1)   /**< Port number for AF_ACMP0_OUT location number i */
+#define AF_ACMP1_OUT_PORT(i)         ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 0 :  -1)   /**< Port number for AF_ACMP1_OUT location number i */
+#define AF_ACMP2_OUT_PORT(i)         ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 4 :  -1)                                                                              /**< Port number for AF_ACMP2_OUT location number i */
+#define AF_USB_VBUSEN_PORT(i)        ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 3 :  -1)                                                                              /**< Port number for AF_USB_VBUSEN location number i */
+#define AF_DBG_TDI_PORT(i)           ((i) == 0 ? 5 :  -1)                                                                                                            /**< Port number for AF_DBG_TDI location number i */
+#define AF_DBG_TDO_PORT(i)           ((i) == 0 ? 5 :  -1)                                                                                                            /**< Port number for AF_DBG_TDO location number i */
+#define AF_DBG_SWV_PORT(i)           ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 3 :  -1)                                                               /**< Port number for AF_DBG_SWV location number i */
+#define AF_DBG_SWDIOTMS_PORT(i)      ((i) == 0 ? 5 :  -1)                                                                                                            /**< Port number for AF_DBG_SWDIOTMS location number i */
+#define AF_DBG_SWCLKTCK_PORT(i)      ((i) == 0 ? 5 :  -1)                                                                                                            /**< Port number for AF_DBG_SWCLKTCK location number i */
+#define AF_ETM_TCLK_PORT(i)          ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 :  -1)                                                /**< Port number for AF_ETM_TCLK location number i */
+#define AF_ETM_TD0_PORT(i)           ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 :  -1)                                                /**< Port number for AF_ETM_TD0 location number i */
+#define AF_ETM_TD1_PORT(i)           ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 :  -1)                                                /**< Port number for AF_ETM_TD1 location number i */
+#define AF_ETM_TD2_PORT(i)           ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 :  -1)                                                /**< Port number for AF_ETM_TD2 location number i */
+#define AF_ETM_TD3_PORT(i)           ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 :  -1)                                                /**< Port number for AF_ETM_TD3 location number i */
+
+/** @} */
+/** @} End of group EFM32GG12B_AF_Ports */
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+

cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b_can.h

@@ -0,0 +1,648 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32GG12B_CAN register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFM32GG12B_CAN CAN
+ * @{
+ * @brief EFM32GG12B_CAN Register Declaration
+ ******************************************************************************/
+/** CAN Register Declaration */
+typedef struct {
+  __IOM uint32_t  CTRL;          /**< Control Register  */
+  __IOM uint32_t  STATUS;        /**< Status Register  */
+  __IM uint32_t   ERRCNT;        /**< Error Count Register  */
+  __IOM uint32_t  BITTIMING;     /**< Bit Timing Register  */
+  __IM uint32_t   INTID;         /**< Interrupt Identification Register  */
+  __IOM uint32_t  TEST;          /**< Test Register  */
+  __IOM uint32_t  BRPE;          /**< BRP Extension Register  */
+  __IM uint32_t   TRANSREQ;      /**< Transmission Request Register  */
+  __IM uint32_t   MESSAGEDATA;   /**< New Data Register  */
+
+  uint32_t        RESERVED0[1U]; /**< Reserved for future use **/
+  __IM uint32_t   MESSAGESTATE;  /**< Message Valid Register  */
+  __IOM uint32_t  CONFIG;        /**< Configuration Register  */
+  __IM uint32_t   IF0IF;         /**< Message Object Interrupt Flag Register  */
+  __IOM uint32_t  IF0IFS;        /**< Message Object Interrupt Flag Set Register  */
+  __IOM uint32_t  IF0IFC;        /**< Message Object Interrupt Flag Clear Register  */
+  __IOM uint32_t  IF0IEN;        /**< Message Object Interrupt Enable Register  */
+  __IM uint32_t   IF1IF;         /**< Status Interrupt Flag Register  */
+  __IOM uint32_t  IF1IFS;        /**< Message Object Interrupt Flag Set Register  */
+  __IOM uint32_t  IF1IFC;        /**< Message Object Interrupt Flag Clear Register  */
+  __IOM uint32_t  IF1IEN;        /**< Status Interrupt Enable Register  */
+  __IOM uint32_t  ROUTE;         /**< I/O Routing Register  */
+
+  uint32_t        RESERVED1[3U]; /**< Reserved registers */
+  CAN_MIR_TypeDef MIR[2U];       /**< Interface Registers */
+} CAN_TypeDef;                   /** @} */
+
+/***************************************************************************//**
+ * @addtogroup EFM32GG12B_CAN
+ * @{
+ * @defgroup EFM32GG12B_CAN_BitFields  CAN Bit Fields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for CAN CTRL */
+#define _CAN_CTRL_RESETVALUE                     0x00000001UL                  /**< Default value for CAN_CTRL */
+#define _CAN_CTRL_MASK                           0x000000EFUL                  /**< Mask for CAN_CTRL */
+#define CAN_CTRL_INIT                            (0x1UL << 0)                  /**< Initialize */
+#define _CAN_CTRL_INIT_SHIFT                     0                             /**< Shift value for CAN_INIT */
+#define _CAN_CTRL_INIT_MASK                      0x1UL                         /**< Bit mask for CAN_INIT */
+#define _CAN_CTRL_INIT_DEFAULT                   0x00000001UL                  /**< Mode DEFAULT for CAN_CTRL */
+#define CAN_CTRL_INIT_DEFAULT                    (_CAN_CTRL_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_CTRL */
+#define CAN_CTRL_IE                              (0x1UL << 1)                  /**< Module Interrupt Enable */
+#define _CAN_CTRL_IE_SHIFT                       1                             /**< Shift value for CAN_IE */
+#define _CAN_CTRL_IE_MASK                        0x2UL                         /**< Bit mask for CAN_IE */
+#define _CAN_CTRL_IE_DEFAULT                     0x00000000UL                  /**< Mode DEFAULT for CAN_CTRL */
+#define CAN_CTRL_IE_DEFAULT                      (_CAN_CTRL_IE_DEFAULT << 1)   /**< Shifted mode DEFAULT for CAN_CTRL */
+#define CAN_CTRL_SIE                             (0x1UL << 2)                  /**< Status Change Interrupt Enable */
+#define _CAN_CTRL_SIE_SHIFT                      2                             /**< Shift value for CAN_SIE */
+#define _CAN_CTRL_SIE_MASK                       0x4UL                         /**< Bit mask for CAN_SIE */
+#define _CAN_CTRL_SIE_DEFAULT                    0x00000000UL                  /**< Mode DEFAULT for CAN_CTRL */
+#define CAN_CTRL_SIE_DEFAULT                     (_CAN_CTRL_SIE_DEFAULT << 2)  /**< Shifted mode DEFAULT for CAN_CTRL */
+#define CAN_CTRL_EIE                             (0x1UL << 3)                  /**< Error Interrupt Enable */
+#define _CAN_CTRL_EIE_SHIFT                      3                             /**< Shift value for CAN_EIE */
+#define _CAN_CTRL_EIE_MASK                       0x8UL                         /**< Bit mask for CAN_EIE */
+#define _CAN_CTRL_EIE_DEFAULT                    0x00000000UL                  /**< Mode DEFAULT for CAN_CTRL */
+#define CAN_CTRL_EIE_DEFAULT                     (_CAN_CTRL_EIE_DEFAULT << 3)  /**< Shifted mode DEFAULT for CAN_CTRL */
+#define CAN_CTRL_DAR                             (0x1UL << 5)                  /**< Disable Automatic Retransmission */
+#define _CAN_CTRL_DAR_SHIFT                      5                             /**< Shift value for CAN_DAR */
+#define _CAN_CTRL_DAR_MASK                       0x20UL                        /**< Bit mask for CAN_DAR */
+#define _CAN_CTRL_DAR_DEFAULT                    0x00000000UL                  /**< Mode DEFAULT for CAN_CTRL */
+#define CAN_CTRL_DAR_DEFAULT                     (_CAN_CTRL_DAR_DEFAULT << 5)  /**< Shifted mode DEFAULT for CAN_CTRL */
+#define CAN_CTRL_CCE                             (0x1UL << 6)                  /**< Configuration Change Enable */
+#define _CAN_CTRL_CCE_SHIFT                      6                             /**< Shift value for CAN_CCE */
+#define _CAN_CTRL_CCE_MASK                       0x40UL                        /**< Bit mask for CAN_CCE */
+#define _CAN_CTRL_CCE_DEFAULT                    0x00000000UL                  /**< Mode DEFAULT for CAN_CTRL */
+#define CAN_CTRL_CCE_DEFAULT                     (_CAN_CTRL_CCE_DEFAULT << 6)  /**< Shifted mode DEFAULT for CAN_CTRL */
+#define CAN_CTRL_TEST                            (0x1UL << 7)                  /**< Test Mode Enable Write */
+#define _CAN_CTRL_TEST_SHIFT                     7                             /**< Shift value for CAN_TEST */
+#define _CAN_CTRL_TEST_MASK                      0x80UL                        /**< Bit mask for CAN_TEST */
+#define _CAN_CTRL_TEST_DEFAULT                   0x00000000UL                  /**< Mode DEFAULT for CAN_CTRL */
+#define CAN_CTRL_TEST_DEFAULT                    (_CAN_CTRL_TEST_DEFAULT << 7) /**< Shifted mode DEFAULT for CAN_CTRL */
+
+/* Bit fields for CAN STATUS */
+#define _CAN_STATUS_RESETVALUE                   0x00000000UL                     /**< Default value for CAN_STATUS */
+#define _CAN_STATUS_MASK                         0x000000FFUL                     /**< Mask for CAN_STATUS */
+#define _CAN_STATUS_LEC_SHIFT                    0                                /**< Shift value for CAN_LEC */
+#define _CAN_STATUS_LEC_MASK                     0x7UL                            /**< Bit mask for CAN_LEC */
+#define _CAN_STATUS_LEC_DEFAULT                  0x00000000UL                     /**< Mode DEFAULT for CAN_STATUS */
+#define _CAN_STATUS_LEC_NONE                     0x00000000UL                     /**< Mode NONE for CAN_STATUS */
+#define _CAN_STATUS_LEC_STUFF                    0x00000001UL                     /**< Mode STUFF for CAN_STATUS */
+#define _CAN_STATUS_LEC_FORM                     0x00000002UL                     /**< Mode FORM for CAN_STATUS */
+#define _CAN_STATUS_LEC_ACK                      0x00000003UL                     /**< Mode ACK for CAN_STATUS */
+#define _CAN_STATUS_LEC_BIT1                     0x00000004UL                     /**< Mode BIT1 for CAN_STATUS */
+#define _CAN_STATUS_LEC_BIT0                     0x00000005UL                     /**< Mode BIT0 for CAN_STATUS */
+#define _CAN_STATUS_LEC_CRC                      0x00000006UL                     /**< Mode CRC for CAN_STATUS */
+#define _CAN_STATUS_LEC_UNUSED                   0x00000007UL                     /**< Mode UNUSED for CAN_STATUS */
+#define CAN_STATUS_LEC_DEFAULT                   (_CAN_STATUS_LEC_DEFAULT << 0)   /**< Shifted mode DEFAULT for CAN_STATUS */
+#define CAN_STATUS_LEC_NONE                      (_CAN_STATUS_LEC_NONE << 0)      /**< Shifted mode NONE for CAN_STATUS */
+#define CAN_STATUS_LEC_STUFF                     (_CAN_STATUS_LEC_STUFF << 0)     /**< Shifted mode STUFF for CAN_STATUS */
+#define CAN_STATUS_LEC_FORM                      (_CAN_STATUS_LEC_FORM << 0)      /**< Shifted mode FORM for CAN_STATUS */
+#define CAN_STATUS_LEC_ACK                       (_CAN_STATUS_LEC_ACK << 0)       /**< Shifted mode ACK for CAN_STATUS */
+#define CAN_STATUS_LEC_BIT1                      (_CAN_STATUS_LEC_BIT1 << 0)      /**< Shifted mode BIT1 for CAN_STATUS */
+#define CAN_STATUS_LEC_BIT0                      (_CAN_STATUS_LEC_BIT0 << 0)      /**< Shifted mode BIT0 for CAN_STATUS */
+#define CAN_STATUS_LEC_CRC                       (_CAN_STATUS_LEC_CRC << 0)       /**< Shifted mode CRC for CAN_STATUS */
+#define CAN_STATUS_LEC_UNUSED                    (_CAN_STATUS_LEC_UNUSED << 0)    /**< Shifted mode UNUSED for CAN_STATUS */
+#define CAN_STATUS_TXOK                          (0x1UL << 3)                     /**< Transmitted a Message Successfully */
+#define _CAN_STATUS_TXOK_SHIFT                   3                                /**< Shift value for CAN_TXOK */
+#define _CAN_STATUS_TXOK_MASK                    0x8UL                            /**< Bit mask for CAN_TXOK */
+#define _CAN_STATUS_TXOK_DEFAULT                 0x00000000UL                     /**< Mode DEFAULT for CAN_STATUS */
+#define CAN_STATUS_TXOK_DEFAULT                  (_CAN_STATUS_TXOK_DEFAULT << 3)  /**< Shifted mode DEFAULT for CAN_STATUS */
+#define CAN_STATUS_RXOK                          (0x1UL << 4)                     /**< Received a Message Successfully */
+#define _CAN_STATUS_RXOK_SHIFT                   4                                /**< Shift value for CAN_RXOK */
+#define _CAN_STATUS_RXOK_MASK                    0x10UL                           /**< Bit mask for CAN_RXOK */
+#define _CAN_STATUS_RXOK_DEFAULT                 0x00000000UL                     /**< Mode DEFAULT for CAN_STATUS */
+#define CAN_STATUS_RXOK_DEFAULT                  (_CAN_STATUS_RXOK_DEFAULT << 4)  /**< Shifted mode DEFAULT for CAN_STATUS */
+#define CAN_STATUS_EPASS                         (0x1UL << 5)                     /**< Error Passive */
+#define _CAN_STATUS_EPASS_SHIFT                  5                                /**< Shift value for CAN_EPASS */
+#define _CAN_STATUS_EPASS_MASK                   0x20UL                           /**< Bit mask for CAN_EPASS */
+#define _CAN_STATUS_EPASS_DEFAULT                0x00000000UL                     /**< Mode DEFAULT for CAN_STATUS */
+#define CAN_STATUS_EPASS_DEFAULT                 (_CAN_STATUS_EPASS_DEFAULT << 5) /**< Shifted mode DEFAULT for CAN_STATUS */
+#define CAN_STATUS_EWARN                         (0x1UL << 6)                     /**< Warning Status */
+#define _CAN_STATUS_EWARN_SHIFT                  6                                /**< Shift value for CAN_EWARN */
+#define _CAN_STATUS_EWARN_MASK                   0x40UL                           /**< Bit mask for CAN_EWARN */
+#define _CAN_STATUS_EWARN_DEFAULT                0x00000000UL                     /**< Mode DEFAULT for CAN_STATUS */
+#define CAN_STATUS_EWARN_DEFAULT                 (_CAN_STATUS_EWARN_DEFAULT << 6) /**< Shifted mode DEFAULT for CAN_STATUS */
+#define CAN_STATUS_BOFF                          (0x1UL << 7)                     /**< Bus Off Status */
+#define _CAN_STATUS_BOFF_SHIFT                   7                                /**< Shift value for CAN_BOFF */
+#define _CAN_STATUS_BOFF_MASK                    0x80UL                           /**< Bit mask for CAN_BOFF */
+#define _CAN_STATUS_BOFF_DEFAULT                 0x00000000UL                     /**< Mode DEFAULT for CAN_STATUS */
+#define CAN_STATUS_BOFF_DEFAULT                  (_CAN_STATUS_BOFF_DEFAULT << 7)  /**< Shifted mode DEFAULT for CAN_STATUS */
+
+/* Bit fields for CAN ERRCNT */
+#define _CAN_ERRCNT_RESETVALUE                   0x00000000UL                        /**< Default value for CAN_ERRCNT */
+#define _CAN_ERRCNT_MASK                         0x0000FFFFUL                        /**< Mask for CAN_ERRCNT */
+#define _CAN_ERRCNT_TEC_SHIFT                    0                                   /**< Shift value for CAN_TEC */
+#define _CAN_ERRCNT_TEC_MASK                     0xFFUL                              /**< Bit mask for CAN_TEC */
+#define _CAN_ERRCNT_TEC_DEFAULT                  0x00000000UL                        /**< Mode DEFAULT for CAN_ERRCNT */
+#define CAN_ERRCNT_TEC_DEFAULT                   (_CAN_ERRCNT_TEC_DEFAULT << 0)      /**< Shifted mode DEFAULT for CAN_ERRCNT */
+#define _CAN_ERRCNT_REC_SHIFT                    8                                   /**< Shift value for CAN_REC */
+#define _CAN_ERRCNT_REC_MASK                     0x7F00UL                            /**< Bit mask for CAN_REC */
+#define _CAN_ERRCNT_REC_DEFAULT                  0x00000000UL                        /**< Mode DEFAULT for CAN_ERRCNT */
+#define CAN_ERRCNT_REC_DEFAULT                   (_CAN_ERRCNT_REC_DEFAULT << 8)      /**< Shifted mode DEFAULT for CAN_ERRCNT */
+#define CAN_ERRCNT_RECERRP                       (0x1UL << 15)                       /**< Receive Error Passive */
+#define _CAN_ERRCNT_RECERRP_SHIFT                15                                  /**< Shift value for CAN_RECERRP */
+#define _CAN_ERRCNT_RECERRP_MASK                 0x8000UL                            /**< Bit mask for CAN_RECERRP */
+#define _CAN_ERRCNT_RECERRP_DEFAULT              0x00000000UL                        /**< Mode DEFAULT for CAN_ERRCNT */
+#define _CAN_ERRCNT_RECERRP_FALSE                0x00000000UL                        /**< Mode FALSE for CAN_ERRCNT */
+#define _CAN_ERRCNT_RECERRP_TRUE                 0x00000001UL                        /**< Mode TRUE for CAN_ERRCNT */
+#define CAN_ERRCNT_RECERRP_DEFAULT               (_CAN_ERRCNT_RECERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for CAN_ERRCNT */
+#define CAN_ERRCNT_RECERRP_FALSE                 (_CAN_ERRCNT_RECERRP_FALSE << 15)   /**< Shifted mode FALSE for CAN_ERRCNT */
+#define CAN_ERRCNT_RECERRP_TRUE                  (_CAN_ERRCNT_RECERRP_TRUE << 15)    /**< Shifted mode TRUE for CAN_ERRCNT */
+
+/* Bit fields for CAN BITTIMING */
+#define _CAN_BITTIMING_RESETVALUE                0x00002301UL                         /**< Default value for CAN_BITTIMING */
+#define _CAN_BITTIMING_MASK                      0x00007FFFUL                         /**< Mask for CAN_BITTIMING */
+#define _CAN_BITTIMING_BRP_SHIFT                 0                                    /**< Shift value for CAN_BRP */
+#define _CAN_BITTIMING_BRP_MASK                  0x3FUL                               /**< Bit mask for CAN_BRP */
+#define _CAN_BITTIMING_BRP_DEFAULT               0x00000001UL                         /**< Mode DEFAULT for CAN_BITTIMING */
+#define CAN_BITTIMING_BRP_DEFAULT                (_CAN_BITTIMING_BRP_DEFAULT << 0)    /**< Shifted mode DEFAULT for CAN_BITTIMING */
+#define _CAN_BITTIMING_SJW_SHIFT                 6                                    /**< Shift value for CAN_SJW */
+#define _CAN_BITTIMING_SJW_MASK                  0xC0UL                               /**< Bit mask for CAN_SJW */
+#define _CAN_BITTIMING_SJW_DEFAULT               0x00000000UL                         /**< Mode DEFAULT for CAN_BITTIMING */
+#define CAN_BITTIMING_SJW_DEFAULT                (_CAN_BITTIMING_SJW_DEFAULT << 6)    /**< Shifted mode DEFAULT for CAN_BITTIMING */
+#define _CAN_BITTIMING_TSEG1_SHIFT               8                                    /**< Shift value for CAN_TSEG1 */
+#define _CAN_BITTIMING_TSEG1_MASK                0xF00UL                              /**< Bit mask for CAN_TSEG1 */
+#define _CAN_BITTIMING_TSEG1_DEFAULT             0x00000003UL                         /**< Mode DEFAULT for CAN_BITTIMING */
+#define CAN_BITTIMING_TSEG1_DEFAULT              (_CAN_BITTIMING_TSEG1_DEFAULT << 8)  /**< Shifted mode DEFAULT for CAN_BITTIMING */
+#define _CAN_BITTIMING_TSEG2_SHIFT               12                                   /**< Shift value for CAN_TSEG2 */
+#define _CAN_BITTIMING_TSEG2_MASK                0x7000UL                             /**< Bit mask for CAN_TSEG2 */
+#define _CAN_BITTIMING_TSEG2_DEFAULT             0x00000002UL                         /**< Mode DEFAULT for CAN_BITTIMING */
+#define CAN_BITTIMING_TSEG2_DEFAULT              (_CAN_BITTIMING_TSEG2_DEFAULT << 12) /**< Shifted mode DEFAULT for CAN_BITTIMING */
+
+/* Bit fields for CAN INTID */
+#define _CAN_INTID_RESETVALUE                    0x00000000UL                       /**< Default value for CAN_INTID */
+#define _CAN_INTID_MASK                          0x0000803FUL                       /**< Mask for CAN_INTID */
+#define _CAN_INTID_INTID_SHIFT                   0                                  /**< Shift value for CAN_INTID */
+#define _CAN_INTID_INTID_MASK                    0x3FUL                             /**< Bit mask for CAN_INTID */
+#define _CAN_INTID_INTID_DEFAULT                 0x00000000UL                       /**< Mode DEFAULT for CAN_INTID */
+#define CAN_INTID_INTID_DEFAULT                  (_CAN_INTID_INTID_DEFAULT << 0)    /**< Shifted mode DEFAULT for CAN_INTID */
+#define CAN_INTID_INTSTAT                        (0x1UL << 15)                      /**< Status Interupt */
+#define _CAN_INTID_INTSTAT_SHIFT                 15                                 /**< Shift value for CAN_INTSTAT */
+#define _CAN_INTID_INTSTAT_MASK                  0x8000UL                           /**< Bit mask for CAN_INTSTAT */
+#define _CAN_INTID_INTSTAT_DEFAULT               0x00000000UL                       /**< Mode DEFAULT for CAN_INTID */
+#define _CAN_INTID_INTSTAT_FALSE                 0x00000000UL                       /**< Mode FALSE for CAN_INTID */
+#define _CAN_INTID_INTSTAT_TRUE                  0x00000001UL                       /**< Mode TRUE for CAN_INTID */
+#define CAN_INTID_INTSTAT_DEFAULT                (_CAN_INTID_INTSTAT_DEFAULT << 15) /**< Shifted mode DEFAULT for CAN_INTID */
+#define CAN_INTID_INTSTAT_FALSE                  (_CAN_INTID_INTSTAT_FALSE << 15)   /**< Shifted mode FALSE for CAN_INTID */
+#define CAN_INTID_INTSTAT_TRUE                   (_CAN_INTID_INTSTAT_TRUE << 15)    /**< Shifted mode TRUE for CAN_INTID */
+
+/* Bit fields for CAN TEST */
+#define _CAN_TEST_RESETVALUE                     0x00000000UL                    /**< Default value for CAN_TEST */
+#define _CAN_TEST_MASK                           0x000000FCUL                    /**< Mask for CAN_TEST */
+#define CAN_TEST_BASIC                           (0x1UL << 2)                    /**< Basic Mode */
+#define _CAN_TEST_BASIC_SHIFT                    2                               /**< Shift value for CAN_BASIC */
+#define _CAN_TEST_BASIC_MASK                     0x4UL                           /**< Bit mask for CAN_BASIC */
+#define _CAN_TEST_BASIC_DEFAULT                  0x00000000UL                    /**< Mode DEFAULT for CAN_TEST */
+#define CAN_TEST_BASIC_DEFAULT                   (_CAN_TEST_BASIC_DEFAULT << 2)  /**< Shifted mode DEFAULT for CAN_TEST */
+#define CAN_TEST_SILENT                          (0x1UL << 3)                    /**< Silent Mode */
+#define _CAN_TEST_SILENT_SHIFT                   3                               /**< Shift value for CAN_SILENT */
+#define _CAN_TEST_SILENT_MASK                    0x8UL                           /**< Bit mask for CAN_SILENT */
+#define _CAN_TEST_SILENT_DEFAULT                 0x00000000UL                    /**< Mode DEFAULT for CAN_TEST */
+#define CAN_TEST_SILENT_DEFAULT                  (_CAN_TEST_SILENT_DEFAULT << 3) /**< Shifted mode DEFAULT for CAN_TEST */
+#define CAN_TEST_LBACK                           (0x1UL << 4)                    /**< Loopback Mode */
+#define _CAN_TEST_LBACK_SHIFT                    4                               /**< Shift value for CAN_LBACK */
+#define _CAN_TEST_LBACK_MASK                     0x10UL                          /**< Bit mask for CAN_LBACK */
+#define _CAN_TEST_LBACK_DEFAULT                  0x00000000UL                    /**< Mode DEFAULT for CAN_TEST */
+#define CAN_TEST_LBACK_DEFAULT                   (_CAN_TEST_LBACK_DEFAULT << 4)  /**< Shifted mode DEFAULT for CAN_TEST */
+#define _CAN_TEST_TX_SHIFT                       5                               /**< Shift value for CAN_TX */
+#define _CAN_TEST_TX_MASK                        0x60UL                          /**< Bit mask for CAN_TX */
+#define _CAN_TEST_TX_DEFAULT                     0x00000000UL                    /**< Mode DEFAULT for CAN_TEST */
+#define _CAN_TEST_TX_CORE                        0x00000000UL                    /**< Mode CORE for CAN_TEST */
+#define _CAN_TEST_TX_SAMPT                       0x00000001UL                    /**< Mode SAMPT for CAN_TEST */
+#define _CAN_TEST_TX_LOW                         0x00000002UL                    /**< Mode LOW for CAN_TEST */
+#define _CAN_TEST_TX_HIGH                        0x00000003UL                    /**< Mode HIGH for CAN_TEST */
+#define CAN_TEST_TX_DEFAULT                      (_CAN_TEST_TX_DEFAULT << 5)     /**< Shifted mode DEFAULT for CAN_TEST */
+#define CAN_TEST_TX_CORE                         (_CAN_TEST_TX_CORE << 5)        /**< Shifted mode CORE for CAN_TEST */
+#define CAN_TEST_TX_SAMPT                        (_CAN_TEST_TX_SAMPT << 5)       /**< Shifted mode SAMPT for CAN_TEST */
+#define CAN_TEST_TX_LOW                          (_CAN_TEST_TX_LOW << 5)         /**< Shifted mode LOW for CAN_TEST */
+#define CAN_TEST_TX_HIGH                         (_CAN_TEST_TX_HIGH << 5)        /**< Shifted mode HIGH for CAN_TEST */
+#define CAN_TEST_RX                              (0x1UL << 7)                    /**< Monitors the Actual Value of CAN_RX Pin */
+#define _CAN_TEST_RX_SHIFT                       7                               /**< Shift value for CAN_RX */
+#define _CAN_TEST_RX_MASK                        0x80UL                          /**< Bit mask for CAN_RX */
+#define _CAN_TEST_RX_DEFAULT                     0x00000000UL                    /**< Mode DEFAULT for CAN_TEST */
+#define _CAN_TEST_RX_LOW                         0x00000000UL                    /**< Mode LOW for CAN_TEST */
+#define _CAN_TEST_RX_HIGH                        0x00000001UL                    /**< Mode HIGH for CAN_TEST */
+#define CAN_TEST_RX_DEFAULT                      (_CAN_TEST_RX_DEFAULT << 7)     /**< Shifted mode DEFAULT for CAN_TEST */
+#define CAN_TEST_RX_LOW                          (_CAN_TEST_RX_LOW << 7)         /**< Shifted mode LOW for CAN_TEST */
+#define CAN_TEST_RX_HIGH                         (_CAN_TEST_RX_HIGH << 7)        /**< Shifted mode HIGH for CAN_TEST */
+
+/* Bit fields for CAN BRPE */
+#define _CAN_BRPE_RESETVALUE                     0x00000000UL                  /**< Default value for CAN_BRPE */
+#define _CAN_BRPE_MASK                           0x0000000FUL                  /**< Mask for CAN_BRPE */
+#define _CAN_BRPE_BRPE_SHIFT                     0                             /**< Shift value for CAN_BRPE */
+#define _CAN_BRPE_BRPE_MASK                      0xFUL                         /**< Bit mask for CAN_BRPE */
+#define _CAN_BRPE_BRPE_DEFAULT                   0x00000000UL                  /**< Mode DEFAULT for CAN_BRPE */
+#define CAN_BRPE_BRPE_DEFAULT                    (_CAN_BRPE_BRPE_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_BRPE */
+
+/* Bit fields for CAN TRANSREQ */
+#define _CAN_TRANSREQ_RESETVALUE                 0x00000000UL                           /**< Default value for CAN_TRANSREQ */
+#define _CAN_TRANSREQ_MASK                       0xFFFFFFFFUL                           /**< Mask for CAN_TRANSREQ */
+#define _CAN_TRANSREQ_TXRQSTOUT_SHIFT            0                                      /**< Shift value for CAN_TXRQSTOUT */
+#define _CAN_TRANSREQ_TXRQSTOUT_MASK             0xFFFFFFFFUL                           /**< Bit mask for CAN_TXRQSTOUT */
+#define _CAN_TRANSREQ_TXRQSTOUT_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for CAN_TRANSREQ */
+#define _CAN_TRANSREQ_TXRQSTOUT_FALSE            0x00000000UL                           /**< Mode FALSE for CAN_TRANSREQ */
+#define _CAN_TRANSREQ_TXRQSTOUT_TRUE             0x00000001UL                           /**< Mode TRUE for CAN_TRANSREQ */
+#define CAN_TRANSREQ_TXRQSTOUT_DEFAULT           (_CAN_TRANSREQ_TXRQSTOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_TRANSREQ */
+#define CAN_TRANSREQ_TXRQSTOUT_FALSE             (_CAN_TRANSREQ_TXRQSTOUT_FALSE << 0)   /**< Shifted mode FALSE for CAN_TRANSREQ */
+#define CAN_TRANSREQ_TXRQSTOUT_TRUE              (_CAN_TRANSREQ_TXRQSTOUT_TRUE << 0)    /**< Shifted mode TRUE for CAN_TRANSREQ */
+
+/* Bit fields for CAN MESSAGEDATA */
+#define _CAN_MESSAGEDATA_RESETVALUE              0x00000000UL                          /**< Default value for CAN_MESSAGEDATA */
+#define _CAN_MESSAGEDATA_MASK                    0xFFFFFFFFUL                          /**< Mask for CAN_MESSAGEDATA */
+#define _CAN_MESSAGEDATA_VALID_SHIFT             0                                     /**< Shift value for CAN_VALID */
+#define _CAN_MESSAGEDATA_VALID_MASK              0xFFFFFFFFUL                          /**< Bit mask for CAN_VALID */
+#define _CAN_MESSAGEDATA_VALID_DEFAULT           0x00000000UL                          /**< Mode DEFAULT for CAN_MESSAGEDATA */
+#define CAN_MESSAGEDATA_VALID_DEFAULT            (_CAN_MESSAGEDATA_VALID_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MESSAGEDATA */
+
+/* Bit fields for CAN MESSAGESTATE */
+#define _CAN_MESSAGESTATE_RESETVALUE             0x00000000UL                           /**< Default value for CAN_MESSAGESTATE */
+#define _CAN_MESSAGESTATE_MASK                   0xFFFFFFFFUL                           /**< Mask for CAN_MESSAGESTATE */
+#define _CAN_MESSAGESTATE_VALID_SHIFT            0                                      /**< Shift value for CAN_VALID */
+#define _CAN_MESSAGESTATE_VALID_MASK             0xFFFFFFFFUL                           /**< Bit mask for CAN_VALID */
+#define _CAN_MESSAGESTATE_VALID_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for CAN_MESSAGESTATE */
+#define CAN_MESSAGESTATE_VALID_DEFAULT           (_CAN_MESSAGESTATE_VALID_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MESSAGESTATE */
+
+/* Bit fields for CAN CONFIG */
+#define _CAN_CONFIG_RESETVALUE                   0x00000000UL                        /**< Default value for CAN_CONFIG */
+#define _CAN_CONFIG_MASK                         0x00008000UL                        /**< Mask for CAN_CONFIG */
+#define CAN_CONFIG_DBGHALT                       (0x1UL << 15)                       /**< Debug Halt */
+#define _CAN_CONFIG_DBGHALT_SHIFT                15                                  /**< Shift value for CAN_DBGHALT */
+#define _CAN_CONFIG_DBGHALT_MASK                 0x8000UL                            /**< Bit mask for CAN_DBGHALT */
+#define _CAN_CONFIG_DBGHALT_DEFAULT              0x00000000UL                        /**< Mode DEFAULT for CAN_CONFIG */
+#define _CAN_CONFIG_DBGHALT_NORMAL               0x00000000UL                        /**< Mode NORMAL for CAN_CONFIG */
+#define _CAN_CONFIG_DBGHALT_STALL                0x00000001UL                        /**< Mode STALL for CAN_CONFIG */
+#define CAN_CONFIG_DBGHALT_DEFAULT               (_CAN_CONFIG_DBGHALT_DEFAULT << 15) /**< Shifted mode DEFAULT for CAN_CONFIG */
+#define CAN_CONFIG_DBGHALT_NORMAL                (_CAN_CONFIG_DBGHALT_NORMAL << 15)  /**< Shifted mode NORMAL for CAN_CONFIG */
+#define CAN_CONFIG_DBGHALT_STALL                 (_CAN_CONFIG_DBGHALT_STALL << 15)   /**< Shifted mode STALL for CAN_CONFIG */
+
+/* Bit fields for CAN IF0IF */
+#define _CAN_IF0IF_RESETVALUE                    0x00000000UL                      /**< Default value for CAN_IF0IF */
+#define _CAN_IF0IF_MASK                          0xFFFFFFFFUL                      /**< Mask for CAN_IF0IF */
+#define _CAN_IF0IF_MESSAGE_SHIFT                 0                                 /**< Shift value for CAN_MESSAGE */
+#define _CAN_IF0IF_MESSAGE_MASK                  0xFFFFFFFFUL                      /**< Bit mask for CAN_MESSAGE */
+#define _CAN_IF0IF_MESSAGE_DEFAULT               0x00000000UL                      /**< Mode DEFAULT for CAN_IF0IF */
+#define CAN_IF0IF_MESSAGE_DEFAULT                (_CAN_IF0IF_MESSAGE_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF0IF */
+
+/* Bit fields for CAN IF0IFS */
+#define _CAN_IF0IFS_RESETVALUE                   0x00000000UL                       /**< Default value for CAN_IF0IFS */
+#define _CAN_IF0IFS_MASK                         0xFFFFFFFFUL                       /**< Mask for CAN_IF0IFS */
+#define _CAN_IF0IFS_MESSAGE_SHIFT                0                                  /**< Shift value for CAN_MESSAGE */
+#define _CAN_IF0IFS_MESSAGE_MASK                 0xFFFFFFFFUL                       /**< Bit mask for CAN_MESSAGE */
+#define _CAN_IF0IFS_MESSAGE_DEFAULT              0x00000000UL                       /**< Mode DEFAULT for CAN_IF0IFS */
+#define CAN_IF0IFS_MESSAGE_DEFAULT               (_CAN_IF0IFS_MESSAGE_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF0IFS */
+
+/* Bit fields for CAN IF0IFC */
+#define _CAN_IF0IFC_RESETVALUE                   0x00000000UL                       /**< Default value for CAN_IF0IFC */
+#define _CAN_IF0IFC_MASK                         0xFFFFFFFFUL                       /**< Mask for CAN_IF0IFC */
+#define _CAN_IF0IFC_MESSAGE_SHIFT                0                                  /**< Shift value for CAN_MESSAGE */
+#define _CAN_IF0IFC_MESSAGE_MASK                 0xFFFFFFFFUL                       /**< Bit mask for CAN_MESSAGE */
+#define _CAN_IF0IFC_MESSAGE_DEFAULT              0x00000000UL                       /**< Mode DEFAULT for CAN_IF0IFC */
+#define CAN_IF0IFC_MESSAGE_DEFAULT               (_CAN_IF0IFC_MESSAGE_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF0IFC */
+
+/* Bit fields for CAN IF0IEN */
+#define _CAN_IF0IEN_RESETVALUE                   0xFFFFFFFFUL                       /**< Default value for CAN_IF0IEN */
+#define _CAN_IF0IEN_MASK                         0xFFFFFFFFUL                       /**< Mask for CAN_IF0IEN */
+#define _CAN_IF0IEN_MESSAGE_SHIFT                0                                  /**< Shift value for CAN_MESSAGE */
+#define _CAN_IF0IEN_MESSAGE_MASK                 0xFFFFFFFFUL                       /**< Bit mask for CAN_MESSAGE */
+#define _CAN_IF0IEN_MESSAGE_DEFAULT              0xFFFFFFFFUL                       /**< Mode DEFAULT for CAN_IF0IEN */
+#define CAN_IF0IEN_MESSAGE_DEFAULT               (_CAN_IF0IEN_MESSAGE_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF0IEN */
+
+/* Bit fields for CAN IF1IF */
+#define _CAN_IF1IF_RESETVALUE                    0x00000000UL                     /**< Default value for CAN_IF1IF */
+#define _CAN_IF1IF_MASK                          0x00000001UL                     /**< Mask for CAN_IF1IF */
+#define CAN_IF1IF_STATUS                         (0x1UL << 0)                     /**< Status Interrupt Flag */
+#define _CAN_IF1IF_STATUS_SHIFT                  0                                /**< Shift value for CAN_STATUS */
+#define _CAN_IF1IF_STATUS_MASK                   0x1UL                            /**< Bit mask for CAN_STATUS */
+#define _CAN_IF1IF_STATUS_DEFAULT                0x00000000UL                     /**< Mode DEFAULT for CAN_IF1IF */
+#define CAN_IF1IF_STATUS_DEFAULT                 (_CAN_IF1IF_STATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF1IF */
+
+/* Bit fields for CAN IF1IFS */
+#define _CAN_IF1IFS_RESETVALUE                   0x00000000UL                      /**< Default value for CAN_IF1IFS */
+#define _CAN_IF1IFS_MASK                         0x00000001UL                      /**< Mask for CAN_IF1IFS */
+#define CAN_IF1IFS_STATUS                        (0x1UL << 0)                      /**< Set STATUS Interrupt Flag */
+#define _CAN_IF1IFS_STATUS_SHIFT                 0                                 /**< Shift value for CAN_STATUS */
+#define _CAN_IF1IFS_STATUS_MASK                  0x1UL                             /**< Bit mask for CAN_STATUS */
+#define _CAN_IF1IFS_STATUS_DEFAULT               0x00000000UL                      /**< Mode DEFAULT for CAN_IF1IFS */
+#define CAN_IF1IFS_STATUS_DEFAULT                (_CAN_IF1IFS_STATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF1IFS */
+
+/* Bit fields for CAN IF1IFC */
+#define _CAN_IF1IFC_RESETVALUE                   0x00000000UL                      /**< Default value for CAN_IF1IFC */
+#define _CAN_IF1IFC_MASK                         0x00000001UL                      /**< Mask for CAN_IF1IFC */
+#define CAN_IF1IFC_STATUS                        (0x1UL << 0)                      /**< Clear STATUS Interrupt Flag */
+#define _CAN_IF1IFC_STATUS_SHIFT                 0                                 /**< Shift value for CAN_STATUS */
+#define _CAN_IF1IFC_STATUS_MASK                  0x1UL                             /**< Bit mask for CAN_STATUS */
+#define _CAN_IF1IFC_STATUS_DEFAULT               0x00000000UL                      /**< Mode DEFAULT for CAN_IF1IFC */
+#define CAN_IF1IFC_STATUS_DEFAULT                (_CAN_IF1IFC_STATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF1IFC */
+
+/* Bit fields for CAN IF1IEN */
+#define _CAN_IF1IEN_RESETVALUE                   0x00000001UL                      /**< Default value for CAN_IF1IEN */
+#define _CAN_IF1IEN_MASK                         0x00000001UL                      /**< Mask for CAN_IF1IEN */
+#define CAN_IF1IEN_STATUS                        (0x1UL << 0)                      /**< STATUS Interrupt Enable */
+#define _CAN_IF1IEN_STATUS_SHIFT                 0                                 /**< Shift value for CAN_STATUS */
+#define _CAN_IF1IEN_STATUS_MASK                  0x1UL                             /**< Bit mask for CAN_STATUS */
+#define _CAN_IF1IEN_STATUS_DEFAULT               0x00000001UL                      /**< Mode DEFAULT for CAN_IF1IEN */
+#define CAN_IF1IEN_STATUS_DEFAULT                (_CAN_IF1IEN_STATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF1IEN */
+
+/* Bit fields for CAN ROUTE */
+#define _CAN_ROUTE_RESETVALUE                    0x00000000UL                    /**< Default value for CAN_ROUTE */
+#define _CAN_ROUTE_MASK                          0x0000071DUL                    /**< Mask for CAN_ROUTE */
+#define CAN_ROUTE_TXPEN                          (0x1UL << 0)                    /**< TX Pin Enable */
+#define _CAN_ROUTE_TXPEN_SHIFT                   0                               /**< Shift value for CAN_TXPEN */
+#define _CAN_ROUTE_TXPEN_MASK                    0x1UL                           /**< Bit mask for CAN_TXPEN */
+#define _CAN_ROUTE_TXPEN_DEFAULT                 0x00000000UL                    /**< Mode DEFAULT for CAN_ROUTE */
+#define CAN_ROUTE_TXPEN_DEFAULT                  (_CAN_ROUTE_TXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_ROUTE */
+#define _CAN_ROUTE_RXLOC_SHIFT                   2                               /**< Shift value for CAN_RXLOC */
+#define _CAN_ROUTE_RXLOC_MASK                    0x1CUL                          /**< Bit mask for CAN_RXLOC */
+#define _CAN_ROUTE_RXLOC_LOC0                    0x00000000UL                    /**< Mode LOC0 for CAN_ROUTE */
+#define _CAN_ROUTE_RXLOC_DEFAULT                 0x00000000UL                    /**< Mode DEFAULT for CAN_ROUTE */
+#define _CAN_ROUTE_RXLOC_LOC1                    0x00000001UL                    /**< Mode LOC1 for CAN_ROUTE */
+#define _CAN_ROUTE_RXLOC_LOC2                    0x00000002UL                    /**< Mode LOC2 for CAN_ROUTE */
+#define _CAN_ROUTE_RXLOC_LOC3                    0x00000003UL                    /**< Mode LOC3 for CAN_ROUTE */
+#define _CAN_ROUTE_RXLOC_LOC4                    0x00000004UL                    /**< Mode LOC4 for CAN_ROUTE */
+#define _CAN_ROUTE_RXLOC_LOC5                    0x00000005UL                    /**< Mode LOC5 for CAN_ROUTE */
+#define _CAN_ROUTE_RXLOC_LOC6                    0x00000006UL                    /**< Mode LOC6 for CAN_ROUTE */
+#define CAN_ROUTE_RXLOC_LOC0                     (_CAN_ROUTE_RXLOC_LOC0 << 2)    /**< Shifted mode LOC0 for CAN_ROUTE */
+#define CAN_ROUTE_RXLOC_DEFAULT                  (_CAN_ROUTE_RXLOC_DEFAULT << 2) /**< Shifted mode DEFAULT for CAN_ROUTE */
+#define CAN_ROUTE_RXLOC_LOC1                     (_CAN_ROUTE_RXLOC_LOC1 << 2)    /**< Shifted mode LOC1 for CAN_ROUTE */
+#define CAN_ROUTE_RXLOC_LOC2                     (_CAN_ROUTE_RXLOC_LOC2 << 2)    /**< Shifted mode LOC2 for CAN_ROUTE */
+#define CAN_ROUTE_RXLOC_LOC3                     (_CAN_ROUTE_RXLOC_LOC3 << 2)    /**< Shifted mode LOC3 for CAN_ROUTE */
+#define CAN_ROUTE_RXLOC_LOC4                     (_CAN_ROUTE_RXLOC_LOC4 << 2)    /**< Shifted mode LOC4 for CAN_ROUTE */
+#define CAN_ROUTE_RXLOC_LOC5                     (_CAN_ROUTE_RXLOC_LOC5 << 2)    /**< Shifted mode LOC5 for CAN_ROUTE */
+#define CAN_ROUTE_RXLOC_LOC6                     (_CAN_ROUTE_RXLOC_LOC6 << 2)    /**< Shifted mode LOC6 for CAN_ROUTE */
+#define _CAN_ROUTE_TXLOC_SHIFT                   8                               /**< Shift value for CAN_TXLOC */
+#define _CAN_ROUTE_TXLOC_MASK                    0x700UL                         /**< Bit mask for CAN_TXLOC */
+#define _CAN_ROUTE_TXLOC_LOC0                    0x00000000UL                    /**< Mode LOC0 for CAN_ROUTE */
+#define _CAN_ROUTE_TXLOC_DEFAULT                 0x00000000UL                    /**< Mode DEFAULT for CAN_ROUTE */
+#define _CAN_ROUTE_TXLOC_LOC1                    0x00000001UL                    /**< Mode LOC1 for CAN_ROUTE */
+#define _CAN_ROUTE_TXLOC_LOC2                    0x00000002UL                    /**< Mode LOC2 for CAN_ROUTE */
+#define _CAN_ROUTE_TXLOC_LOC3                    0x00000003UL                    /**< Mode LOC3 for CAN_ROUTE */
+#define _CAN_ROUTE_TXLOC_LOC4                    0x00000004UL                    /**< Mode LOC4 for CAN_ROUTE */
+#define _CAN_ROUTE_TXLOC_LOC5                    0x00000005UL                    /**< Mode LOC5 for CAN_ROUTE */
+#define _CAN_ROUTE_TXLOC_LOC6                    0x00000006UL                    /**< Mode LOC6 for CAN_ROUTE */
+#define CAN_ROUTE_TXLOC_LOC0                     (_CAN_ROUTE_TXLOC_LOC0 << 8)    /**< Shifted mode LOC0 for CAN_ROUTE */
+#define CAN_ROUTE_TXLOC_DEFAULT                  (_CAN_ROUTE_TXLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CAN_ROUTE */
+#define CAN_ROUTE_TXLOC_LOC1                     (_CAN_ROUTE_TXLOC_LOC1 << 8)    /**< Shifted mode LOC1 for CAN_ROUTE */
+#define CAN_ROUTE_TXLOC_LOC2                     (_CAN_ROUTE_TXLOC_LOC2 << 8)    /**< Shifted mode LOC2 for CAN_ROUTE */
+#define CAN_ROUTE_TXLOC_LOC3                     (_CAN_ROUTE_TXLOC_LOC3 << 8)    /**< Shifted mode LOC3 for CAN_ROUTE */
+#define CAN_ROUTE_TXLOC_LOC4                     (_CAN_ROUTE_TXLOC_LOC4 << 8)    /**< Shifted mode LOC4 for CAN_ROUTE */
+#define CAN_ROUTE_TXLOC_LOC5                     (_CAN_ROUTE_TXLOC_LOC5 << 8)    /**< Shifted mode LOC5 for CAN_ROUTE */
+#define CAN_ROUTE_TXLOC_LOC6                     (_CAN_ROUTE_TXLOC_LOC6 << 8)    /**< Shifted mode LOC6 for CAN_ROUTE */
+
+/* Bit fields for CAN MIR_CMDMASK */
+#define _CAN_MIR_CMDMASK_RESETVALUE              0x00000000UL                                 /**< Default value for CAN_MIR_CMDMASK */
+#define _CAN_MIR_CMDMASK_MASK                    0x000000FFUL                                 /**< Mask for CAN_MIR_CMDMASK */
+#define CAN_MIR_CMDMASK_DATAB                    (0x1UL << 0)                                 /**< CC Channel Mode */
+#define _CAN_MIR_CMDMASK_DATAB_SHIFT             0                                            /**< Shift value for CAN_DATAB */
+#define _CAN_MIR_CMDMASK_DATAB_MASK              0x1UL                                        /**< Bit mask for CAN_DATAB */
+#define _CAN_MIR_CMDMASK_DATAB_DEFAULT           0x00000000UL                                 /**< Mode DEFAULT for CAN_MIR_CMDMASK */
+#define CAN_MIR_CMDMASK_DATAB_DEFAULT            (_CAN_MIR_CMDMASK_DATAB_DEFAULT << 0)        /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */
+#define CAN_MIR_CMDMASK_DATAA                    (0x1UL << 1)                                 /**< Access Data Bytes 0-3 */
+#define _CAN_MIR_CMDMASK_DATAA_SHIFT             1                                            /**< Shift value for CAN_DATAA */
+#define _CAN_MIR_CMDMASK_DATAA_MASK              0x2UL                                        /**< Bit mask for CAN_DATAA */
+#define _CAN_MIR_CMDMASK_DATAA_DEFAULT           0x00000000UL                                 /**< Mode DEFAULT for CAN_MIR_CMDMASK */
+#define CAN_MIR_CMDMASK_DATAA_DEFAULT            (_CAN_MIR_CMDMASK_DATAA_DEFAULT << 1)        /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */
+#define CAN_MIR_CMDMASK_TXRQSTNEWDAT             (0x1UL << 2)                                 /**< Transmission Request Bit/ New Data Bit */
+#define _CAN_MIR_CMDMASK_TXRQSTNEWDAT_SHIFT      2                                            /**< Shift value for CAN_TXRQSTNEWDAT */
+#define _CAN_MIR_CMDMASK_TXRQSTNEWDAT_MASK       0x4UL                                        /**< Bit mask for CAN_TXRQSTNEWDAT */
+#define _CAN_MIR_CMDMASK_TXRQSTNEWDAT_DEFAULT    0x00000000UL                                 /**< Mode DEFAULT for CAN_MIR_CMDMASK */
+#define CAN_MIR_CMDMASK_TXRQSTNEWDAT_DEFAULT     (_CAN_MIR_CMDMASK_TXRQSTNEWDAT_DEFAULT << 2) /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */
+#define CAN_MIR_CMDMASK_CLRINTPND                (0x1UL << 3)                                 /**< Clear Interrupt Pending Bit */
+#define _CAN_MIR_CMDMASK_CLRINTPND_SHIFT         3                                            /**< Shift value for CAN_CLRINTPND */
+#define _CAN_MIR_CMDMASK_CLRINTPND_MASK          0x8UL                                        /**< Bit mask for CAN_CLRINTPND */
+#define _CAN_MIR_CMDMASK_CLRINTPND_DEFAULT       0x00000000UL                                 /**< Mode DEFAULT for CAN_MIR_CMDMASK */
+#define CAN_MIR_CMDMASK_CLRINTPND_DEFAULT        (_CAN_MIR_CMDMASK_CLRINTPND_DEFAULT << 3)    /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */
+#define CAN_MIR_CMDMASK_CONTROL                  (0x1UL << 4)                                 /**< Access Control Bits */
+#define _CAN_MIR_CMDMASK_CONTROL_SHIFT           4                                            /**< Shift value for CAN_CONTROL */
+#define _CAN_MIR_CMDMASK_CONTROL_MASK            0x10UL                                       /**< Bit mask for CAN_CONTROL */
+#define _CAN_MIR_CMDMASK_CONTROL_DEFAULT         0x00000000UL                                 /**< Mode DEFAULT for CAN_MIR_CMDMASK */
+#define CAN_MIR_CMDMASK_CONTROL_DEFAULT          (_CAN_MIR_CMDMASK_CONTROL_DEFAULT << 4)      /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */
+#define CAN_MIR_CMDMASK_ARBACC                   (0x1UL << 5)                                 /**< Access Arbitration Bits */
+#define _CAN_MIR_CMDMASK_ARBACC_SHIFT            5                                            /**< Shift value for CAN_ARBACC */
+#define _CAN_MIR_CMDMASK_ARBACC_MASK             0x20UL                                       /**< Bit mask for CAN_ARBACC */
+#define _CAN_MIR_CMDMASK_ARBACC_DEFAULT          0x00000000UL                                 /**< Mode DEFAULT for CAN_MIR_CMDMASK */
+#define CAN_MIR_CMDMASK_ARBACC_DEFAULT           (_CAN_MIR_CMDMASK_ARBACC_DEFAULT << 5)       /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */
+#define CAN_MIR_CMDMASK_MASKACC                  (0x1UL << 6)                                 /**< Access Mask Bits */
+#define _CAN_MIR_CMDMASK_MASKACC_SHIFT           6                                            /**< Shift value for CAN_MASKACC */
+#define _CAN_MIR_CMDMASK_MASKACC_MASK            0x40UL                                       /**< Bit mask for CAN_MASKACC */
+#define _CAN_MIR_CMDMASK_MASKACC_DEFAULT         0x00000000UL                                 /**< Mode DEFAULT for CAN_MIR_CMDMASK */
+#define CAN_MIR_CMDMASK_MASKACC_DEFAULT          (_CAN_MIR_CMDMASK_MASKACC_DEFAULT << 6)      /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */
+#define CAN_MIR_CMDMASK_WRRD                     (0x1UL << 7)                                 /**< Write/Read RAM */
+#define _CAN_MIR_CMDMASK_WRRD_SHIFT              7                                            /**< Shift value for CAN_WRRD */
+#define _CAN_MIR_CMDMASK_WRRD_MASK               0x80UL                                       /**< Bit mask for CAN_WRRD */
+#define _CAN_MIR_CMDMASK_WRRD_DEFAULT            0x00000000UL                                 /**< Mode DEFAULT for CAN_MIR_CMDMASK */
+#define _CAN_MIR_CMDMASK_WRRD_READ               0x00000000UL                                 /**< Mode READ for CAN_MIR_CMDMASK */
+#define _CAN_MIR_CMDMASK_WRRD_WRITE              0x00000001UL                                 /**< Mode WRITE for CAN_MIR_CMDMASK */
+#define CAN_MIR_CMDMASK_WRRD_DEFAULT             (_CAN_MIR_CMDMASK_WRRD_DEFAULT << 7)         /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */
+#define CAN_MIR_CMDMASK_WRRD_READ                (_CAN_MIR_CMDMASK_WRRD_READ << 7)            /**< Shifted mode READ for CAN_MIR_CMDMASK */
+#define CAN_MIR_CMDMASK_WRRD_WRITE               (_CAN_MIR_CMDMASK_WRRD_WRITE << 7)           /**< Shifted mode WRITE for CAN_MIR_CMDMASK */
+
+/* Bit fields for CAN MIR_MASK */
+#define _CAN_MIR_MASK_RESETVALUE                 0xDFFFFFFFUL                       /**< Default value for CAN_MIR_MASK */
+#define _CAN_MIR_MASK_MASK                       0xDFFFFFFFUL                       /**< Mask for CAN_MIR_MASK */
+#define _CAN_MIR_MASK_MASK_SHIFT                 0                                  /**< Shift value for CAN_MASK */
+#define _CAN_MIR_MASK_MASK_MASK                  0x1FFFFFFFUL                       /**< Bit mask for CAN_MASK */
+#define _CAN_MIR_MASK_MASK_DEFAULT               0x1FFFFFFFUL                       /**< Mode DEFAULT for CAN_MIR_MASK */
+#define CAN_MIR_MASK_MASK_DEFAULT                (_CAN_MIR_MASK_MASK_DEFAULT << 0)  /**< Shifted mode DEFAULT for CAN_MIR_MASK */
+#define CAN_MIR_MASK_MDIR                        (0x1UL << 30)                      /**< Mask Message Direction */
+#define _CAN_MIR_MASK_MDIR_SHIFT                 30                                 /**< Shift value for CAN_MDIR */
+#define _CAN_MIR_MASK_MDIR_MASK                  0x40000000UL                       /**< Bit mask for CAN_MDIR */
+#define _CAN_MIR_MASK_MDIR_DEFAULT               0x00000001UL                       /**< Mode DEFAULT for CAN_MIR_MASK */
+#define CAN_MIR_MASK_MDIR_DEFAULT                (_CAN_MIR_MASK_MDIR_DEFAULT << 30) /**< Shifted mode DEFAULT for CAN_MIR_MASK */
+#define CAN_MIR_MASK_MXTD                        (0x1UL << 31)                      /**< Mask Extended Identifier */
+#define _CAN_MIR_MASK_MXTD_SHIFT                 31                                 /**< Shift value for CAN_MXTD */
+#define _CAN_MIR_MASK_MXTD_MASK                  0x80000000UL                       /**< Bit mask for CAN_MXTD */
+#define _CAN_MIR_MASK_MXTD_DEFAULT               0x00000001UL                       /**< Mode DEFAULT for CAN_MIR_MASK */
+#define CAN_MIR_MASK_MXTD_DEFAULT                (_CAN_MIR_MASK_MXTD_DEFAULT << 31) /**< Shifted mode DEFAULT for CAN_MIR_MASK */
+
+/* Bit fields for CAN MIR_ARB */
+#define _CAN_MIR_ARB_RESETVALUE                  0x00000000UL                        /**< Default value for CAN_MIR_ARB */
+#define _CAN_MIR_ARB_MASK                        0xFFFFFFFFUL                        /**< Mask for CAN_MIR_ARB */
+#define _CAN_MIR_ARB_ID_SHIFT                    0                                   /**< Shift value for CAN_ID */
+#define _CAN_MIR_ARB_ID_MASK                     0x1FFFFFFFUL                        /**< Bit mask for CAN_ID */
+#define _CAN_MIR_ARB_ID_DEFAULT                  0x00000000UL                        /**< Mode DEFAULT for CAN_MIR_ARB */
+#define CAN_MIR_ARB_ID_DEFAULT                   (_CAN_MIR_ARB_ID_DEFAULT << 0)      /**< Shifted mode DEFAULT for CAN_MIR_ARB */
+#define CAN_MIR_ARB_DIR                          (0x1UL << 29)                       /**< Message Direction */
+#define _CAN_MIR_ARB_DIR_SHIFT                   29                                  /**< Shift value for CAN_DIR */
+#define _CAN_MIR_ARB_DIR_MASK                    0x20000000UL                        /**< Bit mask for CAN_DIR */
+#define _CAN_MIR_ARB_DIR_DEFAULT                 0x00000000UL                        /**< Mode DEFAULT for CAN_MIR_ARB */
+#define _CAN_MIR_ARB_DIR_RX                      0x00000000UL                        /**< Mode RX for CAN_MIR_ARB */
+#define _CAN_MIR_ARB_DIR_TX                      0x00000001UL                        /**< Mode TX for CAN_MIR_ARB */
+#define CAN_MIR_ARB_DIR_DEFAULT                  (_CAN_MIR_ARB_DIR_DEFAULT << 29)    /**< Shifted mode DEFAULT for CAN_MIR_ARB */
+#define CAN_MIR_ARB_DIR_RX                       (_CAN_MIR_ARB_DIR_RX << 29)         /**< Shifted mode RX for CAN_MIR_ARB */
+#define CAN_MIR_ARB_DIR_TX                       (_CAN_MIR_ARB_DIR_TX << 29)         /**< Shifted mode TX for CAN_MIR_ARB */
+#define CAN_MIR_ARB_XTD                          (0x1UL << 30)                       /**< Extended Identifier */
+#define _CAN_MIR_ARB_XTD_SHIFT                   30                                  /**< Shift value for CAN_XTD */
+#define _CAN_MIR_ARB_XTD_MASK                    0x40000000UL                        /**< Bit mask for CAN_XTD */
+#define _CAN_MIR_ARB_XTD_DEFAULT                 0x00000000UL                        /**< Mode DEFAULT for CAN_MIR_ARB */
+#define _CAN_MIR_ARB_XTD_STD                     0x00000000UL                        /**< Mode STD for CAN_MIR_ARB */
+#define _CAN_MIR_ARB_XTD_EXT                     0x00000001UL                        /**< Mode EXT for CAN_MIR_ARB */
+#define CAN_MIR_ARB_XTD_DEFAULT                  (_CAN_MIR_ARB_XTD_DEFAULT << 30)    /**< Shifted mode DEFAULT for CAN_MIR_ARB */
+#define CAN_MIR_ARB_XTD_STD                      (_CAN_MIR_ARB_XTD_STD << 30)        /**< Shifted mode STD for CAN_MIR_ARB */
+#define CAN_MIR_ARB_XTD_EXT                      (_CAN_MIR_ARB_XTD_EXT << 30)        /**< Shifted mode EXT for CAN_MIR_ARB */
+#define CAN_MIR_ARB_MSGVAL                       (0x1UL << 31)                       /**< Message Valid */
+#define _CAN_MIR_ARB_MSGVAL_SHIFT                31                                  /**< Shift value for CAN_MSGVAL */
+#define _CAN_MIR_ARB_MSGVAL_MASK                 0x80000000UL                        /**< Bit mask for CAN_MSGVAL */
+#define _CAN_MIR_ARB_MSGVAL_DEFAULT              0x00000000UL                        /**< Mode DEFAULT for CAN_MIR_ARB */
+#define CAN_MIR_ARB_MSGVAL_DEFAULT               (_CAN_MIR_ARB_MSGVAL_DEFAULT << 31) /**< Shifted mode DEFAULT for CAN_MIR_ARB */
+
+/* Bit fields for CAN MIR_CTRL */
+#define _CAN_MIR_CTRL_RESETVALUE                 0x00000000UL                            /**< Default value for CAN_MIR_CTRL */
+#define _CAN_MIR_CTRL_MASK                       0x0000FF8FUL                            /**< Mask for CAN_MIR_CTRL */
+#define _CAN_MIR_CTRL_DLC_SHIFT                  0                                       /**< Shift value for CAN_DLC */
+#define _CAN_MIR_CTRL_DLC_MASK                   0xFUL                                   /**< Bit mask for CAN_DLC */
+#define _CAN_MIR_CTRL_DLC_DEFAULT                0x00000000UL                            /**< Mode DEFAULT for CAN_MIR_CTRL */
+#define CAN_MIR_CTRL_DLC_DEFAULT                 (_CAN_MIR_CTRL_DLC_DEFAULT << 0)        /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
+#define CAN_MIR_CTRL_EOB                         (0x1UL << 7)                            /**< End of Buffer */
+#define _CAN_MIR_CTRL_EOB_SHIFT                  7                                       /**< Shift value for CAN_EOB */
+#define _CAN_MIR_CTRL_EOB_MASK                   0x80UL                                  /**< Bit mask for CAN_EOB */
+#define _CAN_MIR_CTRL_EOB_DEFAULT                0x00000000UL                            /**< Mode DEFAULT for CAN_MIR_CTRL */
+#define CAN_MIR_CTRL_EOB_DEFAULT                 (_CAN_MIR_CTRL_EOB_DEFAULT << 7)        /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
+#define CAN_MIR_CTRL_TXRQST                      (0x1UL << 8)                            /**< Transmit Request */
+#define _CAN_MIR_CTRL_TXRQST_SHIFT               8                                       /**< Shift value for CAN_TXRQST */
+#define _CAN_MIR_CTRL_TXRQST_MASK                0x100UL                                 /**< Bit mask for CAN_TXRQST */
+#define _CAN_MIR_CTRL_TXRQST_DEFAULT             0x00000000UL                            /**< Mode DEFAULT for CAN_MIR_CTRL */
+#define CAN_MIR_CTRL_TXRQST_DEFAULT              (_CAN_MIR_CTRL_TXRQST_DEFAULT << 8)     /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
+#define CAN_MIR_CTRL_RMTEN                       (0x1UL << 9)                            /**< Remote Enable */
+#define _CAN_MIR_CTRL_RMTEN_SHIFT                9                                       /**< Shift value for CAN_RMTEN */
+#define _CAN_MIR_CTRL_RMTEN_MASK                 0x200UL                                 /**< Bit mask for CAN_RMTEN */
+#define _CAN_MIR_CTRL_RMTEN_DEFAULT              0x00000000UL                            /**< Mode DEFAULT for CAN_MIR_CTRL */
+#define CAN_MIR_CTRL_RMTEN_DEFAULT               (_CAN_MIR_CTRL_RMTEN_DEFAULT << 9)      /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
+#define CAN_MIR_CTRL_RXIE                        (0x1UL << 10)                           /**< Receive Interrupt Enable */
+#define _CAN_MIR_CTRL_RXIE_SHIFT                 10                                      /**< Shift value for CAN_RXIE */
+#define _CAN_MIR_CTRL_RXIE_MASK                  0x400UL                                 /**< Bit mask for CAN_RXIE */
+#define _CAN_MIR_CTRL_RXIE_DEFAULT               0x00000000UL                            /**< Mode DEFAULT for CAN_MIR_CTRL */
+#define CAN_MIR_CTRL_RXIE_DEFAULT                (_CAN_MIR_CTRL_RXIE_DEFAULT << 10)      /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
+#define CAN_MIR_CTRL_TXIE                        (0x1UL << 11)                           /**< Transmit Interrupt Enable */
+#define _CAN_MIR_CTRL_TXIE_SHIFT                 11                                      /**< Shift value for CAN_TXIE */
+#define _CAN_MIR_CTRL_TXIE_MASK                  0x800UL                                 /**< Bit mask for CAN_TXIE */
+#define _CAN_MIR_CTRL_TXIE_DEFAULT               0x00000000UL                            /**< Mode DEFAULT for CAN_MIR_CTRL */
+#define CAN_MIR_CTRL_TXIE_DEFAULT                (_CAN_MIR_CTRL_TXIE_DEFAULT << 11)      /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
+#define CAN_MIR_CTRL_UMASK                       (0x1UL << 12)                           /**< Use Acceptance Mask */
+#define _CAN_MIR_CTRL_UMASK_SHIFT                12                                      /**< Shift value for CAN_UMASK */
+#define _CAN_MIR_CTRL_UMASK_MASK                 0x1000UL                                /**< Bit mask for CAN_UMASK */
+#define _CAN_MIR_CTRL_UMASK_DEFAULT              0x00000000UL                            /**< Mode DEFAULT for CAN_MIR_CTRL */
+#define CAN_MIR_CTRL_UMASK_DEFAULT               (_CAN_MIR_CTRL_UMASK_DEFAULT << 12)     /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
+#define CAN_MIR_CTRL_INTPND                      (0x1UL << 13)                           /**< Interrupt Pending */
+#define _CAN_MIR_CTRL_INTPND_SHIFT               13                                      /**< Shift value for CAN_INTPND */
+#define _CAN_MIR_CTRL_INTPND_MASK                0x2000UL                                /**< Bit mask for CAN_INTPND */
+#define _CAN_MIR_CTRL_INTPND_DEFAULT             0x00000000UL                            /**< Mode DEFAULT for CAN_MIR_CTRL */
+#define CAN_MIR_CTRL_INTPND_DEFAULT              (_CAN_MIR_CTRL_INTPND_DEFAULT << 13)    /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
+#define CAN_MIR_CTRL_MESSAGEOF                   (0x1UL << 14)                           /**< Message Lost (only Valid for Message Objects With Direction = Receive) */
+#define _CAN_MIR_CTRL_MESSAGEOF_SHIFT            14                                      /**< Shift value for CAN_MESSAGEOF */
+#define _CAN_MIR_CTRL_MESSAGEOF_MASK             0x4000UL                                /**< Bit mask for CAN_MESSAGEOF */
+#define _CAN_MIR_CTRL_MESSAGEOF_DEFAULT          0x00000000UL                            /**< Mode DEFAULT for CAN_MIR_CTRL */
+#define CAN_MIR_CTRL_MESSAGEOF_DEFAULT           (_CAN_MIR_CTRL_MESSAGEOF_DEFAULT << 14) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
+#define CAN_MIR_CTRL_DATAVALID                   (0x1UL << 15)                           /**< New Data */
+#define _CAN_MIR_CTRL_DATAVALID_SHIFT            15                                      /**< Shift value for CAN_DATAVALID */
+#define _CAN_MIR_CTRL_DATAVALID_MASK             0x8000UL                                /**< Bit mask for CAN_DATAVALID */
+#define _CAN_MIR_CTRL_DATAVALID_DEFAULT          0x00000000UL                            /**< Mode DEFAULT for CAN_MIR_CTRL */
+#define CAN_MIR_CTRL_DATAVALID_DEFAULT           (_CAN_MIR_CTRL_DATAVALID_DEFAULT << 15) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
+
+/* Bit fields for CAN MIR_DATAL */
+#define _CAN_MIR_DATAL_RESETVALUE                0x00000000UL                         /**< Default value for CAN_MIR_DATAL */
+#define _CAN_MIR_DATAL_MASK                      0xFFFFFFFFUL                         /**< Mask for CAN_MIR_DATAL */
+#define _CAN_MIR_DATAL_DATA0_SHIFT               0                                    /**< Shift value for CAN_DATA0 */
+#define _CAN_MIR_DATAL_DATA0_MASK                0xFFUL                               /**< Bit mask for CAN_DATA0 */
+#define _CAN_MIR_DATAL_DATA0_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for CAN_MIR_DATAL */
+#define CAN_MIR_DATAL_DATA0_DEFAULT              (_CAN_MIR_DATAL_DATA0_DEFAULT << 0)  /**< Shifted mode DEFAULT for CAN_MIR_DATAL */
+#define _CAN_MIR_DATAL_DATA1_SHIFT               8                                    /**< Shift value for CAN_DATA1 */
+#define _CAN_MIR_DATAL_DATA1_MASK                0xFF00UL                             /**< Bit mask for CAN_DATA1 */
+#define _CAN_MIR_DATAL_DATA1_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for CAN_MIR_DATAL */
+#define CAN_MIR_DATAL_DATA1_DEFAULT              (_CAN_MIR_DATAL_DATA1_DEFAULT << 8)  /**< Shifted mode DEFAULT for CAN_MIR_DATAL */
+#define _CAN_MIR_DATAL_DATA2_SHIFT               16                                   /**< Shift value for CAN_DATA2 */
+#define _CAN_MIR_DATAL_DATA2_MASK                0xFF0000UL                           /**< Bit mask for CAN_DATA2 */
+#define _CAN_MIR_DATAL_DATA2_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for CAN_MIR_DATAL */
+#define CAN_MIR_DATAL_DATA2_DEFAULT              (_CAN_MIR_DATAL_DATA2_DEFAULT << 16) /**< Shifted mode DEFAULT for CAN_MIR_DATAL */
+#define _CAN_MIR_DATAL_DATA3_SHIFT               24                                   /**< Shift value for CAN_DATA3 */
+#define _CAN_MIR_DATAL_DATA3_MASK                0xFF000000UL                         /**< Bit mask for CAN_DATA3 */
+#define _CAN_MIR_DATAL_DATA3_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for CAN_MIR_DATAL */
+#define CAN_MIR_DATAL_DATA3_DEFAULT              (_CAN_MIR_DATAL_DATA3_DEFAULT << 24) /**< Shifted mode DEFAULT for CAN_MIR_DATAL */
+
+/* Bit fields for CAN MIR_DATAH */
+#define _CAN_MIR_DATAH_RESETVALUE                0x00000000UL                         /**< Default value for CAN_MIR_DATAH */
+#define _CAN_MIR_DATAH_MASK                      0xFFFFFFFFUL                         /**< Mask for CAN_MIR_DATAH */
+#define _CAN_MIR_DATAH_DATA4_SHIFT               0                                    /**< Shift value for CAN_DATA4 */
+#define _CAN_MIR_DATAH_DATA4_MASK                0xFFUL                               /**< Bit mask for CAN_DATA4 */
+#define _CAN_MIR_DATAH_DATA4_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for CAN_MIR_DATAH */
+#define CAN_MIR_DATAH_DATA4_DEFAULT              (_CAN_MIR_DATAH_DATA4_DEFAULT << 0)  /**< Shifted mode DEFAULT for CAN_MIR_DATAH */
+#define _CAN_MIR_DATAH_DATA5_SHIFT               8                                    /**< Shift value for CAN_DATA5 */
+#define _CAN_MIR_DATAH_DATA5_MASK                0xFF00UL                             /**< Bit mask for CAN_DATA5 */
+#define _CAN_MIR_DATAH_DATA5_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for CAN_MIR_DATAH */
+#define CAN_MIR_DATAH_DATA5_DEFAULT              (_CAN_MIR_DATAH_DATA5_DEFAULT << 8)  /**< Shifted mode DEFAULT for CAN_MIR_DATAH */
+#define _CAN_MIR_DATAH_DATA6_SHIFT               16                                   /**< Shift value for CAN_DATA6 */
+#define _CAN_MIR_DATAH_DATA6_MASK                0xFF0000UL                           /**< Bit mask for CAN_DATA6 */
+#define _CAN_MIR_DATAH_DATA6_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for CAN_MIR_DATAH */
+#define CAN_MIR_DATAH_DATA6_DEFAULT              (_CAN_MIR_DATAH_DATA6_DEFAULT << 16) /**< Shifted mode DEFAULT for CAN_MIR_DATAH */
+#define _CAN_MIR_DATAH_DATA7_SHIFT               24                                   /**< Shift value for CAN_DATA7 */
+#define _CAN_MIR_DATAH_DATA7_MASK                0xFF000000UL                         /**< Bit mask for CAN_DATA7 */
+#define _CAN_MIR_DATAH_DATA7_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for CAN_MIR_DATAH */
+#define CAN_MIR_DATAH_DATA7_DEFAULT              (_CAN_MIR_DATAH_DATA7_DEFAULT << 24) /**< Shifted mode DEFAULT for CAN_MIR_DATAH */
+
+/* Bit fields for CAN MIR_CMDREQ */
+#define _CAN_MIR_CMDREQ_RESETVALUE               0x00000001UL                          /**< Default value for CAN_MIR_CMDREQ */
+#define _CAN_MIR_CMDREQ_MASK                     0x0000803FUL                          /**< Mask for CAN_MIR_CMDREQ */
+#define _CAN_MIR_CMDREQ_MSGNUM_SHIFT             0                                     /**< Shift value for CAN_MSGNUM */
+#define _CAN_MIR_CMDREQ_MSGNUM_MASK              0x3FUL                                /**< Bit mask for CAN_MSGNUM */
+#define _CAN_MIR_CMDREQ_MSGNUM_DEFAULT           0x00000001UL                          /**< Mode DEFAULT for CAN_MIR_CMDREQ */
+#define CAN_MIR_CMDREQ_MSGNUM_DEFAULT            (_CAN_MIR_CMDREQ_MSGNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MIR_CMDREQ */
+#define CAN_MIR_CMDREQ_BUSY                      (0x1UL << 15)                         /**< Busy Flag */
+#define _CAN_MIR_CMDREQ_BUSY_SHIFT               15                                    /**< Shift value for CAN_BUSY */
+#define _CAN_MIR_CMDREQ_BUSY_MASK                0x8000UL                              /**< Bit mask for CAN_BUSY */
+#define _CAN_MIR_CMDREQ_BUSY_DEFAULT             0x00000000UL                          /**< Mode DEFAULT for CAN_MIR_CMDREQ */
+#define _CAN_MIR_CMDREQ_BUSY_FALSE               0x00000000UL                          /**< Mode FALSE for CAN_MIR_CMDREQ */
+#define _CAN_MIR_CMDREQ_BUSY_TRUE                0x00000001UL                          /**< Mode TRUE for CAN_MIR_CMDREQ */
+#define CAN_MIR_CMDREQ_BUSY_DEFAULT              (_CAN_MIR_CMDREQ_BUSY_DEFAULT << 15)  /**< Shifted mode DEFAULT for CAN_MIR_CMDREQ */
+#define CAN_MIR_CMDREQ_BUSY_FALSE                (_CAN_MIR_CMDREQ_BUSY_FALSE << 15)    /**< Shifted mode FALSE for CAN_MIR_CMDREQ */
+#define CAN_MIR_CMDREQ_BUSY_TRUE                 (_CAN_MIR_CMDREQ_BUSY_TRUE << 15)     /**< Shifted mode TRUE for CAN_MIR_CMDREQ */
+
+/** @} */
+/** @} End of group EFM32GG12B_CAN */
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+

cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b_can_mir.h

@@ -0,0 +1,65 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32GG12B_CAN_MIR register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @brief CAN_MIR CAN MIR Register
+ * @ingroup EFM32GG12B_CAN
+ ******************************************************************************/
+typedef struct {
+  __IOM uint32_t CMDMASK;       /**< Interface Command Mask Register  */
+  __IOM uint32_t MASK;          /**< Interface Mask Register  */
+  __IOM uint32_t ARB;           /**< Interface Arbitration Register  */
+  __IOM uint32_t CTRL;          /**< Interface Message Control Register  */
+  __IOM uint32_t DATAL;         /**< Interface Data a Register  */
+  __IOM uint32_t DATAH;         /**< Interface Data B Register  */
+  __IOM uint32_t CMDREQ;        /**< Interface Command Request Register  */
+  uint32_t       RESERVED0[1U]; /**< Reserved future */
+} CAN_MIR_TypeDef;
+
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+

cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b_cryotimer.h

@@ -0,0 +1,183 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32GG12B_CRYOTIMER register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFM32GG12B_CRYOTIMER CRYOTIMER
+ * @{
+ * @brief EFM32GG12B_CRYOTIMER Register Declaration
+ ******************************************************************************/
+/** CRYOTIMER Register Declaration */
+typedef struct {
+  __IOM uint32_t CTRL;      /**< Control Register  */
+  __IOM uint32_t PERIODSEL; /**< Interrupt Duration  */
+  __IM uint32_t  CNT;       /**< Counter Value  */
+  __IOM uint32_t EM4WUEN;   /**< Wake Up Enable  */
+  __IM uint32_t  IF;        /**< Interrupt Flag Register  */
+  __IOM uint32_t IFS;       /**< Interrupt Flag Set Register  */
+  __IOM uint32_t IFC;       /**< Interrupt Flag Clear Register  */
+  __IOM uint32_t IEN;       /**< Interrupt Enable Register  */
+} CRYOTIMER_TypeDef;        /** @} */
+
+/***************************************************************************//**
+ * @addtogroup EFM32GG12B_CRYOTIMER
+ * @{
+ * @defgroup EFM32GG12B_CRYOTIMER_BitFields  CRYOTIMER Bit Fields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for CRYOTIMER CTRL */
+#define _CRYOTIMER_CTRL_RESETVALUE                0x00000000UL                            /**< Default value for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_MASK                      0x000000EFUL                            /**< Mask for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_EN                         (0x1UL << 0)                            /**< Enable CRYOTIMER */
+#define _CRYOTIMER_CTRL_EN_SHIFT                  0                                       /**< Shift value for CRYOTIMER_EN */
+#define _CRYOTIMER_CTRL_EN_MASK                   0x1UL                                   /**< Bit mask for CRYOTIMER_EN */
+#define _CRYOTIMER_CTRL_EN_DEFAULT                0x00000000UL                            /**< Mode DEFAULT for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_EN_DEFAULT                 (_CRYOTIMER_CTRL_EN_DEFAULT << 0)       /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_DEBUGRUN                   (0x1UL << 1)                            /**< Debug Mode Run Enable */
+#define _CRYOTIMER_CTRL_DEBUGRUN_SHIFT            1                                       /**< Shift value for CRYOTIMER_DEBUGRUN */
+#define _CRYOTIMER_CTRL_DEBUGRUN_MASK             0x2UL                                   /**< Bit mask for CRYOTIMER_DEBUGRUN */
+#define _CRYOTIMER_CTRL_DEBUGRUN_DEFAULT          0x00000000UL                            /**< Mode DEFAULT for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_DEBUGRUN_DEFAULT           (_CRYOTIMER_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_OSCSEL_SHIFT              2                                       /**< Shift value for CRYOTIMER_OSCSEL */
+#define _CRYOTIMER_CTRL_OSCSEL_MASK               0xCUL                                   /**< Bit mask for CRYOTIMER_OSCSEL */
+#define _CRYOTIMER_CTRL_OSCSEL_DEFAULT            0x00000000UL                            /**< Mode DEFAULT for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_OSCSEL_DISABLED           0x00000000UL                            /**< Mode DISABLED for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_OSCSEL_LFRCO              0x00000001UL                            /**< Mode LFRCO for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_OSCSEL_LFXO               0x00000002UL                            /**< Mode LFXO for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_OSCSEL_ULFRCO             0x00000003UL                            /**< Mode ULFRCO for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_OSCSEL_DEFAULT             (_CRYOTIMER_CTRL_OSCSEL_DEFAULT << 2)   /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_OSCSEL_DISABLED            (_CRYOTIMER_CTRL_OSCSEL_DISABLED << 2)  /**< Shifted mode DISABLED for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_OSCSEL_LFRCO               (_CRYOTIMER_CTRL_OSCSEL_LFRCO << 2)     /**< Shifted mode LFRCO for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_OSCSEL_LFXO                (_CRYOTIMER_CTRL_OSCSEL_LFXO << 2)      /**< Shifted mode LFXO for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_OSCSEL_ULFRCO              (_CRYOTIMER_CTRL_OSCSEL_ULFRCO << 2)    /**< Shifted mode ULFRCO for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_PRESC_SHIFT               5                                       /**< Shift value for CRYOTIMER_PRESC */
+#define _CRYOTIMER_CTRL_PRESC_MASK                0xE0UL                                  /**< Bit mask for CRYOTIMER_PRESC */
+#define _CRYOTIMER_CTRL_PRESC_DEFAULT             0x00000000UL                            /**< Mode DEFAULT for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_PRESC_DIV1                0x00000000UL                            /**< Mode DIV1 for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_PRESC_DIV2                0x00000001UL                            /**< Mode DIV2 for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_PRESC_DIV4                0x00000002UL                            /**< Mode DIV4 for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_PRESC_DIV8                0x00000003UL                            /**< Mode DIV8 for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_PRESC_DIV16               0x00000004UL                            /**< Mode DIV16 for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_PRESC_DIV32               0x00000005UL                            /**< Mode DIV32 for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_PRESC_DIV64               0x00000006UL                            /**< Mode DIV64 for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_PRESC_DIV128              0x00000007UL                            /**< Mode DIV128 for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_PRESC_DEFAULT              (_CRYOTIMER_CTRL_PRESC_DEFAULT << 5)    /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_PRESC_DIV1                 (_CRYOTIMER_CTRL_PRESC_DIV1 << 5)       /**< Shifted mode DIV1 for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_PRESC_DIV2                 (_CRYOTIMER_CTRL_PRESC_DIV2 << 5)       /**< Shifted mode DIV2 for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_PRESC_DIV4                 (_CRYOTIMER_CTRL_PRESC_DIV4 << 5)       /**< Shifted mode DIV4 for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_PRESC_DIV8                 (_CRYOTIMER_CTRL_PRESC_DIV8 << 5)       /**< Shifted mode DIV8 for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_PRESC_DIV16                (_CRYOTIMER_CTRL_PRESC_DIV16 << 5)      /**< Shifted mode DIV16 for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_PRESC_DIV32                (_CRYOTIMER_CTRL_PRESC_DIV32 << 5)      /**< Shifted mode DIV32 for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_PRESC_DIV64                (_CRYOTIMER_CTRL_PRESC_DIV64 << 5)      /**< Shifted mode DIV64 for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_PRESC_DIV128               (_CRYOTIMER_CTRL_PRESC_DIV128 << 5)     /**< Shifted mode DIV128 for CRYOTIMER_CTRL */
+
+/* Bit fields for CRYOTIMER PERIODSEL */
+#define _CRYOTIMER_PERIODSEL_RESETVALUE           0x00000020UL                                  /**< Default value for CRYOTIMER_PERIODSEL */
+#define _CRYOTIMER_PERIODSEL_MASK                 0x0000003FUL                                  /**< Mask for CRYOTIMER_PERIODSEL */
+#define _CRYOTIMER_PERIODSEL_PERIODSEL_SHIFT      0                                             /**< Shift value for CRYOTIMER_PERIODSEL */
+#define _CRYOTIMER_PERIODSEL_PERIODSEL_MASK       0x3FUL                                        /**< Bit mask for CRYOTIMER_PERIODSEL */
+#define _CRYOTIMER_PERIODSEL_PERIODSEL_DEFAULT    0x00000020UL                                  /**< Mode DEFAULT for CRYOTIMER_PERIODSEL */
+#define CRYOTIMER_PERIODSEL_PERIODSEL_DEFAULT     (_CRYOTIMER_PERIODSEL_PERIODSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_PERIODSEL */
+
+/* Bit fields for CRYOTIMER CNT */
+#define _CRYOTIMER_CNT_RESETVALUE                 0x00000000UL                      /**< Default value for CRYOTIMER_CNT */
+#define _CRYOTIMER_CNT_MASK                       0xFFFFFFFFUL                      /**< Mask for CRYOTIMER_CNT */
+#define _CRYOTIMER_CNT_CNT_SHIFT                  0                                 /**< Shift value for CRYOTIMER_CNT */
+#define _CRYOTIMER_CNT_CNT_MASK                   0xFFFFFFFFUL                      /**< Bit mask for CRYOTIMER_CNT */
+#define _CRYOTIMER_CNT_CNT_DEFAULT                0x00000000UL                      /**< Mode DEFAULT for CRYOTIMER_CNT */
+#define CRYOTIMER_CNT_CNT_DEFAULT                 (_CRYOTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_CNT */
+
+/* Bit fields for CRYOTIMER EM4WUEN */
+#define _CRYOTIMER_EM4WUEN_RESETVALUE             0x00000000UL                            /**< Default value for CRYOTIMER_EM4WUEN */
+#define _CRYOTIMER_EM4WUEN_MASK                   0x00000001UL                            /**< Mask for CRYOTIMER_EM4WUEN */
+#define CRYOTIMER_EM4WUEN_EM4WU                   (0x1UL << 0)                            /**< EM4 Wake-up Enable */
+#define _CRYOTIMER_EM4WUEN_EM4WU_SHIFT            0                                       /**< Shift value for CRYOTIMER_EM4WU */
+#define _CRYOTIMER_EM4WUEN_EM4WU_MASK             0x1UL                                   /**< Bit mask for CRYOTIMER_EM4WU */
+#define _CRYOTIMER_EM4WUEN_EM4WU_DEFAULT          0x00000000UL                            /**< Mode DEFAULT for CRYOTIMER_EM4WUEN */
+#define CRYOTIMER_EM4WUEN_EM4WU_DEFAULT           (_CRYOTIMER_EM4WUEN_EM4WU_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_EM4WUEN */
+
+/* Bit fields for CRYOTIMER IF */
+#define _CRYOTIMER_IF_RESETVALUE                  0x00000000UL                        /**< Default value for CRYOTIMER_IF */
+#define _CRYOTIMER_IF_MASK                        0x00000001UL                        /**< Mask for CRYOTIMER_IF */
+#define CRYOTIMER_IF_PERIOD                       (0x1UL << 0)                        /**< Wakeup Event/Interrupt */
+#define _CRYOTIMER_IF_PERIOD_SHIFT                0                                   /**< Shift value for CRYOTIMER_PERIOD */
+#define _CRYOTIMER_IF_PERIOD_MASK                 0x1UL                               /**< Bit mask for CRYOTIMER_PERIOD */
+#define _CRYOTIMER_IF_PERIOD_DEFAULT              0x00000000UL                        /**< Mode DEFAULT for CRYOTIMER_IF */
+#define CRYOTIMER_IF_PERIOD_DEFAULT               (_CRYOTIMER_IF_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IF */
+
+/* Bit fields for CRYOTIMER IFS */
+#define _CRYOTIMER_IFS_RESETVALUE                 0x00000000UL                         /**< Default value for CRYOTIMER_IFS */
+#define _CRYOTIMER_IFS_MASK                       0x00000001UL                         /**< Mask for CRYOTIMER_IFS */
+#define CRYOTIMER_IFS_PERIOD                      (0x1UL << 0)                         /**< Set PERIOD Interrupt Flag */
+#define _CRYOTIMER_IFS_PERIOD_SHIFT               0                                    /**< Shift value for CRYOTIMER_PERIOD */
+#define _CRYOTIMER_IFS_PERIOD_MASK                0x1UL                                /**< Bit mask for CRYOTIMER_PERIOD */
+#define _CRYOTIMER_IFS_PERIOD_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for CRYOTIMER_IFS */
+#define CRYOTIMER_IFS_PERIOD_DEFAULT              (_CRYOTIMER_IFS_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IFS */
+
+/* Bit fields for CRYOTIMER IFC */
+#define _CRYOTIMER_IFC_RESETVALUE                 0x00000000UL                         /**< Default value for CRYOTIMER_IFC */
+#define _CRYOTIMER_IFC_MASK                       0x00000001UL                         /**< Mask for CRYOTIMER_IFC */
+#define CRYOTIMER_IFC_PERIOD                      (0x1UL << 0)                         /**< Clear PERIOD Interrupt Flag */
+#define _CRYOTIMER_IFC_PERIOD_SHIFT               0                                    /**< Shift value for CRYOTIMER_PERIOD */
+#define _CRYOTIMER_IFC_PERIOD_MASK                0x1UL                                /**< Bit mask for CRYOTIMER_PERIOD */
+#define _CRYOTIMER_IFC_PERIOD_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for CRYOTIMER_IFC */
+#define CRYOTIMER_IFC_PERIOD_DEFAULT              (_CRYOTIMER_IFC_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IFC */
+
+/* Bit fields for CRYOTIMER IEN */
+#define _CRYOTIMER_IEN_RESETVALUE                 0x00000000UL                         /**< Default value for CRYOTIMER_IEN */
+#define _CRYOTIMER_IEN_MASK                       0x00000001UL                         /**< Mask for CRYOTIMER_IEN */
+#define CRYOTIMER_IEN_PERIOD                      (0x1UL << 0)                         /**< PERIOD Interrupt Enable */
+#define _CRYOTIMER_IEN_PERIOD_SHIFT               0                                    /**< Shift value for CRYOTIMER_PERIOD */
+#define _CRYOTIMER_IEN_PERIOD_MASK                0x1UL                                /**< Bit mask for CRYOTIMER_PERIOD */
+#define _CRYOTIMER_IEN_PERIOD_DEFAULT             0x00000000UL                         /**< Mode DEFAULT for CRYOTIMER_IEN */
+#define CRYOTIMER_IEN_PERIOD_DEFAULT              (_CRYOTIMER_IEN_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IEN */
+
+/** @} */
+/** @} End of group EFM32GG12B_CRYOTIMER */
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+

cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b_csen.h

@@ -0,0 +1,994 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32GG12B_CSEN register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFM32GG12B_CSEN CSEN
+ * @{
+ * @brief EFM32GG12B_CSEN Register Declaration
+ ******************************************************************************/
+/** CSEN Register Declaration */
+typedef struct {
+  __IOM uint32_t CTRL;          /**< Control  */
+  __IOM uint32_t TIMCTRL;       /**< Timing Control  */
+  __IOM uint32_t CMD;           /**< Command  */
+  __IM uint32_t  STATUS;        /**< Status  */
+  __IOM uint32_t PRSSEL;        /**< PRS Select  */
+  __IOM uint32_t DATA;          /**< Output Data  */
+  __IOM uint32_t SCANMASK0;     /**< Scan Channel Mask 0  */
+  __IOM uint32_t SCANINPUTSEL0; /**< Scan Input Selection 0  */
+  __IOM uint32_t SCANMASK1;     /**< Scan Channel Mask 1  */
+  __IOM uint32_t SCANINPUTSEL1; /**< Scan Input Selection 1  */
+  __IM uint32_t  APORTREQ;      /**< APORT Request Status  */
+  __IM uint32_t  APORTCONFLICT; /**< APORT Request Conflict  */
+  __IOM uint32_t CMPTHR;        /**< Comparator Threshold  */
+  __IOM uint32_t EMA;           /**< Exponential Moving Average  */
+  __IOM uint32_t EMACTRL;       /**< Exponential Moving Average Control  */
+  __IOM uint32_t SINGLECTRL;    /**< Single Conversion Control  */
+  __IOM uint32_t DMBASELINE;    /**< Delta Modulation Baseline  */
+  __IOM uint32_t DMCFG;         /**< Delta Modulation Configuration  */
+  __IOM uint32_t ANACTRL;       /**< Analog Control  */
+
+  uint32_t       RESERVED0[2U]; /**< Reserved for future use **/
+  __IM uint32_t  IF;            /**< Interrupt Flag  */
+  __IOM uint32_t IFS;           /**< Interrupt Flag Set  */
+  __IOM uint32_t IFC;           /**< Interrupt Flag Clear  */
+  __IOM uint32_t IEN;           /**< Interrupt Enable  */
+} CSEN_TypeDef;                 /** @} */
+
+/***************************************************************************//**
+ * @addtogroup EFM32GG12B_CSEN
+ * @{
+ * @defgroup EFM32GG12B_CSEN_BitFields  CSEN Bit Fields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for CSEN CTRL */
+#define _CSEN_CTRL_RESETVALUE                                0x00030000UL                               /**< Default value for CSEN_CTRL */
+#define _CSEN_CTRL_MASK                                      0x1FFFF336UL                               /**< Mask for CSEN_CTRL */
+#define CSEN_CTRL_EN                                         (0x1UL << 1)                               /**< CSEN Enable */
+#define _CSEN_CTRL_EN_SHIFT                                  1                                          /**< Shift value for CSEN_EN */
+#define _CSEN_CTRL_EN_MASK                                   0x2UL                                      /**< Bit mask for CSEN_EN */
+#define _CSEN_CTRL_EN_DEFAULT                                0x00000000UL                               /**< Mode DEFAULT for CSEN_CTRL */
+#define _CSEN_CTRL_EN_DISABLE                                0x00000000UL                               /**< Mode DISABLE for CSEN_CTRL */
+#define _CSEN_CTRL_EN_ENABLE                                 0x00000001UL                               /**< Mode ENABLE for CSEN_CTRL */
+#define CSEN_CTRL_EN_DEFAULT                                 (_CSEN_CTRL_EN_DEFAULT << 1)               /**< Shifted mode DEFAULT for CSEN_CTRL */
+#define CSEN_CTRL_EN_DISABLE                                 (_CSEN_CTRL_EN_DISABLE << 1)               /**< Shifted mode DISABLE for CSEN_CTRL */
+#define CSEN_CTRL_EN_ENABLE                                  (_CSEN_CTRL_EN_ENABLE << 1)                /**< Shifted mode ENABLE for CSEN_CTRL */
+#define CSEN_CTRL_CMPPOL                                     (0x1UL << 2)                               /**< CSEN Digital Comparator Polarity Select */
+#define _CSEN_CTRL_CMPPOL_SHIFT                              2                                          /**< Shift value for CSEN_CMPPOL */
+#define _CSEN_CTRL_CMPPOL_MASK                               0x4UL                                      /**< Bit mask for CSEN_CMPPOL */
+#define _CSEN_CTRL_CMPPOL_DEFAULT                            0x00000000UL                               /**< Mode DEFAULT for CSEN_CTRL */
+#define _CSEN_CTRL_CMPPOL_GT                                 0x00000000UL                               /**< Mode GT for CSEN_CTRL */
+#define _CSEN_CTRL_CMPPOL_LTE                                0x00000001UL                               /**< Mode LTE for CSEN_CTRL */
+#define CSEN_CTRL_CMPPOL_DEFAULT                             (_CSEN_CTRL_CMPPOL_DEFAULT << 2)           /**< Shifted mode DEFAULT for CSEN_CTRL */
+#define CSEN_CTRL_CMPPOL_GT                                  (_CSEN_CTRL_CMPPOL_GT << 2)                /**< Shifted mode GT for CSEN_CTRL */
+#define CSEN_CTRL_CMPPOL_LTE                                 (_CSEN_CTRL_CMPPOL_LTE << 2)               /**< Shifted mode LTE for CSEN_CTRL */
+#define _CSEN_CTRL_CM_SHIFT                                  4                                          /**< Shift value for CSEN_CM */
+#define _CSEN_CTRL_CM_MASK                                   0x30UL                                     /**< Bit mask for CSEN_CM */
+#define _CSEN_CTRL_CM_DEFAULT                                0x00000000UL                               /**< Mode DEFAULT for CSEN_CTRL */
+#define _CSEN_CTRL_CM_SGL                                    0x00000000UL                               /**< Mode SGL for CSEN_CTRL */
+#define _CSEN_CTRL_CM_SCAN                                   0x00000001UL                               /**< Mode SCAN for CSEN_CTRL */
+#define _CSEN_CTRL_CM_CONTSGL                                0x00000002UL                               /**< Mode CONTSGL for CSEN_CTRL */
+#define _CSEN_CTRL_CM_CONTSCAN                               0x00000003UL                               /**< Mode CONTSCAN for CSEN_CTRL */
+#define CSEN_CTRL_CM_DEFAULT                                 (_CSEN_CTRL_CM_DEFAULT << 4)               /**< Shifted mode DEFAULT for CSEN_CTRL */
+#define CSEN_CTRL_CM_SGL                                     (_CSEN_CTRL_CM_SGL << 4)                   /**< Shifted mode SGL for CSEN_CTRL */
+#define CSEN_CTRL_CM_SCAN                                    (_CSEN_CTRL_CM_SCAN << 4)                  /**< Shifted mode SCAN for CSEN_CTRL */
+#define CSEN_CTRL_CM_CONTSGL                                 (_CSEN_CTRL_CM_CONTSGL << 4)               /**< Shifted mode CONTSGL for CSEN_CTRL */
+#define CSEN_CTRL_CM_CONTSCAN                                (_CSEN_CTRL_CM_CONTSCAN << 4)              /**< Shifted mode CONTSCAN for CSEN_CTRL */
+#define _CSEN_CTRL_SARCR_SHIFT                               8                                          /**< Shift value for CSEN_SARCR */
+#define _CSEN_CTRL_SARCR_MASK                                0x300UL                                    /**< Bit mask for CSEN_SARCR */
+#define _CSEN_CTRL_SARCR_DEFAULT                             0x00000000UL                               /**< Mode DEFAULT for CSEN_CTRL */
+#define _CSEN_CTRL_SARCR_CLK10                               0x00000000UL                               /**< Mode CLK10 for CSEN_CTRL */
+#define _CSEN_CTRL_SARCR_CLK12                               0x00000001UL                               /**< Mode CLK12 for CSEN_CTRL */
+#define _CSEN_CTRL_SARCR_CLK14                               0x00000002UL                               /**< Mode CLK14 for CSEN_CTRL */
+#define _CSEN_CTRL_SARCR_CLK16                               0x00000003UL                               /**< Mode CLK16 for CSEN_CTRL */
+#define CSEN_CTRL_SARCR_DEFAULT                              (_CSEN_CTRL_SARCR_DEFAULT << 8)            /**< Shifted mode DEFAULT for CSEN_CTRL */
+#define CSEN_CTRL_SARCR_CLK10                                (_CSEN_CTRL_SARCR_CLK10 << 8)              /**< Shifted mode CLK10 for CSEN_CTRL */
+#define CSEN_CTRL_SARCR_CLK12                                (_CSEN_CTRL_SARCR_CLK12 << 8)              /**< Shifted mode CLK12 for CSEN_CTRL */
+#define CSEN_CTRL_SARCR_CLK14                                (_CSEN_CTRL_SARCR_CLK14 << 8)              /**< Shifted mode CLK14 for CSEN_CTRL */
+#define CSEN_CTRL_SARCR_CLK16                                (_CSEN_CTRL_SARCR_CLK16 << 8)              /**< Shifted mode CLK16 for CSEN_CTRL */
+#define _CSEN_CTRL_ACU_SHIFT                                 12                                         /**< Shift value for CSEN_ACU */
+#define _CSEN_CTRL_ACU_MASK                                  0x7000UL                                   /**< Bit mask for CSEN_ACU */
+#define _CSEN_CTRL_ACU_DEFAULT                               0x00000000UL                               /**< Mode DEFAULT for CSEN_CTRL */
+#define _CSEN_CTRL_ACU_ACC1                                  0x00000000UL                               /**< Mode ACC1 for CSEN_CTRL */
+#define _CSEN_CTRL_ACU_ACC2                                  0x00000001UL                               /**< Mode ACC2 for CSEN_CTRL */
+#define _CSEN_CTRL_ACU_ACC4                                  0x00000002UL                               /**< Mode ACC4 for CSEN_CTRL */
+#define _CSEN_CTRL_ACU_ACC8                                  0x00000003UL                               /**< Mode ACC8 for CSEN_CTRL */
+#define _CSEN_CTRL_ACU_ACC16                                 0x00000004UL                               /**< Mode ACC16 for CSEN_CTRL */
+#define _CSEN_CTRL_ACU_ACC32                                 0x00000005UL                               /**< Mode ACC32 for CSEN_CTRL */
+#define _CSEN_CTRL_ACU_ACC64                                 0x00000006UL                               /**< Mode ACC64 for CSEN_CTRL */
+#define CSEN_CTRL_ACU_DEFAULT                                (_CSEN_CTRL_ACU_DEFAULT << 12)             /**< Shifted mode DEFAULT for CSEN_CTRL */
+#define CSEN_CTRL_ACU_ACC1                                   (_CSEN_CTRL_ACU_ACC1 << 12)                /**< Shifted mode ACC1 for CSEN_CTRL */
+#define CSEN_CTRL_ACU_ACC2                                   (_CSEN_CTRL_ACU_ACC2 << 12)                /**< Shifted mode ACC2 for CSEN_CTRL */
+#define CSEN_CTRL_ACU_ACC4                                   (_CSEN_CTRL_ACU_ACC4 << 12)                /**< Shifted mode ACC4 for CSEN_CTRL */
+#define CSEN_CTRL_ACU_ACC8                                   (_CSEN_CTRL_ACU_ACC8 << 12)                /**< Shifted mode ACC8 for CSEN_CTRL */
+#define CSEN_CTRL_ACU_ACC16                                  (_CSEN_CTRL_ACU_ACC16 << 12)               /**< Shifted mode ACC16 for CSEN_CTRL */
+#define CSEN_CTRL_ACU_ACC32                                  (_CSEN_CTRL_ACU_ACC32 << 12)               /**< Shifted mode ACC32 for CSEN_CTRL */
+#define CSEN_CTRL_ACU_ACC64                                  (_CSEN_CTRL_ACU_ACC64 << 12)               /**< Shifted mode ACC64 for CSEN_CTRL */
+#define CSEN_CTRL_MCEN                                       (0x1UL << 15)                              /**< CSEN Multiple Channel Enable */
+#define _CSEN_CTRL_MCEN_SHIFT                                15                                         /**< Shift value for CSEN_MCEN */
+#define _CSEN_CTRL_MCEN_MASK                                 0x8000UL                                   /**< Bit mask for CSEN_MCEN */
+#define _CSEN_CTRL_MCEN_DEFAULT                              0x00000000UL                               /**< Mode DEFAULT for CSEN_CTRL */
+#define _CSEN_CTRL_MCEN_DISABLE                              0x00000000UL                               /**< Mode DISABLE for CSEN_CTRL */
+#define _CSEN_CTRL_MCEN_ENABLE                               0x00000001UL                               /**< Mode ENABLE for CSEN_CTRL */
+#define CSEN_CTRL_MCEN_DEFAULT                               (_CSEN_CTRL_MCEN_DEFAULT << 15)            /**< Shifted mode DEFAULT for CSEN_CTRL */
+#define CSEN_CTRL_MCEN_DISABLE                               (_CSEN_CTRL_MCEN_DISABLE << 15)            /**< Shifted mode DISABLE for CSEN_CTRL */
+#define CSEN_CTRL_MCEN_ENABLE                                (_CSEN_CTRL_MCEN_ENABLE << 15)             /**< Shifted mode ENABLE for CSEN_CTRL */
+#define _CSEN_CTRL_STM_SHIFT                                 16                                         /**< Shift value for CSEN_STM */
+#define _CSEN_CTRL_STM_MASK                                  0x30000UL                                  /**< Bit mask for CSEN_STM */
+#define _CSEN_CTRL_STM_PRS                                   0x00000000UL                               /**< Mode PRS for CSEN_CTRL */
+#define _CSEN_CTRL_STM_TIMER                                 0x00000001UL                               /**< Mode TIMER for CSEN_CTRL */
+#define _CSEN_CTRL_STM_START                                 0x00000002UL                               /**< Mode START for CSEN_CTRL */
+#define _CSEN_CTRL_STM_DEFAULT                               0x00000003UL                               /**< Mode DEFAULT for CSEN_CTRL */
+#define _CSEN_CTRL_STM_DEFAULT                               0x00000003UL                               /**< Mode DEFAULT for CSEN_CTRL */
+#define CSEN_CTRL_STM_PRS                                    (_CSEN_CTRL_STM_PRS << 16)                 /**< Shifted mode PRS for CSEN_CTRL */
+#define CSEN_CTRL_STM_TIMER                                  (_CSEN_CTRL_STM_TIMER << 16)               /**< Shifted mode TIMER for CSEN_CTRL */
+#define CSEN_CTRL_STM_START                                  (_CSEN_CTRL_STM_START << 16)               /**< Shifted mode START for CSEN_CTRL */
+#define CSEN_CTRL_STM_DEFAULT                                (_CSEN_CTRL_STM_DEFAULT << 16)             /**< Shifted mode DEFAULT for CSEN_CTRL */
+#define CSEN_CTRL_STM_DEFAULT                                (_CSEN_CTRL_STM_DEFAULT << 16)             /**< Shifted mode DEFAULT for CSEN_CTRL */
+#define CSEN_CTRL_CMPEN                                      (0x1UL << 18)                              /**< CSEN Digital Comparator Enable */
+#define _CSEN_CTRL_CMPEN_SHIFT                               18                                         /**< Shift value for CSEN_CMPEN */
+#define _CSEN_CTRL_CMPEN_MASK                                0x40000UL                                  /**< Bit mask for CSEN_CMPEN */
+#define _CSEN_CTRL_CMPEN_DEFAULT                             0x00000000UL                               /**< Mode DEFAULT for CSEN_CTRL */
+#define _CSEN_CTRL_CMPEN_DISABLE                             0x00000000UL                               /**< Mode DISABLE for CSEN_CTRL */
+#define _CSEN_CTRL_CMPEN_ENABLE                              0x00000001UL                               /**< Mode ENABLE for CSEN_CTRL */
+#define CSEN_CTRL_CMPEN_DEFAULT                              (_CSEN_CTRL_CMPEN_DEFAULT << 18)           /**< Shifted mode DEFAULT for CSEN_CTRL */
+#define CSEN_CTRL_CMPEN_DISABLE                              (_CSEN_CTRL_CMPEN_DISABLE << 18)           /**< Shifted mode DISABLE for CSEN_CTRL */
+#define CSEN_CTRL_CMPEN_ENABLE                               (_CSEN_CTRL_CMPEN_ENABLE << 18)            /**< Shifted mode ENABLE for CSEN_CTRL */
+#define CSEN_CTRL_DRSF                                       (0x1UL << 19)                              /**< CSEN Disable Right-Shift */
+#define _CSEN_CTRL_DRSF_SHIFT                                19                                         /**< Shift value for CSEN_DRSF */
+#define _CSEN_CTRL_DRSF_MASK                                 0x80000UL                                  /**< Bit mask for CSEN_DRSF */
+#define _CSEN_CTRL_DRSF_DEFAULT                              0x00000000UL                               /**< Mode DEFAULT for CSEN_CTRL */
+#define _CSEN_CTRL_DRSF_DISABLE                              0x00000000UL                               /**< Mode DISABLE for CSEN_CTRL */
+#define _CSEN_CTRL_DRSF_ENABLE                               0x00000001UL                               /**< Mode ENABLE for CSEN_CTRL */
+#define CSEN_CTRL_DRSF_DEFAULT                               (_CSEN_CTRL_DRSF_DEFAULT << 19)            /**< Shifted mode DEFAULT for CSEN_CTRL */
+#define CSEN_CTRL_DRSF_DISABLE                               (_CSEN_CTRL_DRSF_DISABLE << 19)            /**< Shifted mode DISABLE for CSEN_CTRL */
+#define CSEN_CTRL_DRSF_ENABLE                                (_CSEN_CTRL_DRSF_ENABLE << 19)             /**< Shifted mode ENABLE for CSEN_CTRL */
+#define CSEN_CTRL_DMAEN                                      (0x1UL << 20)                              /**< CSEN DMA Enable Bit */
+#define _CSEN_CTRL_DMAEN_SHIFT                               20                                         /**< Shift value for CSEN_DMAEN */
+#define _CSEN_CTRL_DMAEN_MASK                                0x100000UL                                 /**< Bit mask for CSEN_DMAEN */
+#define _CSEN_CTRL_DMAEN_DEFAULT                             0x00000000UL                               /**< Mode DEFAULT for CSEN_CTRL */
+#define _CSEN_CTRL_DMAEN_DISABLE                             0x00000000UL                               /**< Mode DISABLE for CSEN_CTRL */
+#define _CSEN_CTRL_DMAEN_ENABLE                              0x00000001UL                               /**< Mode ENABLE for CSEN_CTRL */
+#define CSEN_CTRL_DMAEN_DEFAULT                              (_CSEN_CTRL_DMAEN_DEFAULT << 20)           /**< Shifted mode DEFAULT for CSEN_CTRL */
+#define CSEN_CTRL_DMAEN_DISABLE                              (_CSEN_CTRL_DMAEN_DISABLE << 20)           /**< Shifted mode DISABLE for CSEN_CTRL */
+#define CSEN_CTRL_DMAEN_ENABLE                               (_CSEN_CTRL_DMAEN_ENABLE << 20)            /**< Shifted mode ENABLE for CSEN_CTRL */
+#define CSEN_CTRL_CONVSEL                                    (0x1UL << 21)                              /**< CSEN Converter Select */
+#define _CSEN_CTRL_CONVSEL_SHIFT                             21                                         /**< Shift value for CSEN_CONVSEL */
+#define _CSEN_CTRL_CONVSEL_MASK                              0x200000UL                                 /**< Bit mask for CSEN_CONVSEL */
+#define _CSEN_CTRL_CONVSEL_DEFAULT                           0x00000000UL                               /**< Mode DEFAULT for CSEN_CTRL */
+#define _CSEN_CTRL_CONVSEL_SAR                               0x00000000UL                               /**< Mode SAR for CSEN_CTRL */
+#define _CSEN_CTRL_CONVSEL_DM                                0x00000001UL                               /**< Mode DM for CSEN_CTRL */
+#define CSEN_CTRL_CONVSEL_DEFAULT                            (_CSEN_CTRL_CONVSEL_DEFAULT << 21)         /**< Shifted mode DEFAULT for CSEN_CTRL */
+#define CSEN_CTRL_CONVSEL_SAR                                (_CSEN_CTRL_CONVSEL_SAR << 21)             /**< Shifted mode SAR for CSEN_CTRL */
+#define CSEN_CTRL_CONVSEL_DM                                 (_CSEN_CTRL_CONVSEL_DM << 21)              /**< Shifted mode DM for CSEN_CTRL */
+#define CSEN_CTRL_CHOPEN                                     (0x1UL << 22)                              /**< CSEN Chop Enable */
+#define _CSEN_CTRL_CHOPEN_SHIFT                              22                                         /**< Shift value for CSEN_CHOPEN */
+#define _CSEN_CTRL_CHOPEN_MASK                               0x400000UL                                 /**< Bit mask for CSEN_CHOPEN */
+#define _CSEN_CTRL_CHOPEN_DEFAULT                            0x00000000UL                               /**< Mode DEFAULT for CSEN_CTRL */
+#define _CSEN_CTRL_CHOPEN_DISABLE                            0x00000000UL                               /**< Mode DISABLE for CSEN_CTRL */
+#define _CSEN_CTRL_CHOPEN_ENABLE                             0x00000001UL                               /**< Mode ENABLE for CSEN_CTRL */
+#define CSEN_CTRL_CHOPEN_DEFAULT                             (_CSEN_CTRL_CHOPEN_DEFAULT << 22)          /**< Shifted mode DEFAULT for CSEN_CTRL */
+#define CSEN_CTRL_CHOPEN_DISABLE                             (_CSEN_CTRL_CHOPEN_DISABLE << 22)          /**< Shifted mode DISABLE for CSEN_CTRL */
+#define CSEN_CTRL_CHOPEN_ENABLE                              (_CSEN_CTRL_CHOPEN_ENABLE << 22)           /**< Shifted mode ENABLE for CSEN_CTRL */
+#define CSEN_CTRL_AUTOGND                                    (0x1UL << 23)                              /**< CSEN Automatic Ground Enable */
+#define _CSEN_CTRL_AUTOGND_SHIFT                             23                                         /**< Shift value for CSEN_AUTOGND */
+#define _CSEN_CTRL_AUTOGND_MASK                              0x800000UL                                 /**< Bit mask for CSEN_AUTOGND */
+#define _CSEN_CTRL_AUTOGND_DEFAULT                           0x00000000UL                               /**< Mode DEFAULT for CSEN_CTRL */
+#define _CSEN_CTRL_AUTOGND_DISABLE                           0x00000000UL                               /**< Mode DISABLE for CSEN_CTRL */
+#define _CSEN_CTRL_AUTOGND_ENABLE                            0x00000001UL                               /**< Mode ENABLE for CSEN_CTRL */
+#define CSEN_CTRL_AUTOGND_DEFAULT                            (_CSEN_CTRL_AUTOGND_DEFAULT << 23)         /**< Shifted mode DEFAULT for CSEN_CTRL */
+#define CSEN_CTRL_AUTOGND_DISABLE                            (_CSEN_CTRL_AUTOGND_DISABLE << 23)         /**< Shifted mode DISABLE for CSEN_CTRL */
+#define CSEN_CTRL_AUTOGND_ENABLE                             (_CSEN_CTRL_AUTOGND_ENABLE << 23)          /**< Shifted mode ENABLE for CSEN_CTRL */
+#define CSEN_CTRL_MXUC                                       (0x1UL << 24)                              /**< CSEN Mux Disconnect */
+#define _CSEN_CTRL_MXUC_SHIFT                                24                                         /**< Shift value for CSEN_MXUC */
+#define _CSEN_CTRL_MXUC_MASK                                 0x1000000UL                                /**< Bit mask for CSEN_MXUC */
+#define _CSEN_CTRL_MXUC_DEFAULT                              0x00000000UL                               /**< Mode DEFAULT for CSEN_CTRL */
+#define _CSEN_CTRL_MXUC_CONN                                 0x00000000UL                               /**< Mode CONN for CSEN_CTRL */
+#define _CSEN_CTRL_MXUC_UNC                                  0x00000001UL                               /**< Mode UNC for CSEN_CTRL */
+#define CSEN_CTRL_MXUC_DEFAULT                               (_CSEN_CTRL_MXUC_DEFAULT << 24)            /**< Shifted mode DEFAULT for CSEN_CTRL */
+#define CSEN_CTRL_MXUC_CONN                                  (_CSEN_CTRL_MXUC_CONN << 24)               /**< Shifted mode CONN for CSEN_CTRL */
+#define CSEN_CTRL_MXUC_UNC                                   (_CSEN_CTRL_MXUC_UNC << 24)                /**< Shifted mode UNC for CSEN_CTRL */
+#define CSEN_CTRL_EMACMPEN                                   (0x1UL << 25)                              /**< Greater and Less Than Comparison Using the Exponential Moving Average (EMA) is Enabled */
+#define _CSEN_CTRL_EMACMPEN_SHIFT                            25                                         /**< Shift value for CSEN_EMACMPEN */
+#define _CSEN_CTRL_EMACMPEN_MASK                             0x2000000UL                                /**< Bit mask for CSEN_EMACMPEN */
+#define _CSEN_CTRL_EMACMPEN_DEFAULT                          0x00000000UL                               /**< Mode DEFAULT for CSEN_CTRL */
+#define CSEN_CTRL_EMACMPEN_DEFAULT                           (_CSEN_CTRL_EMACMPEN_DEFAULT << 25)        /**< Shifted mode DEFAULT for CSEN_CTRL */
+#define CSEN_CTRL_WARMUPMODE                                 (0x1UL << 26)                              /**< Select Warmup Mode for CSEN */
+#define _CSEN_CTRL_WARMUPMODE_SHIFT                          26                                         /**< Shift value for CSEN_WARMUPMODE */
+#define _CSEN_CTRL_WARMUPMODE_MASK                           0x4000000UL                                /**< Bit mask for CSEN_WARMUPMODE */
+#define _CSEN_CTRL_WARMUPMODE_DEFAULT                        0x00000000UL                               /**< Mode DEFAULT for CSEN_CTRL */
+#define _CSEN_CTRL_WARMUPMODE_NORMAL                         0x00000000UL                               /**< Mode NORMAL for CSEN_CTRL */
+#define _CSEN_CTRL_WARMUPMODE_KEEPCSENWARM                   0x00000001UL                               /**< Mode KEEPCSENWARM for CSEN_CTRL */
+#define CSEN_CTRL_WARMUPMODE_DEFAULT                         (_CSEN_CTRL_WARMUPMODE_DEFAULT << 26)      /**< Shifted mode DEFAULT for CSEN_CTRL */
+#define CSEN_CTRL_WARMUPMODE_NORMAL                          (_CSEN_CTRL_WARMUPMODE_NORMAL << 26)       /**< Shifted mode NORMAL for CSEN_CTRL */
+#define CSEN_CTRL_WARMUPMODE_KEEPCSENWARM                    (_CSEN_CTRL_WARMUPMODE_KEEPCSENWARM << 26) /**< Shifted mode KEEPCSENWARM for CSEN_CTRL */
+#define CSEN_CTRL_LOCALSENS                                  (0x1UL << 27)                              /**< Local Sensing Enable */
+#define _CSEN_CTRL_LOCALSENS_SHIFT                           27                                         /**< Shift value for CSEN_LOCALSENS */
+#define _CSEN_CTRL_LOCALSENS_MASK                            0x8000000UL                                /**< Bit mask for CSEN_LOCALSENS */
+#define _CSEN_CTRL_LOCALSENS_DEFAULT                         0x00000000UL                               /**< Mode DEFAULT for CSEN_CTRL */
+#define CSEN_CTRL_LOCALSENS_DEFAULT                          (_CSEN_CTRL_LOCALSENS_DEFAULT << 27)       /**< Shifted mode DEFAULT for CSEN_CTRL */
+#define CSEN_CTRL_CPACCURACY                                 (0x1UL << 28)                              /**< Charge Pump Accuracy */
+#define _CSEN_CTRL_CPACCURACY_SHIFT                          28                                         /**< Shift value for CSEN_CPACCURACY */
+#define _CSEN_CTRL_CPACCURACY_MASK                           0x10000000UL                               /**< Bit mask for CSEN_CPACCURACY */
+#define _CSEN_CTRL_CPACCURACY_DEFAULT                        0x00000000UL                               /**< Mode DEFAULT for CSEN_CTRL */
+#define _CSEN_CTRL_CPACCURACY_LO                             0x00000000UL                               /**< Mode LO for CSEN_CTRL */
+#define _CSEN_CTRL_CPACCURACY_HI                             0x00000001UL                               /**< Mode HI for CSEN_CTRL */
+#define CSEN_CTRL_CPACCURACY_DEFAULT                         (_CSEN_CTRL_CPACCURACY_DEFAULT << 28)      /**< Shifted mode DEFAULT for CSEN_CTRL */
+#define CSEN_CTRL_CPACCURACY_LO                              (_CSEN_CTRL_CPACCURACY_LO << 28)           /**< Shifted mode LO for CSEN_CTRL */
+#define CSEN_CTRL_CPACCURACY_HI                              (_CSEN_CTRL_CPACCURACY_HI << 28)           /**< Shifted mode HI for CSEN_CTRL */
+
+/* Bit fields for CSEN TIMCTRL */
+#define _CSEN_TIMCTRL_RESETVALUE                             0x00000000UL                            /**< Default value for CSEN_TIMCTRL */
+#define _CSEN_TIMCTRL_MASK                                   0x0003FF07UL                            /**< Mask for CSEN_TIMCTRL */
+#define _CSEN_TIMCTRL_PCPRESC_SHIFT                          0                                       /**< Shift value for CSEN_PCPRESC */
+#define _CSEN_TIMCTRL_PCPRESC_MASK                           0x7UL                                   /**< Bit mask for CSEN_PCPRESC */
+#define _CSEN_TIMCTRL_PCPRESC_DEFAULT                        0x00000000UL                            /**< Mode DEFAULT for CSEN_TIMCTRL */
+#define _CSEN_TIMCTRL_PCPRESC_DIV1                           0x00000000UL                            /**< Mode DIV1 for CSEN_TIMCTRL */
+#define _CSEN_TIMCTRL_PCPRESC_DIV2                           0x00000001UL                            /**< Mode DIV2 for CSEN_TIMCTRL */
+#define _CSEN_TIMCTRL_PCPRESC_DIV4                           0x00000002UL                            /**< Mode DIV4 for CSEN_TIMCTRL */
+#define _CSEN_TIMCTRL_PCPRESC_DIV8                           0x00000003UL                            /**< Mode DIV8 for CSEN_TIMCTRL */
+#define _CSEN_TIMCTRL_PCPRESC_DIV16                          0x00000004UL                            /**< Mode DIV16 for CSEN_TIMCTRL */
+#define _CSEN_TIMCTRL_PCPRESC_DIV32                          0x00000005UL                            /**< Mode DIV32 for CSEN_TIMCTRL */
+#define _CSEN_TIMCTRL_PCPRESC_DIV64                          0x00000006UL                            /**< Mode DIV64 for CSEN_TIMCTRL */
+#define _CSEN_TIMCTRL_PCPRESC_DIV128                         0x00000007UL                            /**< Mode DIV128 for CSEN_TIMCTRL */
+#define CSEN_TIMCTRL_PCPRESC_DEFAULT                         (_CSEN_TIMCTRL_PCPRESC_DEFAULT << 0)    /**< Shifted mode DEFAULT for CSEN_TIMCTRL */
+#define CSEN_TIMCTRL_PCPRESC_DIV1                            (_CSEN_TIMCTRL_PCPRESC_DIV1 << 0)       /**< Shifted mode DIV1 for CSEN_TIMCTRL */
+#define CSEN_TIMCTRL_PCPRESC_DIV2                            (_CSEN_TIMCTRL_PCPRESC_DIV2 << 0)       /**< Shifted mode DIV2 for CSEN_TIMCTRL */
+#define CSEN_TIMCTRL_PCPRESC_DIV4                            (_CSEN_TIMCTRL_PCPRESC_DIV4 << 0)       /**< Shifted mode DIV4 for CSEN_TIMCTRL */
+#define CSEN_TIMCTRL_PCPRESC_DIV8                            (_CSEN_TIMCTRL_PCPRESC_DIV8 << 0)       /**< Shifted mode DIV8 for CSEN_TIMCTRL */
+#define CSEN_TIMCTRL_PCPRESC_DIV16                           (_CSEN_TIMCTRL_PCPRESC_DIV16 << 0)      /**< Shifted mode DIV16 for CSEN_TIMCTRL */
+#define CSEN_TIMCTRL_PCPRESC_DIV32                           (_CSEN_TIMCTRL_PCPRESC_DIV32 << 0)      /**< Shifted mode DIV32 for CSEN_TIMCTRL */
+#define CSEN_TIMCTRL_PCPRESC_DIV64                           (_CSEN_TIMCTRL_PCPRESC_DIV64 << 0)      /**< Shifted mode DIV64 for CSEN_TIMCTRL */
+#define CSEN_TIMCTRL_PCPRESC_DIV128                          (_CSEN_TIMCTRL_PCPRESC_DIV128 << 0)     /**< Shifted mode DIV128 for CSEN_TIMCTRL */
+#define _CSEN_TIMCTRL_PCTOP_SHIFT                            8                                       /**< Shift value for CSEN_PCTOP */
+#define _CSEN_TIMCTRL_PCTOP_MASK                             0xFF00UL                                /**< Bit mask for CSEN_PCTOP */
+#define _CSEN_TIMCTRL_PCTOP_DEFAULT                          0x00000000UL                            /**< Mode DEFAULT for CSEN_TIMCTRL */
+#define CSEN_TIMCTRL_PCTOP_DEFAULT                           (_CSEN_TIMCTRL_PCTOP_DEFAULT << 8)      /**< Shifted mode DEFAULT for CSEN_TIMCTRL */
+#define _CSEN_TIMCTRL_WARMUPCNT_SHIFT                        16                                      /**< Shift value for CSEN_WARMUPCNT */
+#define _CSEN_TIMCTRL_WARMUPCNT_MASK                         0x30000UL                               /**< Bit mask for CSEN_WARMUPCNT */
+#define _CSEN_TIMCTRL_WARMUPCNT_DEFAULT                      0x00000000UL                            /**< Mode DEFAULT for CSEN_TIMCTRL */
+#define CSEN_TIMCTRL_WARMUPCNT_DEFAULT                       (_CSEN_TIMCTRL_WARMUPCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_TIMCTRL */
+
+/* Bit fields for CSEN CMD */
+#define _CSEN_CMD_RESETVALUE                                 0x00000000UL                   /**< Default value for CSEN_CMD */
+#define _CSEN_CMD_MASK                                       0x00000001UL                   /**< Mask for CSEN_CMD */
+#define CSEN_CMD_START                                       (0x1UL << 0)                   /**< Start Software-Triggered Conversions */
+#define _CSEN_CMD_START_SHIFT                                0                              /**< Shift value for CSEN_START */
+#define _CSEN_CMD_START_MASK                                 0x1UL                          /**< Bit mask for CSEN_START */
+#define _CSEN_CMD_START_DEFAULT                              0x00000000UL                   /**< Mode DEFAULT for CSEN_CMD */
+#define CSEN_CMD_START_DEFAULT                               (_CSEN_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_CMD */
+
+/* Bit fields for CSEN STATUS */
+#define _CSEN_STATUS_RESETVALUE                              0x00000000UL                         /**< Default value for CSEN_STATUS */
+#define _CSEN_STATUS_MASK                                    0x00000001UL                         /**< Mask for CSEN_STATUS */
+#define CSEN_STATUS_CSENBUSY                                 (0x1UL << 0)                         /**< Busy Flag */
+#define _CSEN_STATUS_CSENBUSY_SHIFT                          0                                    /**< Shift value for CSEN_CSENBUSY */
+#define _CSEN_STATUS_CSENBUSY_MASK                           0x1UL                                /**< Bit mask for CSEN_CSENBUSY */
+#define _CSEN_STATUS_CSENBUSY_DEFAULT                        0x00000000UL                         /**< Mode DEFAULT for CSEN_STATUS */
+#define _CSEN_STATUS_CSENBUSY_IDLE                           0x00000000UL                         /**< Mode IDLE for CSEN_STATUS */
+#define _CSEN_STATUS_CSENBUSY_BUSY                           0x00000001UL                         /**< Mode BUSY for CSEN_STATUS */
+#define CSEN_STATUS_CSENBUSY_DEFAULT                         (_CSEN_STATUS_CSENBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_STATUS */
+#define CSEN_STATUS_CSENBUSY_IDLE                            (_CSEN_STATUS_CSENBUSY_IDLE << 0)    /**< Shifted mode IDLE for CSEN_STATUS */
+#define CSEN_STATUS_CSENBUSY_BUSY                            (_CSEN_STATUS_CSENBUSY_BUSY << 0)    /**< Shifted mode BUSY for CSEN_STATUS */
+
+/* Bit fields for CSEN PRSSEL */
+#define _CSEN_PRSSEL_RESETVALUE                              0x00000000UL                       /**< Default value for CSEN_PRSSEL */
+#define _CSEN_PRSSEL_MASK                                    0x0000000FUL                       /**< Mask for CSEN_PRSSEL */
+#define _CSEN_PRSSEL_PRSSEL_SHIFT                            0                                  /**< Shift value for CSEN_PRSSEL */
+#define _CSEN_PRSSEL_PRSSEL_MASK                             0xFUL                              /**< Bit mask for CSEN_PRSSEL */
+#define _CSEN_PRSSEL_PRSSEL_DEFAULT                          0x00000000UL                       /**< Mode DEFAULT for CSEN_PRSSEL */
+#define _CSEN_PRSSEL_PRSSEL_PRSCH0                           0x00000000UL                       /**< Mode PRSCH0 for CSEN_PRSSEL */
+#define _CSEN_PRSSEL_PRSSEL_PRSCH1                           0x00000001UL                       /**< Mode PRSCH1 for CSEN_PRSSEL */
+#define _CSEN_PRSSEL_PRSSEL_PRSCH2                           0x00000002UL                       /**< Mode PRSCH2 for CSEN_PRSSEL */
+#define _CSEN_PRSSEL_PRSSEL_PRSCH3                           0x00000003UL                       /**< Mode PRSCH3 for CSEN_PRSSEL */
+#define _CSEN_PRSSEL_PRSSEL_PRSCH4                           0x00000004UL                       /**< Mode PRSCH4 for CSEN_PRSSEL */
+#define _CSEN_PRSSEL_PRSSEL_PRSCH5                           0x00000005UL                       /**< Mode PRSCH5 for CSEN_PRSSEL */
+#define _CSEN_PRSSEL_PRSSEL_PRSCH6                           0x00000006UL                       /**< Mode PRSCH6 for CSEN_PRSSEL */
+#define _CSEN_PRSSEL_PRSSEL_PRSCH7                           0x00000007UL                       /**< Mode PRSCH7 for CSEN_PRSSEL */
+#define _CSEN_PRSSEL_PRSSEL_PRSCH8                           0x00000008UL                       /**< Mode PRSCH8 for CSEN_PRSSEL */
+#define _CSEN_PRSSEL_PRSSEL_PRSCH9                           0x00000009UL                       /**< Mode PRSCH9 for CSEN_PRSSEL */
+#define _CSEN_PRSSEL_PRSSEL_PRSCH10                          0x0000000AUL                       /**< Mode PRSCH10 for CSEN_PRSSEL */
+#define _CSEN_PRSSEL_PRSSEL_PRSCH11                          0x0000000BUL                       /**< Mode PRSCH11 for CSEN_PRSSEL */
+#define _CSEN_PRSSEL_PRSSEL_PRSCH12                          0x0000000CUL                       /**< Mode PRSCH12 for CSEN_PRSSEL */
+#define _CSEN_PRSSEL_PRSSEL_PRSCH13                          0x0000000DUL                       /**< Mode PRSCH13 for CSEN_PRSSEL */
+#define _CSEN_PRSSEL_PRSSEL_PRSCH14                          0x0000000EUL                       /**< Mode PRSCH14 for CSEN_PRSSEL */
+#define _CSEN_PRSSEL_PRSSEL_PRSCH15                          0x0000000FUL                       /**< Mode PRSCH15 for CSEN_PRSSEL */
+#define CSEN_PRSSEL_PRSSEL_DEFAULT                           (_CSEN_PRSSEL_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_PRSSEL */
+#define CSEN_PRSSEL_PRSSEL_PRSCH0                            (_CSEN_PRSSEL_PRSSEL_PRSCH0 << 0)  /**< Shifted mode PRSCH0 for CSEN_PRSSEL */
+#define CSEN_PRSSEL_PRSSEL_PRSCH1                            (_CSEN_PRSSEL_PRSSEL_PRSCH1 << 0)  /**< Shifted mode PRSCH1 for CSEN_PRSSEL */
+#define CSEN_PRSSEL_PRSSEL_PRSCH2                            (_CSEN_PRSSEL_PRSSEL_PRSCH2 << 0)  /**< Shifted mode PRSCH2 for CSEN_PRSSEL */
+#define CSEN_PRSSEL_PRSSEL_PRSCH3                            (_CSEN_PRSSEL_PRSSEL_PRSCH3 << 0)  /**< Shifted mode PRSCH3 for CSEN_PRSSEL */
+#define CSEN_PRSSEL_PRSSEL_PRSCH4                            (_CSEN_PRSSEL_PRSSEL_PRSCH4 << 0)  /**< Shifted mode PRSCH4 for CSEN_PRSSEL */
+#define CSEN_PRSSEL_PRSSEL_PRSCH5                            (_CSEN_PRSSEL_PRSSEL_PRSCH5 << 0)  /**< Shifted mode PRSCH5 for CSEN_PRSSEL */
+#define CSEN_PRSSEL_PRSSEL_PRSCH6                            (_CSEN_PRSSEL_PRSSEL_PRSCH6 << 0)  /**< Shifted mode PRSCH6 for CSEN_PRSSEL */
+#define CSEN_PRSSEL_PRSSEL_PRSCH7                            (_CSEN_PRSSEL_PRSSEL_PRSCH7 << 0)  /**< Shifted mode PRSCH7 for CSEN_PRSSEL */
+#define CSEN_PRSSEL_PRSSEL_PRSCH8                            (_CSEN_PRSSEL_PRSSEL_PRSCH8 << 0)  /**< Shifted mode PRSCH8 for CSEN_PRSSEL */
+#define CSEN_PRSSEL_PRSSEL_PRSCH9                            (_CSEN_PRSSEL_PRSSEL_PRSCH9 << 0)  /**< Shifted mode PRSCH9 for CSEN_PRSSEL */
+#define CSEN_PRSSEL_PRSSEL_PRSCH10                           (_CSEN_PRSSEL_PRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for CSEN_PRSSEL */
+#define CSEN_PRSSEL_PRSSEL_PRSCH11                           (_CSEN_PRSSEL_PRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for CSEN_PRSSEL */
+#define CSEN_PRSSEL_PRSSEL_PRSCH12                           (_CSEN_PRSSEL_PRSSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for CSEN_PRSSEL */
+#define CSEN_PRSSEL_PRSSEL_PRSCH13                           (_CSEN_PRSSEL_PRSSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for CSEN_PRSSEL */
+#define CSEN_PRSSEL_PRSSEL_PRSCH14                           (_CSEN_PRSSEL_PRSSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for CSEN_PRSSEL */
+#define CSEN_PRSSEL_PRSSEL_PRSCH15                           (_CSEN_PRSSEL_PRSSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for CSEN_PRSSEL */
+
+/* Bit fields for CSEN DATA */
+#define _CSEN_DATA_RESETVALUE                                0x00000000UL                   /**< Default value for CSEN_DATA */
+#define _CSEN_DATA_MASK                                      0xFFFFFFFFUL                   /**< Mask for CSEN_DATA */
+#define _CSEN_DATA_DATA_SHIFT                                0                              /**< Shift value for CSEN_DATA */
+#define _CSEN_DATA_DATA_MASK                                 0xFFFFFFFFUL                   /**< Bit mask for CSEN_DATA */
+#define _CSEN_DATA_DATA_DEFAULT                              0x00000000UL                   /**< Mode DEFAULT for CSEN_DATA */
+#define CSEN_DATA_DATA_DEFAULT                               (_CSEN_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_DATA */
+
+/* Bit fields for CSEN SCANMASK0 */
+#define _CSEN_SCANMASK0_RESETVALUE                           0x00000000UL                               /**< Default value for CSEN_SCANMASK0 */
+#define _CSEN_SCANMASK0_MASK                                 0xFFFFFFFFUL                               /**< Mask for CSEN_SCANMASK0 */
+#define _CSEN_SCANMASK0_SCANINPUTEN_SHIFT                    0                                          /**< Shift value for CSEN_SCANINPUTEN */
+#define _CSEN_SCANMASK0_SCANINPUTEN_MASK                     0xFFFFFFFFUL                               /**< Bit mask for CSEN_SCANINPUTEN */
+#define _CSEN_SCANMASK0_SCANINPUTEN_DEFAULT                  0x00000000UL                               /**< Mode DEFAULT for CSEN_SCANMASK0 */
+#define CSEN_SCANMASK0_SCANINPUTEN_DEFAULT                   (_CSEN_SCANMASK0_SCANINPUTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_SCANMASK0 */
+
+/* Bit fields for CSEN SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_RESETVALUE                       0x00000000UL                                              /**< Default value for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_MASK                             0x0F0F0F0FUL                                              /**< Mask for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_SHIFT               0                                                         /**< Shift value for CSEN_INPUT0TO7SEL */
+#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_MASK                0xFUL                                                     /**< Bit mask for CSEN_INPUT0TO7SEL */
+#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_DEFAULT             0x00000000UL                                              /**< Mode DEFAULT for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH0TO7        0x00000004UL                                              /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH8TO15       0x00000005UL                                              /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH16TO23      0x00000006UL                                              /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH24TO31      0x00000007UL                                              /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH0TO7        0x0000000CUL                                              /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH8TO15       0x0000000DUL                                              /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH16TO23      0x0000000EUL                                              /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH24TO31      0x0000000FUL                                              /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_DEFAULT              (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_DEFAULT << 0)           /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH0TO7         (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH0TO7 << 0)      /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH8TO15        (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH8TO15 << 0)     /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH16TO23       (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH16TO23 << 0)    /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH24TO31       (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH24TO31 << 0)    /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH0TO7         (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH0TO7 << 0)      /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH8TO15        (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH8TO15 << 0)     /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH16TO23       (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH16TO23 << 0)    /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH24TO31       (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH24TO31 << 0)    /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_SHIFT              8                                                         /**< Shift value for CSEN_INPUT8TO15SEL */
+#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_MASK               0xF00UL                                                   /**< Bit mask for CSEN_INPUT8TO15SEL */
+#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_DEFAULT            0x00000000UL                                              /**< Mode DEFAULT for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH0TO7       0x00000004UL                                              /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH8TO15      0x00000005UL                                              /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH16TO23     0x00000006UL                                              /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH24TO31     0x00000007UL                                              /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH0TO7       0x0000000CUL                                              /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH8TO15      0x0000000DUL                                              /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH16TO23     0x0000000EUL                                              /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH24TO31     0x0000000FUL                                              /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_DEFAULT             (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_DEFAULT << 8)          /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH0TO7        (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH0TO7 << 8)     /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH8TO15       (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH8TO15 << 8)    /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH16TO23      (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH16TO23 << 8)   /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH24TO31      (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH24TO31 << 8)   /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH0TO7        (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH0TO7 << 8)     /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH8TO15       (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH8TO15 << 8)    /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH16TO23      (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH16TO23 << 8)   /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH24TO31      (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH24TO31 << 8)   /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_SHIFT             16                                                        /**< Shift value for CSEN_INPUT16TO23SEL */
+#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_MASK              0xF0000UL                                                 /**< Bit mask for CSEN_INPUT16TO23SEL */
+#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_DEFAULT           0x00000000UL                                              /**< Mode DEFAULT for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH0TO7      0x00000004UL                                              /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH8TO15     0x00000005UL                                              /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH16TO23    0x00000006UL                                              /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH24TO31    0x00000007UL                                              /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH0TO7      0x0000000CUL                                              /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH8TO15     0x0000000DUL                                              /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH16TO23    0x0000000EUL                                              /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH24TO31    0x0000000FUL                                              /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_DEFAULT            (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_DEFAULT << 16)        /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH0TO7       (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH0TO7 << 16)   /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH8TO15      (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH8TO15 << 16)  /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH16TO23     (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH16TO23 << 16) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH24TO31     (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH24TO31 << 16) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH0TO7       (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH0TO7 << 16)   /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH8TO15      (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH8TO15 << 16)  /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH16TO23     (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH16TO23 << 16) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH24TO31     (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH24TO31 << 16) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_SHIFT             24                                                        /**< Shift value for CSEN_INPUT24TO31SEL */
+#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_MASK              0xF000000UL                                               /**< Bit mask for CSEN_INPUT24TO31SEL */
+#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_DEFAULT           0x00000000UL                                              /**< Mode DEFAULT for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH0TO7      0x00000004UL                                              /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH8TO15     0x00000005UL                                              /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH16TO23    0x00000006UL                                              /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH24TO31    0x00000007UL                                              /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH0TO7      0x0000000CUL                                              /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH8TO15     0x0000000DUL                                              /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH16TO23    0x0000000EUL                                              /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */
+#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH24TO31    0x0000000FUL                                              /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_DEFAULT            (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_DEFAULT << 24)        /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH0TO7       (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH0TO7 << 24)   /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH8TO15      (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH8TO15 << 24)  /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH16TO23     (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH16TO23 << 24) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH24TO31     (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH24TO31 << 24) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH0TO7       (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH0TO7 << 24)   /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH8TO15      (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH8TO15 << 24)  /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH16TO23     (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH16TO23 << 24) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */
+#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH24TO31     (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH24TO31 << 24) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */
+
+/* Bit fields for CSEN SCANMASK1 */
+#define _CSEN_SCANMASK1_RESETVALUE                           0x00000000UL                               /**< Default value for CSEN_SCANMASK1 */
+#define _CSEN_SCANMASK1_MASK                                 0xFFFFFFFFUL                               /**< Mask for CSEN_SCANMASK1 */
+#define _CSEN_SCANMASK1_SCANINPUTEN_SHIFT                    0                                          /**< Shift value for CSEN_SCANINPUTEN */
+#define _CSEN_SCANMASK1_SCANINPUTEN_MASK                     0xFFFFFFFFUL                               /**< Bit mask for CSEN_SCANINPUTEN */
+#define _CSEN_SCANMASK1_SCANINPUTEN_DEFAULT                  0x00000000UL                               /**< Mode DEFAULT for CSEN_SCANMASK1 */
+#define CSEN_SCANMASK1_SCANINPUTEN_DEFAULT                   (_CSEN_SCANMASK1_SCANINPUTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_SCANMASK1 */
+
+/* Bit fields for CSEN SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_RESETVALUE                       0x00000000UL                                              /**< Default value for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_MASK                             0x0F0F0F0FUL                                              /**< Mask for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_SHIFT             0                                                         /**< Shift value for CSEN_INPUT32TO39SEL */
+#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_MASK              0xFUL                                                     /**< Bit mask for CSEN_INPUT32TO39SEL */
+#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_DEFAULT           0x00000000UL                                              /**< Mode DEFAULT for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH0TO7      0x00000004UL                                              /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH8TO15     0x00000005UL                                              /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH16TO23    0x00000006UL                                              /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH24TO31    0x00000007UL                                              /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH0TO7      0x0000000CUL                                              /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH8TO15     0x0000000DUL                                              /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH16TO23    0x0000000EUL                                              /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH24TO31    0x0000000FUL                                              /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_DEFAULT            (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_DEFAULT << 0)         /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH0TO7       (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH0TO7 << 0)    /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH8TO15      (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH8TO15 << 0)   /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH16TO23     (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH16TO23 << 0)  /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH24TO31     (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH24TO31 << 0)  /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH0TO7       (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH0TO7 << 0)    /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH8TO15      (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH8TO15 << 0)   /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH16TO23     (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH16TO23 << 0)  /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH24TO31     (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH24TO31 << 0)  /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_SHIFT             8                                                         /**< Shift value for CSEN_INPUT40TO47SEL */
+#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_MASK              0xF00UL                                                   /**< Bit mask for CSEN_INPUT40TO47SEL */
+#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_DEFAULT           0x00000000UL                                              /**< Mode DEFAULT for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH0TO7      0x00000004UL                                              /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH8TO15     0x00000005UL                                              /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH16TO23    0x00000006UL                                              /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH24TO31    0x00000007UL                                              /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH0TO7      0x0000000CUL                                              /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH8TO15     0x0000000DUL                                              /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH16TO23    0x0000000EUL                                              /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH24TO31    0x0000000FUL                                              /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_DEFAULT            (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_DEFAULT << 8)         /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH0TO7       (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH0TO7 << 8)    /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH8TO15      (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH8TO15 << 8)   /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH16TO23     (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH16TO23 << 8)  /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH24TO31     (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH24TO31 << 8)  /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH0TO7       (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH0TO7 << 8)    /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH8TO15      (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH8TO15 << 8)   /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH16TO23     (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH16TO23 << 8)  /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH24TO31     (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH24TO31 << 8)  /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_SHIFT             16                                                        /**< Shift value for CSEN_INPUT48TO55SEL */
+#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_MASK              0xF0000UL                                                 /**< Bit mask for CSEN_INPUT48TO55SEL */
+#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_DEFAULT           0x00000000UL                                              /**< Mode DEFAULT for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH0TO7      0x00000004UL                                              /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH8TO15     0x00000005UL                                              /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH16TO23    0x00000006UL                                              /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH24TO31    0x00000007UL                                              /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH0TO7      0x0000000CUL                                              /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH8TO15     0x0000000DUL                                              /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH16TO23    0x0000000EUL                                              /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH24TO31    0x0000000FUL                                              /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_DEFAULT            (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_DEFAULT << 16)        /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH0TO7       (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH0TO7 << 16)   /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH8TO15      (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH8TO15 << 16)  /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH16TO23     (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH16TO23 << 16) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH24TO31     (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH24TO31 << 16) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH0TO7       (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH0TO7 << 16)   /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH8TO15      (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH8TO15 << 16)  /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH16TO23     (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH16TO23 << 16) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH24TO31     (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH24TO31 << 16) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_SHIFT             24                                                        /**< Shift value for CSEN_INPUT56TO63SEL */
+#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_MASK              0xF000000UL                                               /**< Bit mask for CSEN_INPUT56TO63SEL */
+#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_DEFAULT           0x00000000UL                                              /**< Mode DEFAULT for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH0TO7      0x00000004UL                                              /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH8TO15     0x00000005UL                                              /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH16TO23    0x00000006UL                                              /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH24TO31    0x00000007UL                                              /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH0TO7      0x0000000CUL                                              /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH8TO15     0x0000000DUL                                              /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH16TO23    0x0000000EUL                                              /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */
+#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH24TO31    0x0000000FUL                                              /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_DEFAULT            (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_DEFAULT << 24)        /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH0TO7       (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH0TO7 << 24)   /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH8TO15      (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH8TO15 << 24)  /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH16TO23     (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH16TO23 << 24) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH24TO31     (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH24TO31 << 24) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH0TO7       (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH0TO7 << 24)   /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH8TO15      (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH8TO15 << 24)  /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH16TO23     (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH16TO23 << 24) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */
+#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH24TO31     (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH24TO31 << 24) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */
+
+/* Bit fields for CSEN APORTREQ */
+#define _CSEN_APORTREQ_RESETVALUE                            0x00000000UL                             /**< Default value for CSEN_APORTREQ */
+#define _CSEN_APORTREQ_MASK                                  0x000003FCUL                             /**< Mask for CSEN_APORTREQ */
+#define CSEN_APORTREQ_APORT1XREQ                             (0x1UL << 2)                             /**< 1 If the Bus Connected to APORT2X is Requested */
+#define _CSEN_APORTREQ_APORT1XREQ_SHIFT                      2                                        /**< Shift value for CSEN_APORT1XREQ */
+#define _CSEN_APORTREQ_APORT1XREQ_MASK                       0x4UL                                    /**< Bit mask for CSEN_APORT1XREQ */
+#define _CSEN_APORTREQ_APORT1XREQ_DEFAULT                    0x00000000UL                             /**< Mode DEFAULT for CSEN_APORTREQ */
+#define CSEN_APORTREQ_APORT1XREQ_DEFAULT                     (_CSEN_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_APORTREQ */
+#define CSEN_APORTREQ_APORT1YREQ                             (0x1UL << 3)                             /**< 1 If the Bus Connected to APORT1X is Requested */
+#define _CSEN_APORTREQ_APORT1YREQ_SHIFT                      3                                        /**< Shift value for CSEN_APORT1YREQ */
+#define _CSEN_APORTREQ_APORT1YREQ_MASK                       0x8UL                                    /**< Bit mask for CSEN_APORT1YREQ */
+#define _CSEN_APORTREQ_APORT1YREQ_DEFAULT                    0x00000000UL                             /**< Mode DEFAULT for CSEN_APORTREQ */
+#define CSEN_APORTREQ_APORT1YREQ_DEFAULT                     (_CSEN_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_APORTREQ */
+#define CSEN_APORTREQ_APORT2XREQ                             (0x1UL << 4)                             /**< 1 If the Bus Connected to APORT2X is Requested */
+#define _CSEN_APORTREQ_APORT2XREQ_SHIFT                      4                                        /**< Shift value for CSEN_APORT2XREQ */
+#define _CSEN_APORTREQ_APORT2XREQ_MASK                       0x10UL                                   /**< Bit mask for CSEN_APORT2XREQ */
+#define _CSEN_APORTREQ_APORT2XREQ_DEFAULT                    0x00000000UL                             /**< Mode DEFAULT for CSEN_APORTREQ */
+#define CSEN_APORTREQ_APORT2XREQ_DEFAULT                     (_CSEN_APORTREQ_APORT2XREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_APORTREQ */
+#define CSEN_APORTREQ_APORT2YREQ                             (0x1UL << 5)                             /**< 1 If the Bus Connected to APORT2Y is Requested */
+#define _CSEN_APORTREQ_APORT2YREQ_SHIFT                      5                                        /**< Shift value for CSEN_APORT2YREQ */
+#define _CSEN_APORTREQ_APORT2YREQ_MASK                       0x20UL                                   /**< Bit mask for CSEN_APORT2YREQ */
+#define _CSEN_APORTREQ_APORT2YREQ_DEFAULT                    0x00000000UL                             /**< Mode DEFAULT for CSEN_APORTREQ */
+#define CSEN_APORTREQ_APORT2YREQ_DEFAULT                     (_CSEN_APORTREQ_APORT2YREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for CSEN_APORTREQ */
+#define CSEN_APORTREQ_APORT3XREQ                             (0x1UL << 6)                             /**< 1 If the Bus Connected to APORT3X is Requested */
+#define _CSEN_APORTREQ_APORT3XREQ_SHIFT                      6                                        /**< Shift value for CSEN_APORT3XREQ */
+#define _CSEN_APORTREQ_APORT3XREQ_MASK                       0x40UL                                   /**< Bit mask for CSEN_APORT3XREQ */
+#define _CSEN_APORTREQ_APORT3XREQ_DEFAULT                    0x00000000UL                             /**< Mode DEFAULT for CSEN_APORTREQ */
+#define CSEN_APORTREQ_APORT3XREQ_DEFAULT                     (_CSEN_APORTREQ_APORT3XREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for CSEN_APORTREQ */
+#define CSEN_APORTREQ_APORT3YREQ                             (0x1UL << 7)                             /**< 1 If the Bus Connected to APORT3Y is Requested */
+#define _CSEN_APORTREQ_APORT3YREQ_SHIFT                      7                                        /**< Shift value for CSEN_APORT3YREQ */
+#define _CSEN_APORTREQ_APORT3YREQ_MASK                       0x80UL                                   /**< Bit mask for CSEN_APORT3YREQ */
+#define _CSEN_APORTREQ_APORT3YREQ_DEFAULT                    0x00000000UL                             /**< Mode DEFAULT for CSEN_APORTREQ */
+#define CSEN_APORTREQ_APORT3YREQ_DEFAULT                     (_CSEN_APORTREQ_APORT3YREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for CSEN_APORTREQ */
+#define CSEN_APORTREQ_APORT4XREQ                             (0x1UL << 8)                             /**< 1 If the Bus Connected to APORT4X is Requested */
+#define _CSEN_APORTREQ_APORT4XREQ_SHIFT                      8                                        /**< Shift value for CSEN_APORT4XREQ */
+#define _CSEN_APORTREQ_APORT4XREQ_MASK                       0x100UL                                  /**< Bit mask for CSEN_APORT4XREQ */
+#define _CSEN_APORTREQ_APORT4XREQ_DEFAULT                    0x00000000UL                             /**< Mode DEFAULT for CSEN_APORTREQ */
+#define CSEN_APORTREQ_APORT4XREQ_DEFAULT                     (_CSEN_APORTREQ_APORT4XREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_APORTREQ */
+#define CSEN_APORTREQ_APORT4YREQ                             (0x1UL << 9)                             /**< 1 If the Bus Connected to APORT4Y is Requested */
+#define _CSEN_APORTREQ_APORT4YREQ_SHIFT                      9                                        /**< Shift value for CSEN_APORT4YREQ */
+#define _CSEN_APORTREQ_APORT4YREQ_MASK                       0x200UL                                  /**< Bit mask for CSEN_APORT4YREQ */
+#define _CSEN_APORTREQ_APORT4YREQ_DEFAULT                    0x00000000UL                             /**< Mode DEFAULT for CSEN_APORTREQ */
+#define CSEN_APORTREQ_APORT4YREQ_DEFAULT                     (_CSEN_APORTREQ_APORT4YREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for CSEN_APORTREQ */
+
+/* Bit fields for CSEN APORTCONFLICT */
+#define _CSEN_APORTCONFLICT_RESETVALUE                       0x00000000UL                                       /**< Default value for CSEN_APORTCONFLICT */
+#define _CSEN_APORTCONFLICT_MASK                             0x000003FCUL                                       /**< Mask for CSEN_APORTCONFLICT */
+#define CSEN_APORTCONFLICT_APORT1XCONFLICT                   (0x1UL << 2)                                       /**< 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral */
+#define _CSEN_APORTCONFLICT_APORT1XCONFLICT_SHIFT            2                                                  /**< Shift value for CSEN_APORT1XCONFLICT */
+#define _CSEN_APORTCONFLICT_APORT1XCONFLICT_MASK             0x4UL                                              /**< Bit mask for CSEN_APORT1XCONFLICT */
+#define _CSEN_APORTCONFLICT_APORT1XCONFLICT_DEFAULT          0x00000000UL                                       /**< Mode DEFAULT for CSEN_APORTCONFLICT */
+#define CSEN_APORTCONFLICT_APORT1XCONFLICT_DEFAULT           (_CSEN_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */
+#define CSEN_APORTCONFLICT_APORT1YCONFLICT                   (0x1UL << 3)                                       /**< 1 If the Bus Connected to APORT1Y is in Conflict With Another Peripheral */
+#define _CSEN_APORTCONFLICT_APORT1YCONFLICT_SHIFT            3                                                  /**< Shift value for CSEN_APORT1YCONFLICT */
+#define _CSEN_APORTCONFLICT_APORT1YCONFLICT_MASK             0x8UL                                              /**< Bit mask for CSEN_APORT1YCONFLICT */
+#define _CSEN_APORTCONFLICT_APORT1YCONFLICT_DEFAULT          0x00000000UL                                       /**< Mode DEFAULT for CSEN_APORTCONFLICT */
+#define CSEN_APORTCONFLICT_APORT1YCONFLICT_DEFAULT           (_CSEN_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */
+#define CSEN_APORTCONFLICT_APORT2XCONFLICT                   (0x1UL << 4)                                       /**< 1 If the Bus Connected to APORT2X is in Conflict With Another Peripheral */
+#define _CSEN_APORTCONFLICT_APORT2XCONFLICT_SHIFT            4                                                  /**< Shift value for CSEN_APORT2XCONFLICT */
+#define _CSEN_APORTCONFLICT_APORT2XCONFLICT_MASK             0x10UL                                             /**< Bit mask for CSEN_APORT2XCONFLICT */
+#define _CSEN_APORTCONFLICT_APORT2XCONFLICT_DEFAULT          0x00000000UL                                       /**< Mode DEFAULT for CSEN_APORTCONFLICT */
+#define CSEN_APORTCONFLICT_APORT2XCONFLICT_DEFAULT           (_CSEN_APORTCONFLICT_APORT2XCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */
+#define CSEN_APORTCONFLICT_APORT2YCONFLICT                   (0x1UL << 5)                                       /**< 1 If the Bus Connected to APORT2Y is in Conflict With Another Peripheral */
+#define _CSEN_APORTCONFLICT_APORT2YCONFLICT_SHIFT            5                                                  /**< Shift value for CSEN_APORT2YCONFLICT */
+#define _CSEN_APORTCONFLICT_APORT2YCONFLICT_MASK             0x20UL                                             /**< Bit mask for CSEN_APORT2YCONFLICT */
+#define _CSEN_APORTCONFLICT_APORT2YCONFLICT_DEFAULT          0x00000000UL                                       /**< Mode DEFAULT for CSEN_APORTCONFLICT */
+#define CSEN_APORTCONFLICT_APORT2YCONFLICT_DEFAULT           (_CSEN_APORTCONFLICT_APORT2YCONFLICT_DEFAULT << 5) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */
+#define CSEN_APORTCONFLICT_APORT3XCONFLICT                   (0x1UL << 6)                                       /**< 1 If the Bus Connected to APORT3X is in Conflict With Another Peripheral */
+#define _CSEN_APORTCONFLICT_APORT3XCONFLICT_SHIFT            6                                                  /**< Shift value for CSEN_APORT3XCONFLICT */
+#define _CSEN_APORTCONFLICT_APORT3XCONFLICT_MASK             0x40UL                                             /**< Bit mask for CSEN_APORT3XCONFLICT */
+#define _CSEN_APORTCONFLICT_APORT3XCONFLICT_DEFAULT          0x00000000UL                                       /**< Mode DEFAULT for CSEN_APORTCONFLICT */
+#define CSEN_APORTCONFLICT_APORT3XCONFLICT_DEFAULT           (_CSEN_APORTCONFLICT_APORT3XCONFLICT_DEFAULT << 6) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */
+#define CSEN_APORTCONFLICT_APORT3YCONFLICT                   (0x1UL << 7)                                       /**< 1 If the Bus Connected to APORT3Y is in Conflict With Another Peripheral */
+#define _CSEN_APORTCONFLICT_APORT3YCONFLICT_SHIFT            7                                                  /**< Shift value for CSEN_APORT3YCONFLICT */
+#define _CSEN_APORTCONFLICT_APORT3YCONFLICT_MASK             0x80UL                                             /**< Bit mask for CSEN_APORT3YCONFLICT */
+#define _CSEN_APORTCONFLICT_APORT3YCONFLICT_DEFAULT          0x00000000UL                                       /**< Mode DEFAULT for CSEN_APORTCONFLICT */
+#define CSEN_APORTCONFLICT_APORT3YCONFLICT_DEFAULT           (_CSEN_APORTCONFLICT_APORT3YCONFLICT_DEFAULT << 7) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */
+#define CSEN_APORTCONFLICT_APORT4XCONFLICT                   (0x1UL << 8)                                       /**< 1 If the Bus Connected to APORT4X is in Conflict With Another Peripheral */
+#define _CSEN_APORTCONFLICT_APORT4XCONFLICT_SHIFT            8                                                  /**< Shift value for CSEN_APORT4XCONFLICT */
+#define _CSEN_APORTCONFLICT_APORT4XCONFLICT_MASK             0x100UL                                            /**< Bit mask for CSEN_APORT4XCONFLICT */
+#define _CSEN_APORTCONFLICT_APORT4XCONFLICT_DEFAULT          0x00000000UL                                       /**< Mode DEFAULT for CSEN_APORTCONFLICT */
+#define CSEN_APORTCONFLICT_APORT4XCONFLICT_DEFAULT           (_CSEN_APORTCONFLICT_APORT4XCONFLICT_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */
+#define CSEN_APORTCONFLICT_APORT4YCONFLICT                   (0x1UL << 9)                                       /**< 1 If the Bus Connected to APORT4Y is in Conflict With Another Peripheral */
+#define _CSEN_APORTCONFLICT_APORT4YCONFLICT_SHIFT            9                                                  /**< Shift value for CSEN_APORT4YCONFLICT */
+#define _CSEN_APORTCONFLICT_APORT4YCONFLICT_MASK             0x200UL                                            /**< Bit mask for CSEN_APORT4YCONFLICT */
+#define _CSEN_APORTCONFLICT_APORT4YCONFLICT_DEFAULT          0x00000000UL                                       /**< Mode DEFAULT for CSEN_APORTCONFLICT */
+#define CSEN_APORTCONFLICT_APORT4YCONFLICT_DEFAULT           (_CSEN_APORTCONFLICT_APORT4YCONFLICT_DEFAULT << 9) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */
+
+/* Bit fields for CSEN CMPTHR */
+#define _CSEN_CMPTHR_RESETVALUE                              0x00000000UL                       /**< Default value for CSEN_CMPTHR */
+#define _CSEN_CMPTHR_MASK                                    0x0000FFFFUL                       /**< Mask for CSEN_CMPTHR */
+#define _CSEN_CMPTHR_CMPTHR_SHIFT                            0                                  /**< Shift value for CSEN_CMPTHR */
+#define _CSEN_CMPTHR_CMPTHR_MASK                             0xFFFFUL                           /**< Bit mask for CSEN_CMPTHR */
+#define _CSEN_CMPTHR_CMPTHR_DEFAULT                          0x00000000UL                       /**< Mode DEFAULT for CSEN_CMPTHR */
+#define CSEN_CMPTHR_CMPTHR_DEFAULT                           (_CSEN_CMPTHR_CMPTHR_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_CMPTHR */
+
+/* Bit fields for CSEN EMA */
+#define _CSEN_EMA_RESETVALUE                                 0x00000000UL                 /**< Default value for CSEN_EMA */
+#define _CSEN_EMA_MASK                                       0x003FFFFFUL                 /**< Mask for CSEN_EMA */
+#define _CSEN_EMA_EMA_SHIFT                                  0                            /**< Shift value for CSEN_EMA */
+#define _CSEN_EMA_EMA_MASK                                   0x3FFFFFUL                   /**< Bit mask for CSEN_EMA */
+#define _CSEN_EMA_EMA_DEFAULT                                0x00000000UL                 /**< Mode DEFAULT for CSEN_EMA */
+#define CSEN_EMA_EMA_DEFAULT                                 (_CSEN_EMA_EMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_EMA */
+
+/* Bit fields for CSEN EMACTRL */
+#define _CSEN_EMACTRL_RESETVALUE                             0x00000000UL                           /**< Default value for CSEN_EMACTRL */
+#define _CSEN_EMACTRL_MASK                                   0x00000007UL                           /**< Mask for CSEN_EMACTRL */
+#define _CSEN_EMACTRL_EMASAMPLE_SHIFT                        0                                      /**< Shift value for CSEN_EMASAMPLE */
+#define _CSEN_EMACTRL_EMASAMPLE_MASK                         0x7UL                                  /**< Bit mask for CSEN_EMASAMPLE */
+#define _CSEN_EMACTRL_EMASAMPLE_DEFAULT                      0x00000000UL                           /**< Mode DEFAULT for CSEN_EMACTRL */
+#define _CSEN_EMACTRL_EMASAMPLE_W1                           0x00000000UL                           /**< Mode W1 for CSEN_EMACTRL */
+#define _CSEN_EMACTRL_EMASAMPLE_W2                           0x00000001UL                           /**< Mode W2 for CSEN_EMACTRL */
+#define _CSEN_EMACTRL_EMASAMPLE_W4                           0x00000002UL                           /**< Mode W4 for CSEN_EMACTRL */
+#define _CSEN_EMACTRL_EMASAMPLE_W8                           0x00000003UL                           /**< Mode W8 for CSEN_EMACTRL */
+#define _CSEN_EMACTRL_EMASAMPLE_W16                          0x00000004UL                           /**< Mode W16 for CSEN_EMACTRL */
+#define _CSEN_EMACTRL_EMASAMPLE_W32                          0x00000005UL                           /**< Mode W32 for CSEN_EMACTRL */
+#define _CSEN_EMACTRL_EMASAMPLE_W64                          0x00000006UL                           /**< Mode W64 for CSEN_EMACTRL */
+#define CSEN_EMACTRL_EMASAMPLE_DEFAULT                       (_CSEN_EMACTRL_EMASAMPLE_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_EMACTRL */
+#define CSEN_EMACTRL_EMASAMPLE_W1                            (_CSEN_EMACTRL_EMASAMPLE_W1 << 0)      /**< Shifted mode W1 for CSEN_EMACTRL */
+#define CSEN_EMACTRL_EMASAMPLE_W2                            (_CSEN_EMACTRL_EMASAMPLE_W2 << 0)      /**< Shifted mode W2 for CSEN_EMACTRL */
+#define CSEN_EMACTRL_EMASAMPLE_W4                            (_CSEN_EMACTRL_EMASAMPLE_W4 << 0)      /**< Shifted mode W4 for CSEN_EMACTRL */
+#define CSEN_EMACTRL_EMASAMPLE_W8                            (_CSEN_EMACTRL_EMASAMPLE_W8 << 0)      /**< Shifted mode W8 for CSEN_EMACTRL */
+#define CSEN_EMACTRL_EMASAMPLE_W16                           (_CSEN_EMACTRL_EMASAMPLE_W16 << 0)     /**< Shifted mode W16 for CSEN_EMACTRL */
+#define CSEN_EMACTRL_EMASAMPLE_W32                           (_CSEN_EMACTRL_EMASAMPLE_W32 << 0)     /**< Shifted mode W32 for CSEN_EMACTRL */
+#define CSEN_EMACTRL_EMASAMPLE_W64                           (_CSEN_EMACTRL_EMASAMPLE_W64 << 0)     /**< Shifted mode W64 for CSEN_EMACTRL */
+
+/* Bit fields for CSEN SINGLECTRL */
+#define _CSEN_SINGLECTRL_RESETVALUE                          0x00000000UL                                  /**< Default value for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_MASK                                0x000007F0UL                                  /**< Mask for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_SHIFT                     4                                             /**< Shift value for CSEN_SINGLESEL */
+#define _CSEN_SINGLECTRL_SINGLESEL_MASK                      0x7F0UL                                       /**< Bit mask for CSEN_SINGLESEL */
+#define _CSEN_SINGLECTRL_SINGLESEL_DEFAULT                   0x00000000UL                                  /**< Mode DEFAULT for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH0                0x00000020UL                                  /**< Mode APORT1XCH0 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH1                0x00000021UL                                  /**< Mode APORT1YCH1 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH2                0x00000022UL                                  /**< Mode APORT1XCH2 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH3                0x00000023UL                                  /**< Mode APORT1YCH3 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH4                0x00000024UL                                  /**< Mode APORT1XCH4 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH5                0x00000025UL                                  /**< Mode APORT1YCH5 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH6                0x00000026UL                                  /**< Mode APORT1XCH6 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH7                0x00000027UL                                  /**< Mode APORT1YCH7 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH8                0x00000028UL                                  /**< Mode APORT1XCH8 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH9                0x00000029UL                                  /**< Mode APORT1YCH9 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH10               0x0000002AUL                                  /**< Mode APORT1XCH10 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH11               0x0000002BUL                                  /**< Mode APORT1YCH11 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH12               0x0000002CUL                                  /**< Mode APORT1XCH12 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH13               0x0000002DUL                                  /**< Mode APORT1YCH13 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH14               0x0000002EUL                                  /**< Mode APORT1XCH14 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH15               0x0000002FUL                                  /**< Mode APORT1YCH15 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH16               0x00000030UL                                  /**< Mode APORT1XCH16 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH17               0x00000031UL                                  /**< Mode APORT1YCH17 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH18               0x00000032UL                                  /**< Mode APORT1XCH18 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH19               0x00000033UL                                  /**< Mode APORT1YCH19 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH20               0x00000034UL                                  /**< Mode APORT1XCH20 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH21               0x00000035UL                                  /**< Mode APORT1YCH21 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH22               0x00000036UL                                  /**< Mode APORT1XCH22 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH23               0x00000037UL                                  /**< Mode APORT1YCH23 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH24               0x00000038UL                                  /**< Mode APORT1XCH24 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH25               0x00000039UL                                  /**< Mode APORT1YCH25 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH26               0x0000003AUL                                  /**< Mode APORT1XCH26 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH27               0x0000003BUL                                  /**< Mode APORT1YCH27 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH28               0x0000003CUL                                  /**< Mode APORT1XCH28 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH29               0x0000003DUL                                  /**< Mode APORT1YCH29 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH30               0x0000003EUL                                  /**< Mode APORT1XCH30 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH31               0x0000003FUL                                  /**< Mode APORT1YCH31 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH0                0x00000060UL                                  /**< Mode APORT3XCH0 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH1                0x00000061UL                                  /**< Mode APORT3YCH1 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH2                0x00000062UL                                  /**< Mode APORT3XCH2 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH3                0x00000063UL                                  /**< Mode APORT3YCH3 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH4                0x00000064UL                                  /**< Mode APORT3XCH4 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH5                0x00000065UL                                  /**< Mode APORT3YCH5 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH6                0x00000066UL                                  /**< Mode APORT3XCH6 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH7                0x00000067UL                                  /**< Mode APORT3YCH7 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH8                0x00000068UL                                  /**< Mode APORT3XCH8 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH9                0x00000069UL                                  /**< Mode APORT3YCH9 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH10               0x0000006AUL                                  /**< Mode APORT3XCH10 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH11               0x0000006BUL                                  /**< Mode APORT3YCH11 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH12               0x0000006CUL                                  /**< Mode APORT3XCH12 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH13               0x0000006DUL                                  /**< Mode APORT3YCH13 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH14               0x0000006EUL                                  /**< Mode APORT3XCH14 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH15               0x0000006FUL                                  /**< Mode APORT3YCH15 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH16               0x00000070UL                                  /**< Mode APORT3XCH16 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH17               0x00000071UL                                  /**< Mode APORT3YCH17 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH18               0x00000072UL                                  /**< Mode APORT3XCH18 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH19               0x00000073UL                                  /**< Mode APORT3YCH19 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH20               0x00000074UL                                  /**< Mode APORT3XCH20 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH21               0x00000075UL                                  /**< Mode APORT3YCH21 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH22               0x00000076UL                                  /**< Mode APORT3XCH22 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH23               0x00000077UL                                  /**< Mode APORT3YCH23 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH24               0x00000078UL                                  /**< Mode APORT3XCH24 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH25               0x00000079UL                                  /**< Mode APORT3YCH25 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH26               0x0000007AUL                                  /**< Mode APORT3XCH26 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH27               0x0000007BUL                                  /**< Mode APORT3YCH27 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH28               0x0000007CUL                                  /**< Mode APORT3XCH28 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH29               0x0000007DUL                                  /**< Mode APORT3YCH29 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH30               0x0000007EUL                                  /**< Mode APORT3XCH30 for CSEN_SINGLECTRL */
+#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH31               0x0000007FUL                                  /**< Mode APORT3YCH31 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_DEFAULT                    (_CSEN_SINGLECTRL_SINGLESEL_DEFAULT << 4)     /**< Shifted mode DEFAULT for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH0                 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH0 << 4)  /**< Shifted mode APORT1XCH0 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH1                 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH1 << 4)  /**< Shifted mode APORT1YCH1 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH2                 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH2 << 4)  /**< Shifted mode APORT1XCH2 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH3                 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH3 << 4)  /**< Shifted mode APORT1YCH3 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH4                 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH4 << 4)  /**< Shifted mode APORT1XCH4 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH5                 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH5 << 4)  /**< Shifted mode APORT1YCH5 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH6                 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH6 << 4)  /**< Shifted mode APORT1XCH6 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH7                 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH7 << 4)  /**< Shifted mode APORT1YCH7 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH8                 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH8 << 4)  /**< Shifted mode APORT1XCH8 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH9                 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH9 << 4)  /**< Shifted mode APORT1YCH9 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH10                (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH10 << 4) /**< Shifted mode APORT1XCH10 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH11                (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH11 << 4) /**< Shifted mode APORT1YCH11 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH12                (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH12 << 4) /**< Shifted mode APORT1XCH12 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH13                (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH13 << 4) /**< Shifted mode APORT1YCH13 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH14                (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH14 << 4) /**< Shifted mode APORT1XCH14 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH15                (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH15 << 4) /**< Shifted mode APORT1YCH15 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH16                (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH16 << 4) /**< Shifted mode APORT1XCH16 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH17                (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH17 << 4) /**< Shifted mode APORT1YCH17 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH18                (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH18 << 4) /**< Shifted mode APORT1XCH18 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH19                (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH19 << 4) /**< Shifted mode APORT1YCH19 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH20                (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH20 << 4) /**< Shifted mode APORT1XCH20 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH21                (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH21 << 4) /**< Shifted mode APORT1YCH21 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH22                (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH22 << 4) /**< Shifted mode APORT1XCH22 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH23                (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH23 << 4) /**< Shifted mode APORT1YCH23 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH24                (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH24 << 4) /**< Shifted mode APORT1XCH24 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH25                (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH25 << 4) /**< Shifted mode APORT1YCH25 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH26                (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH26 << 4) /**< Shifted mode APORT1XCH26 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH27                (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH27 << 4) /**< Shifted mode APORT1YCH27 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH28                (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH28 << 4) /**< Shifted mode APORT1XCH28 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH29                (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH29 << 4) /**< Shifted mode APORT1YCH29 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH30                (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH30 << 4) /**< Shifted mode APORT1XCH30 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH31                (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH31 << 4) /**< Shifted mode APORT1YCH31 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH0                 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH0 << 4)  /**< Shifted mode APORT3XCH0 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH1                 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH1 << 4)  /**< Shifted mode APORT3YCH1 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH2                 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH2 << 4)  /**< Shifted mode APORT3XCH2 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH3                 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH3 << 4)  /**< Shifted mode APORT3YCH3 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH4                 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH4 << 4)  /**< Shifted mode APORT3XCH4 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH5                 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH5 << 4)  /**< Shifted mode APORT3YCH5 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH6                 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH6 << 4)  /**< Shifted mode APORT3XCH6 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH7                 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH7 << 4)  /**< Shifted mode APORT3YCH7 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH8                 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH8 << 4)  /**< Shifted mode APORT3XCH8 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH9                 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH9 << 4)  /**< Shifted mode APORT3YCH9 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH10                (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH10 << 4) /**< Shifted mode APORT3XCH10 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH11                (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH11 << 4) /**< Shifted mode APORT3YCH11 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH12                (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH12 << 4) /**< Shifted mode APORT3XCH12 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH13                (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH13 << 4) /**< Shifted mode APORT3YCH13 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH14                (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH14 << 4) /**< Shifted mode APORT3XCH14 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH15                (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH15 << 4) /**< Shifted mode APORT3YCH15 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH16                (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH16 << 4) /**< Shifted mode APORT3XCH16 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH17                (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH17 << 4) /**< Shifted mode APORT3YCH17 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH18                (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH18 << 4) /**< Shifted mode APORT3XCH18 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH19                (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH19 << 4) /**< Shifted mode APORT3YCH19 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH20                (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH20 << 4) /**< Shifted mode APORT3XCH20 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH21                (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH21 << 4) /**< Shifted mode APORT3YCH21 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH22                (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH22 << 4) /**< Shifted mode APORT3XCH22 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH23                (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH23 << 4) /**< Shifted mode APORT3YCH23 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH24                (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH24 << 4) /**< Shifted mode APORT3XCH24 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH25                (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH25 << 4) /**< Shifted mode APORT3YCH25 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH26                (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH26 << 4) /**< Shifted mode APORT3XCH26 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH27                (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH27 << 4) /**< Shifted mode APORT3YCH27 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH28                (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH28 << 4) /**< Shifted mode APORT3XCH28 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH29                (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH29 << 4) /**< Shifted mode APORT3YCH29 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH30                (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH30 << 4) /**< Shifted mode APORT3XCH30 for CSEN_SINGLECTRL */
+#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH31                (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH31 << 4) /**< Shifted mode APORT3YCH31 for CSEN_SINGLECTRL */
+
+/* Bit fields for CSEN DMBASELINE */
+#define _CSEN_DMBASELINE_RESETVALUE                          0x00000000UL                                /**< Default value for CSEN_DMBASELINE */
+#define _CSEN_DMBASELINE_MASK                                0xFFFFFFFFUL                                /**< Mask for CSEN_DMBASELINE */
+#define _CSEN_DMBASELINE_BASELINEUP_SHIFT                    0                                           /**< Shift value for CSEN_BASELINEUP */
+#define _CSEN_DMBASELINE_BASELINEUP_MASK                     0xFFFFUL                                    /**< Bit mask for CSEN_BASELINEUP */
+#define _CSEN_DMBASELINE_BASELINEUP_DEFAULT                  0x00000000UL                                /**< Mode DEFAULT for CSEN_DMBASELINE */
+#define CSEN_DMBASELINE_BASELINEUP_DEFAULT                   (_CSEN_DMBASELINE_BASELINEUP_DEFAULT << 0)  /**< Shifted mode DEFAULT for CSEN_DMBASELINE */
+#define _CSEN_DMBASELINE_BASELINEDN_SHIFT                    16                                          /**< Shift value for CSEN_BASELINEDN */
+#define _CSEN_DMBASELINE_BASELINEDN_MASK                     0xFFFF0000UL                                /**< Bit mask for CSEN_BASELINEDN */
+#define _CSEN_DMBASELINE_BASELINEDN_DEFAULT                  0x00000000UL                                /**< Mode DEFAULT for CSEN_DMBASELINE */
+#define CSEN_DMBASELINE_BASELINEDN_DEFAULT                   (_CSEN_DMBASELINE_BASELINEDN_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_DMBASELINE */
+
+/* Bit fields for CSEN DMCFG */
+#define _CSEN_DMCFG_RESETVALUE                               0x00000000UL                        /**< Default value for CSEN_DMCFG */
+#define _CSEN_DMCFG_MASK                                     0x103F0FFFUL                        /**< Mask for CSEN_DMCFG */
+#define _CSEN_DMCFG_DMG_SHIFT                                0                                   /**< Shift value for CSEN_DMG */
+#define _CSEN_DMCFG_DMG_MASK                                 0xFFUL                              /**< Bit mask for CSEN_DMG */
+#define _CSEN_DMCFG_DMG_DEFAULT                              0x00000000UL                        /**< Mode DEFAULT for CSEN_DMCFG */
+#define CSEN_DMCFG_DMG_DEFAULT                               (_CSEN_DMCFG_DMG_DEFAULT << 0)      /**< Shifted mode DEFAULT for CSEN_DMCFG */
+#define _CSEN_DMCFG_DMR_SHIFT                                8                                   /**< Shift value for CSEN_DMR */
+#define _CSEN_DMCFG_DMR_MASK                                 0xF00UL                             /**< Bit mask for CSEN_DMR */
+#define _CSEN_DMCFG_DMR_DEFAULT                              0x00000000UL                        /**< Mode DEFAULT for CSEN_DMCFG */
+#define CSEN_DMCFG_DMR_DEFAULT                               (_CSEN_DMCFG_DMR_DEFAULT << 8)      /**< Shifted mode DEFAULT for CSEN_DMCFG */
+#define _CSEN_DMCFG_DMCR_SHIFT                               16                                  /**< Shift value for CSEN_DMCR */
+#define _CSEN_DMCFG_DMCR_MASK                                0xF0000UL                           /**< Bit mask for CSEN_DMCR */
+#define _CSEN_DMCFG_DMCR_DEFAULT                             0x00000000UL                        /**< Mode DEFAULT for CSEN_DMCFG */
+#define CSEN_DMCFG_DMCR_DEFAULT                              (_CSEN_DMCFG_DMCR_DEFAULT << 16)    /**< Shifted mode DEFAULT for CSEN_DMCFG */
+#define _CSEN_DMCFG_CRMODE_SHIFT                             20                                  /**< Shift value for CSEN_CRMODE */
+#define _CSEN_DMCFG_CRMODE_MASK                              0x300000UL                          /**< Bit mask for CSEN_CRMODE */
+#define _CSEN_DMCFG_CRMODE_DEFAULT                           0x00000000UL                        /**< Mode DEFAULT for CSEN_DMCFG */
+#define _CSEN_DMCFG_CRMODE_DM10                              0x00000000UL                        /**< Mode DM10 for CSEN_DMCFG */
+#define _CSEN_DMCFG_CRMODE_DM12                              0x00000001UL                        /**< Mode DM12 for CSEN_DMCFG */
+#define _CSEN_DMCFG_CRMODE_DM14                              0x00000002UL                        /**< Mode DM14 for CSEN_DMCFG */
+#define _CSEN_DMCFG_CRMODE_DM16                              0x00000003UL                        /**< Mode DM16 for CSEN_DMCFG */
+#define CSEN_DMCFG_CRMODE_DEFAULT                            (_CSEN_DMCFG_CRMODE_DEFAULT << 20)  /**< Shifted mode DEFAULT for CSEN_DMCFG */
+#define CSEN_DMCFG_CRMODE_DM10                               (_CSEN_DMCFG_CRMODE_DM10 << 20)     /**< Shifted mode DM10 for CSEN_DMCFG */
+#define CSEN_DMCFG_CRMODE_DM12                               (_CSEN_DMCFG_CRMODE_DM12 << 20)     /**< Shifted mode DM12 for CSEN_DMCFG */
+#define CSEN_DMCFG_CRMODE_DM14                               (_CSEN_DMCFG_CRMODE_DM14 << 20)     /**< Shifted mode DM14 for CSEN_DMCFG */
+#define CSEN_DMCFG_CRMODE_DM16                               (_CSEN_DMCFG_CRMODE_DM16 << 20)     /**< Shifted mode DM16 for CSEN_DMCFG */
+#define CSEN_DMCFG_DMGRDIS                                   (0x1UL << 28)                       /**< Delta Modulation Gain Step Reduction Disable */
+#define _CSEN_DMCFG_DMGRDIS_SHIFT                            28                                  /**< Shift value for CSEN_DMGRDIS */
+#define _CSEN_DMCFG_DMGRDIS_MASK                             0x10000000UL                        /**< Bit mask for CSEN_DMGRDIS */
+#define _CSEN_DMCFG_DMGRDIS_DEFAULT                          0x00000000UL                        /**< Mode DEFAULT for CSEN_DMCFG */
+#define CSEN_DMCFG_DMGRDIS_DEFAULT                           (_CSEN_DMCFG_DMGRDIS_DEFAULT << 28) /**< Shifted mode DEFAULT for CSEN_DMCFG */
+
+/* Bit fields for CSEN ANACTRL */
+#define _CSEN_ANACTRL_RESETVALUE                             0x00000070UL                           /**< Default value for CSEN_ANACTRL */
+#define _CSEN_ANACTRL_MASK                                   0x00700770UL                           /**< Mask for CSEN_ANACTRL */
+#define _CSEN_ANACTRL_IREFPROG_SHIFT                         4                                      /**< Shift value for CSEN_IREFPROG */
+#define _CSEN_ANACTRL_IREFPROG_MASK                          0x70UL                                 /**< Bit mask for CSEN_IREFPROG */
+#define _CSEN_ANACTRL_IREFPROG_DEFAULT                       0x00000007UL                           /**< Mode DEFAULT for CSEN_ANACTRL */
+#define CSEN_ANACTRL_IREFPROG_DEFAULT                        (_CSEN_ANACTRL_IREFPROG_DEFAULT << 4)  /**< Shifted mode DEFAULT for CSEN_ANACTRL */
+#define _CSEN_ANACTRL_IDACIREFS_SHIFT                        8                                      /**< Shift value for CSEN_IDACIREFS */
+#define _CSEN_ANACTRL_IDACIREFS_MASK                         0x700UL                                /**< Bit mask for CSEN_IDACIREFS */
+#define _CSEN_ANACTRL_IDACIREFS_DEFAULT                      0x00000000UL                           /**< Mode DEFAULT for CSEN_ANACTRL */
+#define CSEN_ANACTRL_IDACIREFS_DEFAULT                       (_CSEN_ANACTRL_IDACIREFS_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_ANACTRL */
+#define _CSEN_ANACTRL_TRSTPROG_SHIFT                         20                                     /**< Shift value for CSEN_TRSTPROG */
+#define _CSEN_ANACTRL_TRSTPROG_MASK                          0x700000UL                             /**< Bit mask for CSEN_TRSTPROG */
+#define _CSEN_ANACTRL_TRSTPROG_DEFAULT                       0x00000000UL                           /**< Mode DEFAULT for CSEN_ANACTRL */
+#define CSEN_ANACTRL_TRSTPROG_DEFAULT                        (_CSEN_ANACTRL_TRSTPROG_DEFAULT << 20) /**< Shifted mode DEFAULT for CSEN_ANACTRL */
+
+/* Bit fields for CSEN IF */
+#define _CSEN_IF_RESETVALUE                                  0x00000000UL                          /**< Default value for CSEN_IF */
+#define _CSEN_IF_MASK                                        0x0000001FUL                          /**< Mask for CSEN_IF */
+#define CSEN_IF_CMP                                          (0x1UL << 0)                          /**< Digital Comparator Interrupt Flag */
+#define _CSEN_IF_CMP_SHIFT                                   0                                     /**< Shift value for CSEN_CMP */
+#define _CSEN_IF_CMP_MASK                                    0x1UL                                 /**< Bit mask for CSEN_CMP */
+#define _CSEN_IF_CMP_DEFAULT                                 0x00000000UL                          /**< Mode DEFAULT for CSEN_IF */
+#define CSEN_IF_CMP_DEFAULT                                  (_CSEN_IF_CMP_DEFAULT << 0)           /**< Shifted mode DEFAULT for CSEN_IF */
+#define CSEN_IF_CONV                                         (0x1UL << 1)                          /**< Conversion Done Interrupt Flag */
+#define _CSEN_IF_CONV_SHIFT                                  1                                     /**< Shift value for CSEN_CONV */
+#define _CSEN_IF_CONV_MASK                                   0x2UL                                 /**< Bit mask for CSEN_CONV */
+#define _CSEN_IF_CONV_DEFAULT                                0x00000000UL                          /**< Mode DEFAULT for CSEN_IF */
+#define CSEN_IF_CONV_DEFAULT                                 (_CSEN_IF_CONV_DEFAULT << 1)          /**< Shifted mode DEFAULT for CSEN_IF */
+#define CSEN_IF_EOS                                          (0x1UL << 2)                          /**< End of Scan Interrupt Flag. */
+#define _CSEN_IF_EOS_SHIFT                                   2                                     /**< Shift value for CSEN_EOS */
+#define _CSEN_IF_EOS_MASK                                    0x4UL                                 /**< Bit mask for CSEN_EOS */
+#define _CSEN_IF_EOS_DEFAULT                                 0x00000000UL                          /**< Mode DEFAULT for CSEN_IF */
+#define CSEN_IF_EOS_DEFAULT                                  (_CSEN_IF_EOS_DEFAULT << 2)           /**< Shifted mode DEFAULT for CSEN_IF */
+#define CSEN_IF_DMAOF                                        (0x1UL << 3)                          /**< DMA Overflow Interrupt Flag. */
+#define _CSEN_IF_DMAOF_SHIFT                                 3                                     /**< Shift value for CSEN_DMAOF */
+#define _CSEN_IF_DMAOF_MASK                                  0x8UL                                 /**< Bit mask for CSEN_DMAOF */
+#define _CSEN_IF_DMAOF_DEFAULT                               0x00000000UL                          /**< Mode DEFAULT for CSEN_IF */
+#define CSEN_IF_DMAOF_DEFAULT                                (_CSEN_IF_DMAOF_DEFAULT << 3)         /**< Shifted mode DEFAULT for CSEN_IF */
+#define CSEN_IF_APORTCONFLICT                                (0x1UL << 4)                          /**< APORT Conflict Interrupt Flag */
+#define _CSEN_IF_APORTCONFLICT_SHIFT                         4                                     /**< Shift value for CSEN_APORTCONFLICT */
+#define _CSEN_IF_APORTCONFLICT_MASK                          0x10UL                                /**< Bit mask for CSEN_APORTCONFLICT */
+#define _CSEN_IF_APORTCONFLICT_DEFAULT                       0x00000000UL                          /**< Mode DEFAULT for CSEN_IF */
+#define CSEN_IF_APORTCONFLICT_DEFAULT                        (_CSEN_IF_APORTCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_IF */
+
+/* Bit fields for CSEN IFS */
+#define _CSEN_IFS_RESETVALUE                                 0x00000000UL                           /**< Default value for CSEN_IFS */
+#define _CSEN_IFS_MASK                                       0x0000001FUL                           /**< Mask for CSEN_IFS */
+#define CSEN_IFS_CMP                                         (0x1UL << 0)                           /**< Set CMP Interrupt Flag */
+#define _CSEN_IFS_CMP_SHIFT                                  0                                      /**< Shift value for CSEN_CMP */
+#define _CSEN_IFS_CMP_MASK                                   0x1UL                                  /**< Bit mask for CSEN_CMP */
+#define _CSEN_IFS_CMP_DEFAULT                                0x00000000UL                           /**< Mode DEFAULT for CSEN_IFS */
+#define CSEN_IFS_CMP_DEFAULT                                 (_CSEN_IFS_CMP_DEFAULT << 0)           /**< Shifted mode DEFAULT for CSEN_IFS */
+#define CSEN_IFS_CONV                                        (0x1UL << 1)                           /**< Set CONV Interrupt Flag */
+#define _CSEN_IFS_CONV_SHIFT                                 1                                      /**< Shift value for CSEN_CONV */
+#define _CSEN_IFS_CONV_MASK                                  0x2UL                                  /**< Bit mask for CSEN_CONV */
+#define _CSEN_IFS_CONV_DEFAULT                               0x00000000UL                           /**< Mode DEFAULT for CSEN_IFS */
+#define CSEN_IFS_CONV_DEFAULT                                (_CSEN_IFS_CONV_DEFAULT << 1)          /**< Shifted mode DEFAULT for CSEN_IFS */
+#define CSEN_IFS_EOS                                         (0x1UL << 2)                           /**< Set EOS Interrupt Flag */
+#define _CSEN_IFS_EOS_SHIFT                                  2                                      /**< Shift value for CSEN_EOS */
+#define _CSEN_IFS_EOS_MASK                                   0x4UL                                  /**< Bit mask for CSEN_EOS */
+#define _CSEN_IFS_EOS_DEFAULT                                0x00000000UL                           /**< Mode DEFAULT for CSEN_IFS */
+#define CSEN_IFS_EOS_DEFAULT                                 (_CSEN_IFS_EOS_DEFAULT << 2)           /**< Shifted mode DEFAULT for CSEN_IFS */
+#define CSEN_IFS_DMAOF                                       (0x1UL << 3)                           /**< Set DMAOF Interrupt Flag */
+#define _CSEN_IFS_DMAOF_SHIFT                                3                                      /**< Shift value for CSEN_DMAOF */
+#define _CSEN_IFS_DMAOF_MASK                                 0x8UL                                  /**< Bit mask for CSEN_DMAOF */
+#define _CSEN_IFS_DMAOF_DEFAULT                              0x00000000UL                           /**< Mode DEFAULT for CSEN_IFS */
+#define CSEN_IFS_DMAOF_DEFAULT                               (_CSEN_IFS_DMAOF_DEFAULT << 3)         /**< Shifted mode DEFAULT for CSEN_IFS */
+#define CSEN_IFS_APORTCONFLICT                               (0x1UL << 4)                           /**< Set APORTCONFLICT Interrupt Flag */
+#define _CSEN_IFS_APORTCONFLICT_SHIFT                        4                                      /**< Shift value for CSEN_APORTCONFLICT */
+#define _CSEN_IFS_APORTCONFLICT_MASK                         0x10UL                                 /**< Bit mask for CSEN_APORTCONFLICT */
+#define _CSEN_IFS_APORTCONFLICT_DEFAULT                      0x00000000UL                           /**< Mode DEFAULT for CSEN_IFS */
+#define CSEN_IFS_APORTCONFLICT_DEFAULT                       (_CSEN_IFS_APORTCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_IFS */
+
+/* Bit fields for CSEN IFC */
+#define _CSEN_IFC_RESETVALUE                                 0x00000000UL                           /**< Default value for CSEN_IFC */
+#define _CSEN_IFC_MASK                                       0x0000001FUL                           /**< Mask for CSEN_IFC */
+#define CSEN_IFC_CMP                                         (0x1UL << 0)                           /**< Clear CMP Interrupt Flag */
+#define _CSEN_IFC_CMP_SHIFT                                  0                                      /**< Shift value for CSEN_CMP */
+#define _CSEN_IFC_CMP_MASK                                   0x1UL                                  /**< Bit mask for CSEN_CMP */
+#define _CSEN_IFC_CMP_DEFAULT                                0x00000000UL                           /**< Mode DEFAULT for CSEN_IFC */
+#define CSEN_IFC_CMP_DEFAULT                                 (_CSEN_IFC_CMP_DEFAULT << 0)           /**< Shifted mode DEFAULT for CSEN_IFC */
+#define CSEN_IFC_CONV                                        (0x1UL << 1)                           /**< Clear CONV Interrupt Flag */
+#define _CSEN_IFC_CONV_SHIFT                                 1                                      /**< Shift value for CSEN_CONV */
+#define _CSEN_IFC_CONV_MASK                                  0x2UL                                  /**< Bit mask for CSEN_CONV */
+#define _CSEN_IFC_CONV_DEFAULT                               0x00000000UL                           /**< Mode DEFAULT for CSEN_IFC */
+#define CSEN_IFC_CONV_DEFAULT                                (_CSEN_IFC_CONV_DEFAULT << 1)          /**< Shifted mode DEFAULT for CSEN_IFC */
+#define CSEN_IFC_EOS                                         (0x1UL << 2)                           /**< Clear EOS Interrupt Flag */
+#define _CSEN_IFC_EOS_SHIFT                                  2                                      /**< Shift value for CSEN_EOS */
+#define _CSEN_IFC_EOS_MASK                                   0x4UL                                  /**< Bit mask for CSEN_EOS */
+#define _CSEN_IFC_EOS_DEFAULT                                0x00000000UL                           /**< Mode DEFAULT for CSEN_IFC */
+#define CSEN_IFC_EOS_DEFAULT                                 (_CSEN_IFC_EOS_DEFAULT << 2)           /**< Shifted mode DEFAULT for CSEN_IFC */
+#define CSEN_IFC_DMAOF                                       (0x1UL << 3)                           /**< Clear DMAOF Interrupt Flag */
+#define _CSEN_IFC_DMAOF_SHIFT                                3                                      /**< Shift value for CSEN_DMAOF */
+#define _CSEN_IFC_DMAOF_MASK                                 0x8UL                                  /**< Bit mask for CSEN_DMAOF */
+#define _CSEN_IFC_DMAOF_DEFAULT                              0x00000000UL                           /**< Mode DEFAULT for CSEN_IFC */
+#define CSEN_IFC_DMAOF_DEFAULT                               (_CSEN_IFC_DMAOF_DEFAULT << 3)         /**< Shifted mode DEFAULT for CSEN_IFC */
+#define CSEN_IFC_APORTCONFLICT                               (0x1UL << 4)                           /**< Clear APORTCONFLICT Interrupt Flag */
+#define _CSEN_IFC_APORTCONFLICT_SHIFT                        4                                      /**< Shift value for CSEN_APORTCONFLICT */
+#define _CSEN_IFC_APORTCONFLICT_MASK                         0x10UL                                 /**< Bit mask for CSEN_APORTCONFLICT */
+#define _CSEN_IFC_APORTCONFLICT_DEFAULT                      0x00000000UL                           /**< Mode DEFAULT for CSEN_IFC */
+#define CSEN_IFC_APORTCONFLICT_DEFAULT                       (_CSEN_IFC_APORTCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_IFC */
+
+/* Bit fields for CSEN IEN */
+#define _CSEN_IEN_RESETVALUE                                 0x00000000UL                           /**< Default value for CSEN_IEN */
+#define _CSEN_IEN_MASK                                       0x0000001FUL                           /**< Mask for CSEN_IEN */
+#define CSEN_IEN_CMP                                         (0x1UL << 0)                           /**< CMP Interrupt Enable */
+#define _CSEN_IEN_CMP_SHIFT                                  0                                      /**< Shift value for CSEN_CMP */
+#define _CSEN_IEN_CMP_MASK                                   0x1UL                                  /**< Bit mask for CSEN_CMP */
+#define _CSEN_IEN_CMP_DEFAULT                                0x00000000UL                           /**< Mode DEFAULT for CSEN_IEN */
+#define CSEN_IEN_CMP_DEFAULT                                 (_CSEN_IEN_CMP_DEFAULT << 0)           /**< Shifted mode DEFAULT for CSEN_IEN */
+#define CSEN_IEN_CONV                                        (0x1UL << 1)                           /**< CONV Interrupt Enable */
+#define _CSEN_IEN_CONV_SHIFT                                 1                                      /**< Shift value for CSEN_CONV */
+#define _CSEN_IEN_CONV_MASK                                  0x2UL                                  /**< Bit mask for CSEN_CONV */
+#define _CSEN_IEN_CONV_DEFAULT                               0x00000000UL                           /**< Mode DEFAULT for CSEN_IEN */
+#define CSEN_IEN_CONV_DEFAULT                                (_CSEN_IEN_CONV_DEFAULT << 1)          /**< Shifted mode DEFAULT for CSEN_IEN */
+#define CSEN_IEN_EOS                                         (0x1UL << 2)                           /**< EOS Interrupt Enable */
+#define _CSEN_IEN_EOS_SHIFT                                  2                                      /**< Shift value for CSEN_EOS */
+#define _CSEN_IEN_EOS_MASK                                   0x4UL                                  /**< Bit mask for CSEN_EOS */
+#define _CSEN_IEN_EOS_DEFAULT                                0x00000000UL                           /**< Mode DEFAULT for CSEN_IEN */
+#define CSEN_IEN_EOS_DEFAULT                                 (_CSEN_IEN_EOS_DEFAULT << 2)           /**< Shifted mode DEFAULT for CSEN_IEN */
+#define CSEN_IEN_DMAOF                                       (0x1UL << 3)                           /**< DMAOF Interrupt Enable */
+#define _CSEN_IEN_DMAOF_SHIFT                                3                                      /**< Shift value for CSEN_DMAOF */
+#define _CSEN_IEN_DMAOF_MASK                                 0x8UL                                  /**< Bit mask for CSEN_DMAOF */
+#define _CSEN_IEN_DMAOF_DEFAULT                              0x00000000UL                           /**< Mode DEFAULT for CSEN_IEN */
+#define CSEN_IEN_DMAOF_DEFAULT                               (_CSEN_IEN_DMAOF_DEFAULT << 3)         /**< Shifted mode DEFAULT for CSEN_IEN */
+#define CSEN_IEN_APORTCONFLICT                               (0x1UL << 4)                           /**< APORTCONFLICT Interrupt Enable */
+#define _CSEN_IEN_APORTCONFLICT_SHIFT                        4                                      /**< Shift value for CSEN_APORTCONFLICT */
+#define _CSEN_IEN_APORTCONFLICT_MASK                         0x10UL                                 /**< Bit mask for CSEN_APORTCONFLICT */
+#define _CSEN_IEN_APORTCONFLICT_DEFAULT                      0x00000000UL                           /**< Mode DEFAULT for CSEN_IEN */
+#define CSEN_IEN_APORTCONFLICT_DEFAULT                       (_CSEN_IEN_APORTCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_IEN */
+
+/** @} */
+/** @} End of group EFM32GG12B_CSEN */
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+

cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b_dma_descriptor.h

@@ -0,0 +1,64 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32GG12B_DMA_DESCRIPTOR register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFM32GG12B_DMA_DESCRIPTOR DMA Descriptor
+ * @{
+ ******************************************************************************/
+/** DMA_DESCRIPTOR Register Declaration */
+typedef struct {
+  /* Note! Use of double __IOM (volatile) qualifier to ensure that both */
+  /* pointer and referenced memory are declared volatile. */
+  __IOM uint32_t     CTRL;     /**< DMA control register */
+  __IOM void * __IOM SRC;      /**< DMA source address */
+  __IOM void * __IOM DST;      /**< DMA destination address */
+  __IOM void * __IOM LINK;     /**< DMA link address */
+} DMA_DESCRIPTOR_TypeDef;      /**< @} */
+
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+

cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b_dmareq.h

@@ -0,0 +1,147 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32GG12B_DMAREQ register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @addtogroup EFM32GG12B_DMAREQ DMAREQ
+ * @{
+ * @defgroup EFM32GG12B_DMAREQ_BitFields DMAREQ Bit Fields
+ * @{
+ ******************************************************************************/
+#define DMAREQ_PRS_REQ0               ((1 << 16) + 0)  /**< DMA channel select for PRS_REQ0 */
+#define DMAREQ_PRS_REQ1               ((1 << 16) + 1)  /**< DMA channel select for PRS_REQ1 */
+#define DMAREQ_ADC0_SINGLE            ((8 << 16) + 0)  /**< DMA channel select for ADC0_SINGLE */
+#define DMAREQ_ADC0_SCAN              ((8 << 16) + 1)  /**< DMA channel select for ADC0_SCAN */
+#define DMAREQ_ADC1_SINGLE            ((9 << 16) + 0)  /**< DMA channel select for ADC1_SINGLE */
+#define DMAREQ_ADC1_SCAN              ((9 << 16) + 1)  /**< DMA channel select for ADC1_SCAN */
+#define DMAREQ_VDAC0_CH0              ((10 << 16) + 0) /**< DMA channel select for VDAC0_CH0 */
+#define DMAREQ_VDAC0_CH1              ((10 << 16) + 1) /**< DMA channel select for VDAC0_CH1 */
+#define DMAREQ_USART0_RXDATAV         ((12 << 16) + 0) /**< DMA channel select for USART0_RXDATAV */
+#define DMAREQ_USART0_TXBL            ((12 << 16) + 1) /**< DMA channel select for USART0_TXBL */
+#define DMAREQ_USART0_TXEMPTY         ((12 << 16) + 2) /**< DMA channel select for USART0_TXEMPTY */
+#define DMAREQ_USART1_RXDATAV         ((13 << 16) + 0) /**< DMA channel select for USART1_RXDATAV */
+#define DMAREQ_USART1_TXBL            ((13 << 16) + 1) /**< DMA channel select for USART1_TXBL */
+#define DMAREQ_USART1_TXEMPTY         ((13 << 16) + 2) /**< DMA channel select for USART1_TXEMPTY */
+#define DMAREQ_USART1_RXDATAVRIGHT    ((13 << 16) + 3) /**< DMA channel select for USART1_RXDATAVRIGHT */
+#define DMAREQ_USART1_TXBLRIGHT       ((13 << 16) + 4) /**< DMA channel select for USART1_TXBLRIGHT */
+#define DMAREQ_USART2_RXDATAV         ((14 << 16) + 0) /**< DMA channel select for USART2_RXDATAV */
+#define DMAREQ_USART2_TXBL            ((14 << 16) + 1) /**< DMA channel select for USART2_TXBL */
+#define DMAREQ_USART2_TXEMPTY         ((14 << 16) + 2) /**< DMA channel select for USART2_TXEMPTY */
+#define DMAREQ_USART3_RXDATAV         ((15 << 16) + 0) /**< DMA channel select for USART3_RXDATAV */
+#define DMAREQ_USART3_TXBL            ((15 << 16) + 1) /**< DMA channel select for USART3_TXBL */
+#define DMAREQ_USART3_TXEMPTY         ((15 << 16) + 2) /**< DMA channel select for USART3_TXEMPTY */
+#define DMAREQ_USART3_RXDATAVRIGHT    ((15 << 16) + 3) /**< DMA channel select for USART3_RXDATAVRIGHT */
+#define DMAREQ_USART3_TXBLRIGHT       ((15 << 16) + 4) /**< DMA channel select for USART3_TXBLRIGHT */
+#define DMAREQ_USART4_RXDATAV         ((16 << 16) + 0) /**< DMA channel select for USART4_RXDATAV */
+#define DMAREQ_USART4_TXBL            ((16 << 16) + 1) /**< DMA channel select for USART4_TXBL */
+#define DMAREQ_USART4_TXEMPTY         ((16 << 16) + 2) /**< DMA channel select for USART4_TXEMPTY */
+#define DMAREQ_USART4_RXDATAVRIGHT    ((16 << 16) + 3) /**< DMA channel select for USART4_RXDATAVRIGHT */
+#define DMAREQ_USART4_TXBLRIGHT       ((16 << 16) + 4) /**< DMA channel select for USART4_TXBLRIGHT */
+#define DMAREQ_UART0_RXDATAV          ((18 << 16) + 0) /**< DMA channel select for UART0_RXDATAV */
+#define DMAREQ_UART0_TXBL             ((18 << 16) + 1) /**< DMA channel select for UART0_TXBL */
+#define DMAREQ_UART0_TXEMPTY          ((18 << 16) + 2) /**< DMA channel select for UART0_TXEMPTY */
+#define DMAREQ_UART1_RXDATAV          ((19 << 16) + 0) /**< DMA channel select for UART1_RXDATAV */
+#define DMAREQ_UART1_TXBL             ((19 << 16) + 1) /**< DMA channel select for UART1_TXBL */
+#define DMAREQ_UART1_TXEMPTY          ((19 << 16) + 2) /**< DMA channel select for UART1_TXEMPTY */
+#define DMAREQ_LEUART0_RXDATAV        ((20 << 16) + 0) /**< DMA channel select for LEUART0_RXDATAV */
+#define DMAREQ_LEUART0_TXBL           ((20 << 16) + 1) /**< DMA channel select for LEUART0_TXBL */
+#define DMAREQ_LEUART0_TXEMPTY        ((20 << 16) + 2) /**< DMA channel select for LEUART0_TXEMPTY */
+#define DMAREQ_LEUART1_RXDATAV        ((21 << 16) + 0) /**< DMA channel select for LEUART1_RXDATAV */
+#define DMAREQ_LEUART1_TXBL           ((21 << 16) + 1) /**< DMA channel select for LEUART1_TXBL */
+#define DMAREQ_LEUART1_TXEMPTY        ((21 << 16) + 2) /**< DMA channel select for LEUART1_TXEMPTY */
+#define DMAREQ_I2C0_RXDATAV           ((22 << 16) + 0) /**< DMA channel select for I2C0_RXDATAV */
+#define DMAREQ_I2C0_TXBL              ((22 << 16) + 1) /**< DMA channel select for I2C0_TXBL */
+#define DMAREQ_I2C1_RXDATAV           ((23 << 16) + 0) /**< DMA channel select for I2C1_RXDATAV */
+#define DMAREQ_I2C1_TXBL              ((23 << 16) + 1) /**< DMA channel select for I2C1_TXBL */
+#define DMAREQ_TIMER0_UFOF            ((25 << 16) + 0) /**< DMA channel select for TIMER0_UFOF */
+#define DMAREQ_TIMER0_CC0             ((25 << 16) + 1) /**< DMA channel select for TIMER0_CC0 */
+#define DMAREQ_TIMER0_CC1             ((25 << 16) + 2) /**< DMA channel select for TIMER0_CC1 */
+#define DMAREQ_TIMER0_CC2             ((25 << 16) + 3) /**< DMA channel select for TIMER0_CC2 */
+#define DMAREQ_TIMER1_UFOF            ((26 << 16) + 0) /**< DMA channel select for TIMER1_UFOF */
+#define DMAREQ_TIMER1_CC0             ((26 << 16) + 1) /**< DMA channel select for TIMER1_CC0 */
+#define DMAREQ_TIMER1_CC1             ((26 << 16) + 2) /**< DMA channel select for TIMER1_CC1 */
+#define DMAREQ_TIMER1_CC2             ((26 << 16) + 3) /**< DMA channel select for TIMER1_CC2 */
+#define DMAREQ_TIMER1_CC3             ((26 << 16) + 4) /**< DMA channel select for TIMER1_CC3 */
+#define DMAREQ_TIMER2_UFOF            ((27 << 16) + 0) /**< DMA channel select for TIMER2_UFOF */
+#define DMAREQ_TIMER2_CC0             ((27 << 16) + 1) /**< DMA channel select for TIMER2_CC0 */
+#define DMAREQ_TIMER2_CC1             ((27 << 16) + 2) /**< DMA channel select for TIMER2_CC1 */
+#define DMAREQ_TIMER2_CC2             ((27 << 16) + 3) /**< DMA channel select for TIMER2_CC2 */
+#define DMAREQ_TIMER3_UFOF            ((28 << 16) + 0) /**< DMA channel select for TIMER3_UFOF */
+#define DMAREQ_TIMER3_CC0             ((28 << 16) + 1) /**< DMA channel select for TIMER3_CC0 */
+#define DMAREQ_TIMER3_CC1             ((28 << 16) + 2) /**< DMA channel select for TIMER3_CC1 */
+#define DMAREQ_TIMER3_CC2             ((28 << 16) + 3) /**< DMA channel select for TIMER3_CC2 */
+#define DMAREQ_WTIMER0_UFOF           ((32 << 16) + 0) /**< DMA channel select for WTIMER0_UFOF */
+#define DMAREQ_WTIMER0_CC0            ((32 << 16) + 1) /**< DMA channel select for WTIMER0_CC0 */
+#define DMAREQ_WTIMER0_CC1            ((32 << 16) + 2) /**< DMA channel select for WTIMER0_CC1 */
+#define DMAREQ_WTIMER0_CC2            ((32 << 16) + 3) /**< DMA channel select for WTIMER0_CC2 */
+#define DMAREQ_WTIMER1_UFOF           ((33 << 16) + 0) /**< DMA channel select for WTIMER1_UFOF */
+#define DMAREQ_WTIMER1_CC0            ((33 << 16) + 1) /**< DMA channel select for WTIMER1_CC0 */
+#define DMAREQ_WTIMER1_CC1            ((33 << 16) + 2) /**< DMA channel select for WTIMER1_CC1 */
+#define DMAREQ_WTIMER1_CC2            ((33 << 16) + 3) /**< DMA channel select for WTIMER1_CC2 */
+#define DMAREQ_WTIMER1_CC3            ((33 << 16) + 4) /**< DMA channel select for WTIMER1_CC3 */
+#define DMAREQ_MSC_WDATA              ((48 << 16) + 0) /**< DMA channel select for MSC_WDATA */
+#define DMAREQ_CRYPTO0_DATA0WR        ((49 << 16) + 0) /**< DMA channel select for CRYPTO0_DATA0WR */
+#define DMAREQ_CRYPTO0_DATA0XWR       ((49 << 16) + 1) /**< DMA channel select for CRYPTO0_DATA0XWR */
+#define DMAREQ_CRYPTO0_DATA0RD        ((49 << 16) + 2) /**< DMA channel select for CRYPTO0_DATA0RD */
+#define DMAREQ_CRYPTO0_DATA1WR        ((49 << 16) + 3) /**< DMA channel select for CRYPTO0_DATA1WR */
+#define DMAREQ_CRYPTO0_DATA1RD        ((49 << 16) + 4) /**< DMA channel select for CRYPTO0_DATA1RD */
+#define DMAREQ_EBI_PXL0EMPTY          ((50 << 16) + 0) /**< DMA channel select for EBI_PXL0EMPTY */
+#define DMAREQ_EBI_PXL1EMPTY          ((50 << 16) + 1) /**< DMA channel select for EBI_PXL1EMPTY */
+#define DMAREQ_EBI_PXLFULL            ((50 << 16) + 2) /**< DMA channel select for EBI_PXLFULL */
+#define DMAREQ_EBI_DDEMPTY            ((50 << 16) + 3) /**< DMA channel select for EBI_DDEMPTY */
+#define DMAREQ_EBI_VSYNC              ((50 << 16) + 4) /**< DMA channel select for EBI_VSYNC */
+#define DMAREQ_EBI_HSYNC              ((50 << 16) + 5) /**< DMA channel select for EBI_HSYNC */
+#define DMAREQ_PDM_RXDATAV            ((51 << 16) + 0) /**< DMA channel select for PDM_RXDATAV */
+#define DMAREQ_CSEN_DATA              ((61 << 16) + 0) /**< DMA channel select for CSEN_DATA */
+#define DMAREQ_CSEN_BSLN              ((61 << 16) + 1) /**< DMA channel select for CSEN_BSLN */
+#define DMAREQ_LESENSE_BUFDATAV       ((62 << 16) + 0) /**< DMA channel select for LESENSE_BUFDATAV */
+
+/** @} */
+/** @} End of group EFM32GG12B_DMAREQ */
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+

cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b_etm.h

@@ -0,0 +1,797 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32GG12B_ETM register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFM32GG12B_ETM ETM
+ * @{
+ * @brief EFM32GG12B_ETM Register Declaration
+ ******************************************************************************/
+/** ETM Register Declaration */
+typedef struct {
+  __IOM uint32_t ETMCR;            /**< Main Control Register  */
+  __IM uint32_t  ETMCCR;           /**< Configuration Code Register  */
+  __IOM uint32_t ETMTRIGGER;       /**< ETM Trigger Event Register  */
+  uint32_t       RESERVED0[1U];    /**< Reserved for future use **/
+  __IOM uint32_t ETMSR;            /**< ETM Status Register  */
+  __IM uint32_t  ETMSCR;           /**< ETM System Configuration Register  */
+  uint32_t       RESERVED1[2U];    /**< Reserved for future use **/
+  __IOM uint32_t ETMTEEVR;         /**< ETM TraceEnable Event Register  */
+  __IOM uint32_t ETMTECR1;         /**< ETM Trace control Register  */
+  uint32_t       RESERVED2[1U];    /**< Reserved for future use **/
+  __IOM uint32_t ETMFFLR;          /**< ETM Fifo Full Level Register  */
+  uint32_t       RESERVED3[68U];   /**< Reserved for future use **/
+  __IOM uint32_t ETMCNTRLDVR1;     /**< Counter Reload Value  */
+  uint32_t       RESERVED4[39U];   /**< Reserved for future use **/
+  __IOM uint32_t ETMSYNCFR;        /**< Synchronisation Frequency Register  */
+  __IM uint32_t  ETMIDR;           /**< ID Register  */
+  __IM uint32_t  ETMCCER;          /**< Configuration Code Extension Register  */
+  uint32_t       RESERVED5[1U];    /**< Reserved for future use **/
+  __IOM uint32_t ETMTESSEICR;      /**< TraceEnable Start/Stop EmbeddedICE Control Register  */
+  uint32_t       RESERVED6[1U];    /**< Reserved for future use **/
+  __IOM uint32_t ETMTSEVR;         /**< Timestamp Event Register  */
+  uint32_t       RESERVED7[1U];    /**< Reserved for future use **/
+  __IOM uint32_t ETMTRACEIDR;      /**< CoreSight Trace ID Register  */
+  uint32_t       RESERVED8[1U];    /**< Reserved for future use **/
+  __IM uint32_t  ETMIDR2;          /**< ETM ID Register 2  */
+  uint32_t       RESERVED9[66U];   /**< Reserved for future use **/
+  __IM uint32_t  ETMPDSR;          /**< Device Power-down Status Register  */
+  uint32_t       RESERVED10[754U]; /**< Reserved for future use **/
+  __IOM uint32_t ETMISCIN;         /**< Integration Test Miscellaneous Inputs Register  */
+  uint32_t       RESERVED11[1U];   /**< Reserved for future use **/
+  __IOM uint32_t ITTRIGOUT;        /**< Integration Test Trigger Out Register  */
+  uint32_t       RESERVED12[1U];   /**< Reserved for future use **/
+  __IM uint32_t  ETMITATBCTR2;     /**< ETM Integration Test ATB Control 2 Register  */
+  uint32_t       RESERVED13[1U];   /**< Reserved for future use **/
+  __IOM uint32_t ETMITATBCTR0;     /**< ETM Integration Test ATB Control 0 Register  */
+  uint32_t       RESERVED14[1U];   /**< Reserved for future use **/
+  __IOM uint32_t ETMITCTRL;        /**< ETM Integration Control Register  */
+  uint32_t       RESERVED15[39U];  /**< Reserved for future use **/
+  __IOM uint32_t ETMCLAIMSET;      /**< ETM Claim Tag Set Register  */
+  __IOM uint32_t ETMCLAIMCLR;      /**< ETM Claim Tag Clear Register  */
+  uint32_t       RESERVED16[2U];   /**< Reserved for future use **/
+  __IOM uint32_t ETMLAR;           /**< ETM Lock Access Register  */
+  __IM uint32_t  ETMLSR;           /**< Lock Status Register  */
+  __IM uint32_t  ETMAUTHSTATUS;    /**< ETM Authentication Status Register  */
+  uint32_t       RESERVED17[4U];   /**< Reserved for future use **/
+  __IM uint32_t  ETMDEVTYPE;       /**< CoreSight Device Type Register  */
+  __IM uint32_t  ETMPIDR4;         /**< Peripheral ID4 Register  */
+  __OM uint32_t  ETMPIDR5;         /**< Peripheral ID5 Register  */
+  __OM uint32_t  ETMPIDR6;         /**< Peripheral ID6 Register  */
+  __OM uint32_t  ETMPIDR7;         /**< Peripheral ID7 Register  */
+  __IM uint32_t  ETMPIDR0;         /**< Peripheral ID0 Register  */
+  __IM uint32_t  ETMPIDR1;         /**< Peripheral ID1 Register  */
+  __IM uint32_t  ETMPIDR2;         /**< Peripheral ID2 Register  */
+  __IM uint32_t  ETMPIDR3;         /**< Peripheral ID3 Register  */
+  __IM uint32_t  ETMCIDR0;         /**< Component ID0 Register  */
+  __IM uint32_t  ETMCIDR1;         /**< Component ID1 Register  */
+  __IM uint32_t  ETMCIDR2;         /**< Component ID2 Register  */
+  __IM uint32_t  ETMCIDR3;         /**< Component ID3 Register  */
+} ETM_TypeDef;                     /** @} */
+
+/***************************************************************************//**
+ * @addtogroup EFM32GG12B_ETM
+ * @{
+ * @defgroup EFM32GG12B_ETM_BitFields  ETM Bit Fields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for ETM ETMCR */
+#define _ETM_ETMCR_RESETVALUE                         0x00000411UL                           /**< Default value for ETM_ETMCR */
+#define _ETM_ETMCR_MASK                               0x10632FF1UL                           /**< Mask for ETM_ETMCR */
+#define ETM_ETMCR_POWERDWN                            (0x1UL << 0)                           /**< ETM Control in low power mode */
+#define _ETM_ETMCR_POWERDWN_SHIFT                     0                                      /**< Shift value for ETM_POWERDWN */
+#define _ETM_ETMCR_POWERDWN_MASK                      0x1UL                                  /**< Bit mask for ETM_POWERDWN */
+#define _ETM_ETMCR_POWERDWN_DEFAULT                   0x00000001UL                           /**< Mode DEFAULT for ETM_ETMCR */
+#define ETM_ETMCR_POWERDWN_DEFAULT                    (_ETM_ETMCR_POWERDWN_DEFAULT << 0)     /**< Shifted mode DEFAULT for ETM_ETMCR */
+#define _ETM_ETMCR_PORTSIZE_SHIFT                     4                                      /**< Shift value for ETM_PORTSIZE */
+#define _ETM_ETMCR_PORTSIZE_MASK                      0x70UL                                 /**< Bit mask for ETM_PORTSIZE */
+#define _ETM_ETMCR_PORTSIZE_DEFAULT                   0x00000001UL                           /**< Mode DEFAULT for ETM_ETMCR */
+#define ETM_ETMCR_PORTSIZE_DEFAULT                    (_ETM_ETMCR_PORTSIZE_DEFAULT << 4)     /**< Shifted mode DEFAULT for ETM_ETMCR */
+#define ETM_ETMCR_STALL                               (0x1UL << 7)                           /**< Stall Processor */
+#define _ETM_ETMCR_STALL_SHIFT                        7                                      /**< Shift value for ETM_STALL */
+#define _ETM_ETMCR_STALL_MASK                         0x80UL                                 /**< Bit mask for ETM_STALL */
+#define _ETM_ETMCR_STALL_DEFAULT                      0x00000000UL                           /**< Mode DEFAULT for ETM_ETMCR */
+#define ETM_ETMCR_STALL_DEFAULT                       (_ETM_ETMCR_STALL_DEFAULT << 7)        /**< Shifted mode DEFAULT for ETM_ETMCR */
+#define ETM_ETMCR_BRANCHOUTPUT                        (0x1UL << 8)                           /**< Branch Output */
+#define _ETM_ETMCR_BRANCHOUTPUT_SHIFT                 8                                      /**< Shift value for ETM_BRANCHOUTPUT */
+#define _ETM_ETMCR_BRANCHOUTPUT_MASK                  0x100UL                                /**< Bit mask for ETM_BRANCHOUTPUT */
+#define _ETM_ETMCR_BRANCHOUTPUT_DEFAULT               0x00000000UL                           /**< Mode DEFAULT for ETM_ETMCR */
+#define ETM_ETMCR_BRANCHOUTPUT_DEFAULT                (_ETM_ETMCR_BRANCHOUTPUT_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMCR */
+#define ETM_ETMCR_DBGREQCTRL                          (0x1UL << 9)                           /**< Debug Request Control */
+#define _ETM_ETMCR_DBGREQCTRL_SHIFT                   9                                      /**< Shift value for ETM_DBGREQCTRL */
+#define _ETM_ETMCR_DBGREQCTRL_MASK                    0x200UL                                /**< Bit mask for ETM_DBGREQCTRL */
+#define _ETM_ETMCR_DBGREQCTRL_DEFAULT                 0x00000000UL                           /**< Mode DEFAULT for ETM_ETMCR */
+#define ETM_ETMCR_DBGREQCTRL_DEFAULT                  (_ETM_ETMCR_DBGREQCTRL_DEFAULT << 9)   /**< Shifted mode DEFAULT for ETM_ETMCR */
+#define ETM_ETMCR_ETMPROG                             (0x1UL << 10)                          /**< ETM Programming */
+#define _ETM_ETMCR_ETMPROG_SHIFT                      10                                     /**< Shift value for ETM_ETMPROG */
+#define _ETM_ETMCR_ETMPROG_MASK                       0x400UL                                /**< Bit mask for ETM_ETMPROG */
+#define _ETM_ETMCR_ETMPROG_DEFAULT                    0x00000001UL                           /**< Mode DEFAULT for ETM_ETMCR */
+#define ETM_ETMCR_ETMPROG_DEFAULT                     (_ETM_ETMCR_ETMPROG_DEFAULT << 10)     /**< Shifted mode DEFAULT for ETM_ETMCR */
+#define ETM_ETMCR_ETMPORTSEL                          (0x1UL << 11)                          /**< ETM Port Selection */
+#define _ETM_ETMCR_ETMPORTSEL_SHIFT                   11                                     /**< Shift value for ETM_ETMPORTSEL */
+#define _ETM_ETMCR_ETMPORTSEL_MASK                    0x800UL                                /**< Bit mask for ETM_ETMPORTSEL */
+#define _ETM_ETMCR_ETMPORTSEL_DEFAULT                 0x00000000UL                           /**< Mode DEFAULT for ETM_ETMCR */
+#define _ETM_ETMCR_ETMPORTSEL_ETMLOW                  0x00000000UL                           /**< Mode ETMLOW for ETM_ETMCR */
+#define _ETM_ETMCR_ETMPORTSEL_ETMHIGH                 0x00000001UL                           /**< Mode ETMHIGH for ETM_ETMCR */
+#define ETM_ETMCR_ETMPORTSEL_DEFAULT                  (_ETM_ETMCR_ETMPORTSEL_DEFAULT << 11)  /**< Shifted mode DEFAULT for ETM_ETMCR */
+#define ETM_ETMCR_ETMPORTSEL_ETMLOW                   (_ETM_ETMCR_ETMPORTSEL_ETMLOW << 11)   /**< Shifted mode ETMLOW for ETM_ETMCR */
+#define ETM_ETMCR_ETMPORTSEL_ETMHIGH                  (_ETM_ETMCR_ETMPORTSEL_ETMHIGH << 11)  /**< Shifted mode ETMHIGH for ETM_ETMCR */
+#define ETM_ETMCR_PORTMODE2                           (0x1UL << 13)                          /**< Port Mode[2] */
+#define _ETM_ETMCR_PORTMODE2_SHIFT                    13                                     /**< Shift value for ETM_PORTMODE2 */
+#define _ETM_ETMCR_PORTMODE2_MASK                     0x2000UL                               /**< Bit mask for ETM_PORTMODE2 */
+#define _ETM_ETMCR_PORTMODE2_DEFAULT                  0x00000000UL                           /**< Mode DEFAULT for ETM_ETMCR */
+#define ETM_ETMCR_PORTMODE2_DEFAULT                   (_ETM_ETMCR_PORTMODE2_DEFAULT << 13)   /**< Shifted mode DEFAULT for ETM_ETMCR */
+#define _ETM_ETMCR_PORTMODE_SHIFT                     16                                     /**< Shift value for ETM_PORTMODE */
+#define _ETM_ETMCR_PORTMODE_MASK                      0x30000UL                              /**< Bit mask for ETM_PORTMODE */
+#define _ETM_ETMCR_PORTMODE_DEFAULT                   0x00000000UL                           /**< Mode DEFAULT for ETM_ETMCR */
+#define ETM_ETMCR_PORTMODE_DEFAULT                    (_ETM_ETMCR_PORTMODE_DEFAULT << 16)    /**< Shifted mode DEFAULT for ETM_ETMCR */
+#define _ETM_ETMCR_EPORTSIZE_SHIFT                    21                                     /**< Shift value for ETM_EPORTSIZE */
+#define _ETM_ETMCR_EPORTSIZE_MASK                     0x600000UL                             /**< Bit mask for ETM_EPORTSIZE */
+#define _ETM_ETMCR_EPORTSIZE_DEFAULT                  0x00000000UL                           /**< Mode DEFAULT for ETM_ETMCR */
+#define ETM_ETMCR_EPORTSIZE_DEFAULT                   (_ETM_ETMCR_EPORTSIZE_DEFAULT << 21)   /**< Shifted mode DEFAULT for ETM_ETMCR */
+#define ETM_ETMCR_TSTAMPEN                            (0x1UL << 28)                          /**< Time Stamp Enable */
+#define _ETM_ETMCR_TSTAMPEN_SHIFT                     28                                     /**< Shift value for ETM_TSTAMPEN */
+#define _ETM_ETMCR_TSTAMPEN_MASK                      0x10000000UL                           /**< Bit mask for ETM_TSTAMPEN */
+#define _ETM_ETMCR_TSTAMPEN_DEFAULT                   0x00000000UL                           /**< Mode DEFAULT for ETM_ETMCR */
+#define ETM_ETMCR_TSTAMPEN_DEFAULT                    (_ETM_ETMCR_TSTAMPEN_DEFAULT << 28)    /**< Shifted mode DEFAULT for ETM_ETMCR */
+
+/* Bit fields for ETM ETMCCR */
+#define _ETM_ETMCCR_RESETVALUE                        0x8C802000UL                             /**< Default value for ETM_ETMCCR */
+#define _ETM_ETMCCR_MASK                              0x8FFFFFFFUL                             /**< Mask for ETM_ETMCCR */
+#define _ETM_ETMCCR_ADRCMPPAIR_SHIFT                  0                                        /**< Shift value for ETM_ADRCMPPAIR */
+#define _ETM_ETMCCR_ADRCMPPAIR_MASK                   0xFUL                                    /**< Bit mask for ETM_ADRCMPPAIR */
+#define _ETM_ETMCCR_ADRCMPPAIR_DEFAULT                0x00000000UL                             /**< Mode DEFAULT for ETM_ETMCCR */
+#define ETM_ETMCCR_ADRCMPPAIR_DEFAULT                 (_ETM_ETMCCR_ADRCMPPAIR_DEFAULT << 0)    /**< Shifted mode DEFAULT for ETM_ETMCCR */
+#define _ETM_ETMCCR_DATACMPNUM_SHIFT                  4                                        /**< Shift value for ETM_DATACMPNUM */
+#define _ETM_ETMCCR_DATACMPNUM_MASK                   0xF0UL                                   /**< Bit mask for ETM_DATACMPNUM */
+#define _ETM_ETMCCR_DATACMPNUM_DEFAULT                0x00000000UL                             /**< Mode DEFAULT for ETM_ETMCCR */
+#define ETM_ETMCCR_DATACMPNUM_DEFAULT                 (_ETM_ETMCCR_DATACMPNUM_DEFAULT << 4)    /**< Shifted mode DEFAULT for ETM_ETMCCR */
+#define _ETM_ETMCCR_MMDECCNT_SHIFT                    8                                        /**< Shift value for ETM_MMDECCNT */
+#define _ETM_ETMCCR_MMDECCNT_MASK                     0x1F00UL                                 /**< Bit mask for ETM_MMDECCNT */
+#define _ETM_ETMCCR_MMDECCNT_DEFAULT                  0x00000000UL                             /**< Mode DEFAULT for ETM_ETMCCR */
+#define ETM_ETMCCR_MMDECCNT_DEFAULT                   (_ETM_ETMCCR_MMDECCNT_DEFAULT << 8)      /**< Shifted mode DEFAULT for ETM_ETMCCR */
+#define _ETM_ETMCCR_COUNTNUM_SHIFT                    13                                       /**< Shift value for ETM_COUNTNUM */
+#define _ETM_ETMCCR_COUNTNUM_MASK                     0xE000UL                                 /**< Bit mask for ETM_COUNTNUM */
+#define _ETM_ETMCCR_COUNTNUM_DEFAULT                  0x00000001UL                             /**< Mode DEFAULT for ETM_ETMCCR */
+#define ETM_ETMCCR_COUNTNUM_DEFAULT                   (_ETM_ETMCCR_COUNTNUM_DEFAULT << 13)     /**< Shifted mode DEFAULT for ETM_ETMCCR */
+#define ETM_ETMCCR_SEQPRES                            (0x1UL << 16)                            /**< Sequencer Present */
+#define _ETM_ETMCCR_SEQPRES_SHIFT                     16                                       /**< Shift value for ETM_SEQPRES */
+#define _ETM_ETMCCR_SEQPRES_MASK                      0x10000UL                                /**< Bit mask for ETM_SEQPRES */
+#define _ETM_ETMCCR_SEQPRES_DEFAULT                   0x00000000UL                             /**< Mode DEFAULT for ETM_ETMCCR */
+#define ETM_ETMCCR_SEQPRES_DEFAULT                    (_ETM_ETMCCR_SEQPRES_DEFAULT << 16)      /**< Shifted mode DEFAULT for ETM_ETMCCR */
+#define _ETM_ETMCCR_EXTINPNUM_SHIFT                   17                                       /**< Shift value for ETM_EXTINPNUM */
+#define _ETM_ETMCCR_EXTINPNUM_MASK                    0xE0000UL                                /**< Bit mask for ETM_EXTINPNUM */
+#define _ETM_ETMCCR_EXTINPNUM_DEFAULT                 0x00000000UL                             /**< Mode DEFAULT for ETM_ETMCCR */
+#define _ETM_ETMCCR_EXTINPNUM_ZERO                    0x00000000UL                             /**< Mode ZERO for ETM_ETMCCR */
+#define _ETM_ETMCCR_EXTINPNUM_ONE                     0x00000001UL                             /**< Mode ONE for ETM_ETMCCR */
+#define _ETM_ETMCCR_EXTINPNUM_TWO                     0x00000002UL                             /**< Mode TWO for ETM_ETMCCR */
+#define ETM_ETMCCR_EXTINPNUM_DEFAULT                  (_ETM_ETMCCR_EXTINPNUM_DEFAULT << 17)    /**< Shifted mode DEFAULT for ETM_ETMCCR */
+#define ETM_ETMCCR_EXTINPNUM_ZERO                     (_ETM_ETMCCR_EXTINPNUM_ZERO << 17)       /**< Shifted mode ZERO for ETM_ETMCCR */
+#define ETM_ETMCCR_EXTINPNUM_ONE                      (_ETM_ETMCCR_EXTINPNUM_ONE << 17)        /**< Shifted mode ONE for ETM_ETMCCR */
+#define ETM_ETMCCR_EXTINPNUM_TWO                      (_ETM_ETMCCR_EXTINPNUM_TWO << 17)        /**< Shifted mode TWO for ETM_ETMCCR */
+#define _ETM_ETMCCR_EXTOUTNUM_SHIFT                   20                                       /**< Shift value for ETM_EXTOUTNUM */
+#define _ETM_ETMCCR_EXTOUTNUM_MASK                    0x700000UL                               /**< Bit mask for ETM_EXTOUTNUM */
+#define _ETM_ETMCCR_EXTOUTNUM_DEFAULT                 0x00000000UL                             /**< Mode DEFAULT for ETM_ETMCCR */
+#define ETM_ETMCCR_EXTOUTNUM_DEFAULT                  (_ETM_ETMCCR_EXTOUTNUM_DEFAULT << 20)    /**< Shifted mode DEFAULT for ETM_ETMCCR */
+#define ETM_ETMCCR_FIFOFULLPRES                       (0x1UL << 23)                            /**< FIFIO FULL present */
+#define _ETM_ETMCCR_FIFOFULLPRES_SHIFT                23                                       /**< Shift value for ETM_FIFOFULLPRES */
+#define _ETM_ETMCCR_FIFOFULLPRES_MASK                 0x800000UL                               /**< Bit mask for ETM_FIFOFULLPRES */
+#define _ETM_ETMCCR_FIFOFULLPRES_DEFAULT              0x00000001UL                             /**< Mode DEFAULT for ETM_ETMCCR */
+#define ETM_ETMCCR_FIFOFULLPRES_DEFAULT               (_ETM_ETMCCR_FIFOFULLPRES_DEFAULT << 23) /**< Shifted mode DEFAULT for ETM_ETMCCR */
+#define _ETM_ETMCCR_IDCOMPNUM_SHIFT                   24                                       /**< Shift value for ETM_IDCOMPNUM */
+#define _ETM_ETMCCR_IDCOMPNUM_MASK                    0x3000000UL                              /**< Bit mask for ETM_IDCOMPNUM */
+#define _ETM_ETMCCR_IDCOMPNUM_DEFAULT                 0x00000000UL                             /**< Mode DEFAULT for ETM_ETMCCR */
+#define ETM_ETMCCR_IDCOMPNUM_DEFAULT                  (_ETM_ETMCCR_IDCOMPNUM_DEFAULT << 24)    /**< Shifted mode DEFAULT for ETM_ETMCCR */
+#define ETM_ETMCCR_TRACESS                            (0x1UL << 26)                            /**< Trace Start/Stop Block Present */
+#define _ETM_ETMCCR_TRACESS_SHIFT                     26                                       /**< Shift value for ETM_TRACESS */
+#define _ETM_ETMCCR_TRACESS_MASK                      0x4000000UL                              /**< Bit mask for ETM_TRACESS */
+#define _ETM_ETMCCR_TRACESS_DEFAULT                   0x00000001UL                             /**< Mode DEFAULT for ETM_ETMCCR */
+#define ETM_ETMCCR_TRACESS_DEFAULT                    (_ETM_ETMCCR_TRACESS_DEFAULT << 26)      /**< Shifted mode DEFAULT for ETM_ETMCCR */
+#define ETM_ETMCCR_MMACCESS                           (0x1UL << 27)                            /**< Coprocessor and Memeory Access */
+#define _ETM_ETMCCR_MMACCESS_SHIFT                    27                                       /**< Shift value for ETM_MMACCESS */
+#define _ETM_ETMCCR_MMACCESS_MASK                     0x8000000UL                              /**< Bit mask for ETM_MMACCESS */
+#define _ETM_ETMCCR_MMACCESS_DEFAULT                  0x00000001UL                             /**< Mode DEFAULT for ETM_ETMCCR */
+#define ETM_ETMCCR_MMACCESS_DEFAULT                   (_ETM_ETMCCR_MMACCESS_DEFAULT << 27)     /**< Shifted mode DEFAULT for ETM_ETMCCR */
+#define ETM_ETMCCR_ETMID                              (0x1UL << 31)                            /**< ETM ID Register Present */
+#define _ETM_ETMCCR_ETMID_SHIFT                       31                                       /**< Shift value for ETM_ETMID */
+#define _ETM_ETMCCR_ETMID_MASK                        0x80000000UL                             /**< Bit mask for ETM_ETMID */
+#define _ETM_ETMCCR_ETMID_DEFAULT                     0x00000001UL                             /**< Mode DEFAULT for ETM_ETMCCR */
+#define ETM_ETMCCR_ETMID_DEFAULT                      (_ETM_ETMCCR_ETMID_DEFAULT << 31)        /**< Shifted mode DEFAULT for ETM_ETMCCR */
+
+/* Bit fields for ETM ETMTRIGGER */
+#define _ETM_ETMTRIGGER_RESETVALUE                    0x00000000UL                           /**< Default value for ETM_ETMTRIGGER */
+#define _ETM_ETMTRIGGER_MASK                          0x0001FFFFUL                           /**< Mask for ETM_ETMTRIGGER */
+#define _ETM_ETMTRIGGER_RESA_SHIFT                    0                                      /**< Shift value for ETM_RESA */
+#define _ETM_ETMTRIGGER_RESA_MASK                     0x7FUL                                 /**< Bit mask for ETM_RESA */
+#define _ETM_ETMTRIGGER_RESA_DEFAULT                  0x00000000UL                           /**< Mode DEFAULT for ETM_ETMTRIGGER */
+#define ETM_ETMTRIGGER_RESA_DEFAULT                   (_ETM_ETMTRIGGER_RESA_DEFAULT << 0)    /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */
+#define _ETM_ETMTRIGGER_RESB_SHIFT                    7                                      /**< Shift value for ETM_RESB */
+#define _ETM_ETMTRIGGER_RESB_MASK                     0x3F80UL                               /**< Bit mask for ETM_RESB */
+#define _ETM_ETMTRIGGER_RESB_DEFAULT                  0x00000000UL                           /**< Mode DEFAULT for ETM_ETMTRIGGER */
+#define ETM_ETMTRIGGER_RESB_DEFAULT                   (_ETM_ETMTRIGGER_RESB_DEFAULT << 7)    /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */
+#define _ETM_ETMTRIGGER_ETMFCN_SHIFT                  14                                     /**< Shift value for ETM_ETMFCN */
+#define _ETM_ETMTRIGGER_ETMFCN_MASK                   0x1C000UL                              /**< Bit mask for ETM_ETMFCN */
+#define _ETM_ETMTRIGGER_ETMFCN_DEFAULT                0x00000000UL                           /**< Mode DEFAULT for ETM_ETMTRIGGER */
+#define ETM_ETMTRIGGER_ETMFCN_DEFAULT                 (_ETM_ETMTRIGGER_ETMFCN_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */
+
+/* Bit fields for ETM ETMSR */
+#define _ETM_ETMSR_RESETVALUE                         0x00000002UL                         /**< Default value for ETM_ETMSR */
+#define _ETM_ETMSR_MASK                               0x0000000FUL                         /**< Mask for ETM_ETMSR */
+#define ETM_ETMSR_ETHOF                               (0x1UL << 0)                         /**< ETM Overflow */
+#define _ETM_ETMSR_ETHOF_SHIFT                        0                                    /**< Shift value for ETM_ETHOF */
+#define _ETM_ETMSR_ETHOF_MASK                         0x1UL                                /**< Bit mask for ETM_ETHOF */
+#define _ETM_ETMSR_ETHOF_DEFAULT                      0x00000000UL                         /**< Mode DEFAULT for ETM_ETMSR */
+#define ETM_ETMSR_ETHOF_DEFAULT                       (_ETM_ETMSR_ETHOF_DEFAULT << 0)      /**< Shifted mode DEFAULT for ETM_ETMSR */
+#define ETM_ETMSR_ETMPROGBIT                          (0x1UL << 1)                         /**< ETM Programming Bit Status */
+#define _ETM_ETMSR_ETMPROGBIT_SHIFT                   1                                    /**< Shift value for ETM_ETMPROGBIT */
+#define _ETM_ETMSR_ETMPROGBIT_MASK                    0x2UL                                /**< Bit mask for ETM_ETMPROGBIT */
+#define _ETM_ETMSR_ETMPROGBIT_DEFAULT                 0x00000001UL                         /**< Mode DEFAULT for ETM_ETMSR */
+#define ETM_ETMSR_ETMPROGBIT_DEFAULT                  (_ETM_ETMSR_ETMPROGBIT_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMSR */
+#define ETM_ETMSR_TRACESTAT                           (0x1UL << 2)                         /**< Trace Start/Stop Status */
+#define _ETM_ETMSR_TRACESTAT_SHIFT                    2                                    /**< Shift value for ETM_TRACESTAT */
+#define _ETM_ETMSR_TRACESTAT_MASK                     0x4UL                                /**< Bit mask for ETM_TRACESTAT */
+#define _ETM_ETMSR_TRACESTAT_DEFAULT                  0x00000000UL                         /**< Mode DEFAULT for ETM_ETMSR */
+#define ETM_ETMSR_TRACESTAT_DEFAULT                   (_ETM_ETMSR_TRACESTAT_DEFAULT << 2)  /**< Shifted mode DEFAULT for ETM_ETMSR */
+#define ETM_ETMSR_TRIGBIT                             (0x1UL << 3)                         /**< Trigger Bit */
+#define _ETM_ETMSR_TRIGBIT_SHIFT                      3                                    /**< Shift value for ETM_TRIGBIT */
+#define _ETM_ETMSR_TRIGBIT_MASK                       0x8UL                                /**< Bit mask for ETM_TRIGBIT */
+#define _ETM_ETMSR_TRIGBIT_DEFAULT                    0x00000000UL                         /**< Mode DEFAULT for ETM_ETMSR */
+#define ETM_ETMSR_TRIGBIT_DEFAULT                     (_ETM_ETMSR_TRIGBIT_DEFAULT << 3)    /**< Shifted mode DEFAULT for ETM_ETMSR */
+
+/* Bit fields for ETM ETMSCR */
+#define _ETM_ETMSCR_RESETVALUE                        0x00020D09UL                            /**< Default value for ETM_ETMSCR */
+#define _ETM_ETMSCR_MASK                              0x00027F0FUL                            /**< Mask for ETM_ETMSCR */
+#define _ETM_ETMSCR_MAXPORTSIZE_SHIFT                 0                                       /**< Shift value for ETM_MAXPORTSIZE */
+#define _ETM_ETMSCR_MAXPORTSIZE_MASK                  0x7UL                                   /**< Bit mask for ETM_MAXPORTSIZE */
+#define _ETM_ETMSCR_MAXPORTSIZE_DEFAULT               0x00000001UL                            /**< Mode DEFAULT for ETM_ETMSCR */
+#define ETM_ETMSCR_MAXPORTSIZE_DEFAULT                (_ETM_ETMSCR_MAXPORTSIZE_DEFAULT << 0)  /**< Shifted mode DEFAULT for ETM_ETMSCR */
+#define ETM_ETMSCR_FIFOFULL                           (0x1UL << 8)                            /**< FIFO FULL Supported */
+#define _ETM_ETMSCR_FIFOFULL_SHIFT                    8                                       /**< Shift value for ETM_FIFOFULL */
+#define _ETM_ETMSCR_FIFOFULL_MASK                     0x100UL                                 /**< Bit mask for ETM_FIFOFULL */
+#define _ETM_ETMSCR_FIFOFULL_DEFAULT                  0x00000001UL                            /**< Mode DEFAULT for ETM_ETMSCR */
+#define ETM_ETMSCR_FIFOFULL_DEFAULT                   (_ETM_ETMSCR_FIFOFULL_DEFAULT << 8)     /**< Shifted mode DEFAULT for ETM_ETMSCR */
+#define ETM_ETMSCR_MAXPORTSIZE3                       (0x1UL << 9)                            /**< Max Port Size[3] */
+#define _ETM_ETMSCR_MAXPORTSIZE3_SHIFT                9                                       /**< Shift value for ETM_MAXPORTSIZE3 */
+#define _ETM_ETMSCR_MAXPORTSIZE3_MASK                 0x200UL                                 /**< Bit mask for ETM_MAXPORTSIZE3 */
+#define _ETM_ETMSCR_MAXPORTSIZE3_DEFAULT              0x00000000UL                            /**< Mode DEFAULT for ETM_ETMSCR */
+#define ETM_ETMSCR_MAXPORTSIZE3_DEFAULT               (_ETM_ETMSCR_MAXPORTSIZE3_DEFAULT << 9) /**< Shifted mode DEFAULT for ETM_ETMSCR */
+#define ETM_ETMSCR_PORTSIZE                           (0x1UL << 10)                           /**< Port Size Supported */
+#define _ETM_ETMSCR_PORTSIZE_SHIFT                    10                                      /**< Shift value for ETM_PORTSIZE */
+#define _ETM_ETMSCR_PORTSIZE_MASK                     0x400UL                                 /**< Bit mask for ETM_PORTSIZE */
+#define _ETM_ETMSCR_PORTSIZE_DEFAULT                  0x00000001UL                            /**< Mode DEFAULT for ETM_ETMSCR */
+#define ETM_ETMSCR_PORTSIZE_DEFAULT                   (_ETM_ETMSCR_PORTSIZE_DEFAULT << 10)    /**< Shifted mode DEFAULT for ETM_ETMSCR */
+#define ETM_ETMSCR_PORTMODE                           (0x1UL << 11)                           /**< Port Mode Supported */
+#define _ETM_ETMSCR_PORTMODE_SHIFT                    11                                      /**< Shift value for ETM_PORTMODE */
+#define _ETM_ETMSCR_PORTMODE_MASK                     0x800UL                                 /**< Bit mask for ETM_PORTMODE */
+#define _ETM_ETMSCR_PORTMODE_DEFAULT                  0x00000001UL                            /**< Mode DEFAULT for ETM_ETMSCR */
+#define ETM_ETMSCR_PORTMODE_DEFAULT                   (_ETM_ETMSCR_PORTMODE_DEFAULT << 11)    /**< Shifted mode DEFAULT for ETM_ETMSCR */
+#define _ETM_ETMSCR_PROCNUM_SHIFT                     12                                      /**< Shift value for ETM_PROCNUM */
+#define _ETM_ETMSCR_PROCNUM_MASK                      0x7000UL                                /**< Bit mask for ETM_PROCNUM */
+#define _ETM_ETMSCR_PROCNUM_DEFAULT                   0x00000000UL                            /**< Mode DEFAULT for ETM_ETMSCR */
+#define ETM_ETMSCR_PROCNUM_DEFAULT                    (_ETM_ETMSCR_PROCNUM_DEFAULT << 12)     /**< Shifted mode DEFAULT for ETM_ETMSCR */
+#define ETM_ETMSCR_NOFETCHCOMP                        (0x1UL << 17)                           /**< No Fetch Comparison */
+#define _ETM_ETMSCR_NOFETCHCOMP_SHIFT                 17                                      /**< Shift value for ETM_NOFETCHCOMP */
+#define _ETM_ETMSCR_NOFETCHCOMP_MASK                  0x20000UL                               /**< Bit mask for ETM_NOFETCHCOMP */
+#define _ETM_ETMSCR_NOFETCHCOMP_DEFAULT               0x00000001UL                            /**< Mode DEFAULT for ETM_ETMSCR */
+#define ETM_ETMSCR_NOFETCHCOMP_DEFAULT                (_ETM_ETMSCR_NOFETCHCOMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ETM_ETMSCR */
+
+/* Bit fields for ETM ETMTEEVR */
+#define _ETM_ETMTEEVR_RESETVALUE                      0x00000000UL                           /**< Default value for ETM_ETMTEEVR */
+#define _ETM_ETMTEEVR_MASK                            0x0001FFFFUL                           /**< Mask for ETM_ETMTEEVR */
+#define _ETM_ETMTEEVR_RESA_SHIFT                      0                                      /**< Shift value for ETM_RESA */
+#define _ETM_ETMTEEVR_RESA_MASK                       0x7FUL                                 /**< Bit mask for ETM_RESA */
+#define _ETM_ETMTEEVR_RESA_DEFAULT                    0x00000000UL                           /**< Mode DEFAULT for ETM_ETMTEEVR */
+#define ETM_ETMTEEVR_RESA_DEFAULT                     (_ETM_ETMTEEVR_RESA_DEFAULT << 0)      /**< Shifted mode DEFAULT for ETM_ETMTEEVR */
+#define _ETM_ETMTEEVR_RESB_SHIFT                      7                                      /**< Shift value for ETM_RESB */
+#define _ETM_ETMTEEVR_RESB_MASK                       0x3F80UL                               /**< Bit mask for ETM_RESB */
+#define _ETM_ETMTEEVR_RESB_DEFAULT                    0x00000000UL                           /**< Mode DEFAULT for ETM_ETMTEEVR */
+#define ETM_ETMTEEVR_RESB_DEFAULT                     (_ETM_ETMTEEVR_RESB_DEFAULT << 7)      /**< Shifted mode DEFAULT for ETM_ETMTEEVR */
+#define _ETM_ETMTEEVR_ETMFCNEN_SHIFT                  14                                     /**< Shift value for ETM_ETMFCNEN */
+#define _ETM_ETMTEEVR_ETMFCNEN_MASK                   0x1C000UL                              /**< Bit mask for ETM_ETMFCNEN */
+#define _ETM_ETMTEEVR_ETMFCNEN_DEFAULT                0x00000000UL                           /**< Mode DEFAULT for ETM_ETMTEEVR */
+#define ETM_ETMTEEVR_ETMFCNEN_DEFAULT                 (_ETM_ETMTEEVR_ETMFCNEN_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */
+
+/* Bit fields for ETM ETMTECR1 */
+#define _ETM_ETMTECR1_RESETVALUE                      0x00000000UL                           /**< Default value for ETM_ETMTECR1 */
+#define _ETM_ETMTECR1_MASK                            0x03FFFFFFUL                           /**< Mask for ETM_ETMTECR1 */
+#define _ETM_ETMTECR1_ADRCMP_SHIFT                    0                                      /**< Shift value for ETM_ADRCMP */
+#define _ETM_ETMTECR1_ADRCMP_MASK                     0xFFUL                                 /**< Bit mask for ETM_ADRCMP */
+#define _ETM_ETMTECR1_ADRCMP_DEFAULT                  0x00000000UL                           /**< Mode DEFAULT for ETM_ETMTECR1 */
+#define ETM_ETMTECR1_ADRCMP_DEFAULT                   (_ETM_ETMTECR1_ADRCMP_DEFAULT << 0)    /**< Shifted mode DEFAULT for ETM_ETMTECR1 */
+#define _ETM_ETMTECR1_MEMMAP_SHIFT                    8                                      /**< Shift value for ETM_MEMMAP */
+#define _ETM_ETMTECR1_MEMMAP_MASK                     0xFFFF00UL                             /**< Bit mask for ETM_MEMMAP */
+#define _ETM_ETMTECR1_MEMMAP_DEFAULT                  0x00000000UL                           /**< Mode DEFAULT for ETM_ETMTECR1 */
+#define ETM_ETMTECR1_MEMMAP_DEFAULT                   (_ETM_ETMTECR1_MEMMAP_DEFAULT << 8)    /**< Shifted mode DEFAULT for ETM_ETMTECR1 */
+#define ETM_ETMTECR1_INCEXCTL                         (0x1UL << 24)                          /**< Trace Include/Exclude Flag */
+#define _ETM_ETMTECR1_INCEXCTL_SHIFT                  24                                     /**< Shift value for ETM_INCEXCTL */
+#define _ETM_ETMTECR1_INCEXCTL_MASK                   0x1000000UL                            /**< Bit mask for ETM_INCEXCTL */
+#define _ETM_ETMTECR1_INCEXCTL_DEFAULT                0x00000000UL                           /**< Mode DEFAULT for ETM_ETMTECR1 */
+#define _ETM_ETMTECR1_INCEXCTL_INC                    0x00000000UL                           /**< Mode INC for ETM_ETMTECR1 */
+#define _ETM_ETMTECR1_INCEXCTL_EXC                    0x00000001UL                           /**< Mode EXC for ETM_ETMTECR1 */
+#define ETM_ETMTECR1_INCEXCTL_DEFAULT                 (_ETM_ETMTECR1_INCEXCTL_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */
+#define ETM_ETMTECR1_INCEXCTL_INC                     (_ETM_ETMTECR1_INCEXCTL_INC << 24)     /**< Shifted mode INC for ETM_ETMTECR1 */
+#define ETM_ETMTECR1_INCEXCTL_EXC                     (_ETM_ETMTECR1_INCEXCTL_EXC << 24)     /**< Shifted mode EXC for ETM_ETMTECR1 */
+#define ETM_ETMTECR1_TCE                              (0x1UL << 25)                          /**< Trace Control Enable */
+#define _ETM_ETMTECR1_TCE_SHIFT                       25                                     /**< Shift value for ETM_TCE */
+#define _ETM_ETMTECR1_TCE_MASK                        0x2000000UL                            /**< Bit mask for ETM_TCE */
+#define _ETM_ETMTECR1_TCE_DEFAULT                     0x00000000UL                           /**< Mode DEFAULT for ETM_ETMTECR1 */
+#define _ETM_ETMTECR1_TCE_EN                          0x00000000UL                           /**< Mode EN for ETM_ETMTECR1 */
+#define _ETM_ETMTECR1_TCE_DIS                         0x00000001UL                           /**< Mode DIS for ETM_ETMTECR1 */
+#define ETM_ETMTECR1_TCE_DEFAULT                      (_ETM_ETMTECR1_TCE_DEFAULT << 25)      /**< Shifted mode DEFAULT for ETM_ETMTECR1 */
+#define ETM_ETMTECR1_TCE_EN                           (_ETM_ETMTECR1_TCE_EN << 25)           /**< Shifted mode EN for ETM_ETMTECR1 */
+#define ETM_ETMTECR1_TCE_DIS                          (_ETM_ETMTECR1_TCE_DIS << 25)          /**< Shifted mode DIS for ETM_ETMTECR1 */
+
+/* Bit fields for ETM ETMFFLR */
+#define _ETM_ETMFFLR_RESETVALUE                       0x00000000UL                        /**< Default value for ETM_ETMFFLR */
+#define _ETM_ETMFFLR_MASK                             0x000000FFUL                        /**< Mask for ETM_ETMFFLR */
+#define _ETM_ETMFFLR_BYTENUM_SHIFT                    0                                   /**< Shift value for ETM_BYTENUM */
+#define _ETM_ETMFFLR_BYTENUM_MASK                     0xFFUL                              /**< Bit mask for ETM_BYTENUM */
+#define _ETM_ETMFFLR_BYTENUM_DEFAULT                  0x00000000UL                        /**< Mode DEFAULT for ETM_ETMFFLR */
+#define ETM_ETMFFLR_BYTENUM_DEFAULT                   (_ETM_ETMFFLR_BYTENUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMFFLR */
+
+/* Bit fields for ETM ETMCNTRLDVR1 */
+#define _ETM_ETMCNTRLDVR1_RESETVALUE                  0x00000000UL                           /**< Default value for ETM_ETMCNTRLDVR1 */
+#define _ETM_ETMCNTRLDVR1_MASK                        0x0000FFFFUL                           /**< Mask for ETM_ETMCNTRLDVR1 */
+#define _ETM_ETMCNTRLDVR1_COUNT_SHIFT                 0                                      /**< Shift value for ETM_COUNT */
+#define _ETM_ETMCNTRLDVR1_COUNT_MASK                  0xFFFFUL                               /**< Bit mask for ETM_COUNT */
+#define _ETM_ETMCNTRLDVR1_COUNT_DEFAULT               0x00000000UL                           /**< Mode DEFAULT for ETM_ETMCNTRLDVR1 */
+#define ETM_ETMCNTRLDVR1_COUNT_DEFAULT                (_ETM_ETMCNTRLDVR1_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCNTRLDVR1 */
+
+/* Bit fields for ETM ETMSYNCFR */
+#define _ETM_ETMSYNCFR_RESETVALUE                     0x00000400UL                       /**< Default value for ETM_ETMSYNCFR */
+#define _ETM_ETMSYNCFR_MASK                           0x00000FFFUL                       /**< Mask for ETM_ETMSYNCFR */
+#define _ETM_ETMSYNCFR_FREQ_SHIFT                     0                                  /**< Shift value for ETM_FREQ */
+#define _ETM_ETMSYNCFR_FREQ_MASK                      0xFFFUL                            /**< Bit mask for ETM_FREQ */
+#define _ETM_ETMSYNCFR_FREQ_DEFAULT                   0x00000400UL                       /**< Mode DEFAULT for ETM_ETMSYNCFR */
+#define ETM_ETMSYNCFR_FREQ_DEFAULT                    (_ETM_ETMSYNCFR_FREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSYNCFR */
+
+/* Bit fields for ETM ETMIDR */
+#define _ETM_ETMIDR_RESETVALUE                        0x4114F253UL                         /**< Default value for ETM_ETMIDR */
+#define _ETM_ETMIDR_MASK                              0xFF1DFFFFUL                         /**< Mask for ETM_ETMIDR */
+#define _ETM_ETMIDR_IMPVER_SHIFT                      0                                    /**< Shift value for ETM_IMPVER */
+#define _ETM_ETMIDR_IMPVER_MASK                       0xFUL                                /**< Bit mask for ETM_IMPVER */
+#define _ETM_ETMIDR_IMPVER_DEFAULT                    0x00000003UL                         /**< Mode DEFAULT for ETM_ETMIDR */
+#define ETM_ETMIDR_IMPVER_DEFAULT                     (_ETM_ETMIDR_IMPVER_DEFAULT << 0)    /**< Shifted mode DEFAULT for ETM_ETMIDR */
+#define _ETM_ETMIDR_ETMMINVER_SHIFT                   4                                    /**< Shift value for ETM_ETMMINVER */
+#define _ETM_ETMIDR_ETMMINVER_MASK                    0xF0UL                               /**< Bit mask for ETM_ETMMINVER */
+#define _ETM_ETMIDR_ETMMINVER_DEFAULT                 0x00000005UL                         /**< Mode DEFAULT for ETM_ETMIDR */
+#define ETM_ETMIDR_ETMMINVER_DEFAULT                  (_ETM_ETMIDR_ETMMINVER_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMIDR */
+#define _ETM_ETMIDR_ETMMAJVER_SHIFT                   8                                    /**< Shift value for ETM_ETMMAJVER */
+#define _ETM_ETMIDR_ETMMAJVER_MASK                    0xF00UL                              /**< Bit mask for ETM_ETMMAJVER */
+#define _ETM_ETMIDR_ETMMAJVER_DEFAULT                 0x00000002UL                         /**< Mode DEFAULT for ETM_ETMIDR */
+#define ETM_ETMIDR_ETMMAJVER_DEFAULT                  (_ETM_ETMIDR_ETMMAJVER_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMIDR */
+#define _ETM_ETMIDR_PROCFAM_SHIFT                     12                                   /**< Shift value for ETM_PROCFAM */
+#define _ETM_ETMIDR_PROCFAM_MASK                      0xF000UL                             /**< Bit mask for ETM_PROCFAM */
+#define _ETM_ETMIDR_PROCFAM_DEFAULT                   0x0000000FUL                         /**< Mode DEFAULT for ETM_ETMIDR */
+#define ETM_ETMIDR_PROCFAM_DEFAULT                    (_ETM_ETMIDR_PROCFAM_DEFAULT << 12)  /**< Shifted mode DEFAULT for ETM_ETMIDR */
+#define ETM_ETMIDR_LPCF                               (0x1UL << 16)                        /**< Load PC First */
+#define _ETM_ETMIDR_LPCF_SHIFT                        16                                   /**< Shift value for ETM_LPCF */
+#define _ETM_ETMIDR_LPCF_MASK                         0x10000UL                            /**< Bit mask for ETM_LPCF */
+#define _ETM_ETMIDR_LPCF_DEFAULT                      0x00000000UL                         /**< Mode DEFAULT for ETM_ETMIDR */
+#define ETM_ETMIDR_LPCF_DEFAULT                       (_ETM_ETMIDR_LPCF_DEFAULT << 16)     /**< Shifted mode DEFAULT for ETM_ETMIDR */
+#define ETM_ETMIDR_THUMBT                             (0x1UL << 18)                        /**< 32-bit Thumb Instruction Tracing */
+#define _ETM_ETMIDR_THUMBT_SHIFT                      18                                   /**< Shift value for ETM_THUMBT */
+#define _ETM_ETMIDR_THUMBT_MASK                       0x40000UL                            /**< Bit mask for ETM_THUMBT */
+#define _ETM_ETMIDR_THUMBT_DEFAULT                    0x00000001UL                         /**< Mode DEFAULT for ETM_ETMIDR */
+#define ETM_ETMIDR_THUMBT_DEFAULT                     (_ETM_ETMIDR_THUMBT_DEFAULT << 18)   /**< Shifted mode DEFAULT for ETM_ETMIDR */
+#define ETM_ETMIDR_SECEXT                             (0x1UL << 19)                        /**< Security Extension Support */
+#define _ETM_ETMIDR_SECEXT_SHIFT                      19                                   /**< Shift value for ETM_SECEXT */
+#define _ETM_ETMIDR_SECEXT_MASK                       0x80000UL                            /**< Bit mask for ETM_SECEXT */
+#define _ETM_ETMIDR_SECEXT_DEFAULT                    0x00000000UL                         /**< Mode DEFAULT for ETM_ETMIDR */
+#define ETM_ETMIDR_SECEXT_DEFAULT                     (_ETM_ETMIDR_SECEXT_DEFAULT << 19)   /**< Shifted mode DEFAULT for ETM_ETMIDR */
+#define ETM_ETMIDR_BPE                                (0x1UL << 20)                        /**< Branch Packet Encoding */
+#define _ETM_ETMIDR_BPE_SHIFT                         20                                   /**< Shift value for ETM_BPE */
+#define _ETM_ETMIDR_BPE_MASK                          0x100000UL                           /**< Bit mask for ETM_BPE */
+#define _ETM_ETMIDR_BPE_DEFAULT                       0x00000001UL                         /**< Mode DEFAULT for ETM_ETMIDR */
+#define ETM_ETMIDR_BPE_DEFAULT                        (_ETM_ETMIDR_BPE_DEFAULT << 20)      /**< Shifted mode DEFAULT for ETM_ETMIDR */
+#define _ETM_ETMIDR_IMPCODE_SHIFT                     24                                   /**< Shift value for ETM_IMPCODE */
+#define _ETM_ETMIDR_IMPCODE_MASK                      0xFF000000UL                         /**< Bit mask for ETM_IMPCODE */
+#define _ETM_ETMIDR_IMPCODE_DEFAULT                   0x00000041UL                         /**< Mode DEFAULT for ETM_ETMIDR */
+#define ETM_ETMIDR_IMPCODE_DEFAULT                    (_ETM_ETMIDR_IMPCODE_DEFAULT << 24)  /**< Shifted mode DEFAULT for ETM_ETMIDR */
+
+/* Bit fields for ETM ETMCCER */
+#define _ETM_ETMCCER_RESETVALUE                       0x18541800UL                           /**< Default value for ETM_ETMCCER */
+#define _ETM_ETMCCER_MASK                             0x387FFFFBUL                           /**< Mask for ETM_ETMCCER */
+#define _ETM_ETMCCER_EXTINPSEL_SHIFT                  0                                      /**< Shift value for ETM_EXTINPSEL */
+#define _ETM_ETMCCER_EXTINPSEL_MASK                   0x3UL                                  /**< Bit mask for ETM_EXTINPSEL */
+#define _ETM_ETMCCER_EXTINPSEL_DEFAULT                0x00000000UL                           /**< Mode DEFAULT for ETM_ETMCCER */
+#define ETM_ETMCCER_EXTINPSEL_DEFAULT                 (_ETM_ETMCCER_EXTINPSEL_DEFAULT << 0)  /**< Shifted mode DEFAULT for ETM_ETMCCER */
+#define _ETM_ETMCCER_EXTINPBUS_SHIFT                  3                                      /**< Shift value for ETM_EXTINPBUS */
+#define _ETM_ETMCCER_EXTINPBUS_MASK                   0x7F8UL                                /**< Bit mask for ETM_EXTINPBUS */
+#define _ETM_ETMCCER_EXTINPBUS_DEFAULT                0x00000000UL                           /**< Mode DEFAULT for ETM_ETMCCER */
+#define ETM_ETMCCER_EXTINPBUS_DEFAULT                 (_ETM_ETMCCER_EXTINPBUS_DEFAULT << 3)  /**< Shifted mode DEFAULT for ETM_ETMCCER */
+#define ETM_ETMCCER_READREGS                          (0x1UL << 11)                          /**< Readable Registers */
+#define _ETM_ETMCCER_READREGS_SHIFT                   11                                     /**< Shift value for ETM_READREGS */
+#define _ETM_ETMCCER_READREGS_MASK                    0x800UL                                /**< Bit mask for ETM_READREGS */
+#define _ETM_ETMCCER_READREGS_DEFAULT                 0x00000001UL                           /**< Mode DEFAULT for ETM_ETMCCER */
+#define ETM_ETMCCER_READREGS_DEFAULT                  (_ETM_ETMCCER_READREGS_DEFAULT << 11)  /**< Shifted mode DEFAULT for ETM_ETMCCER */
+#define ETM_ETMCCER_DADDRCMP                          (0x1UL << 12)                          /**< Data Address comparisons */
+#define _ETM_ETMCCER_DADDRCMP_SHIFT                   12                                     /**< Shift value for ETM_DADDRCMP */
+#define _ETM_ETMCCER_DADDRCMP_MASK                    0x1000UL                               /**< Bit mask for ETM_DADDRCMP */
+#define _ETM_ETMCCER_DADDRCMP_DEFAULT                 0x00000001UL                           /**< Mode DEFAULT for ETM_ETMCCER */
+#define ETM_ETMCCER_DADDRCMP_DEFAULT                  (_ETM_ETMCCER_DADDRCMP_DEFAULT << 12)  /**< Shifted mode DEFAULT for ETM_ETMCCER */
+#define _ETM_ETMCCER_INSTRES_SHIFT                    13                                     /**< Shift value for ETM_INSTRES */
+#define _ETM_ETMCCER_INSTRES_MASK                     0xE000UL                               /**< Bit mask for ETM_INSTRES */
+#define _ETM_ETMCCER_INSTRES_DEFAULT                  0x00000000UL                           /**< Mode DEFAULT for ETM_ETMCCER */
+#define ETM_ETMCCER_INSTRES_DEFAULT                   (_ETM_ETMCCER_INSTRES_DEFAULT << 13)   /**< Shifted mode DEFAULT for ETM_ETMCCER */
+#define _ETM_ETMCCER_EICEWPNT_SHIFT                   16                                     /**< Shift value for ETM_EICEWPNT */
+#define _ETM_ETMCCER_EICEWPNT_MASK                    0xF0000UL                              /**< Bit mask for ETM_EICEWPNT */
+#define _ETM_ETMCCER_EICEWPNT_DEFAULT                 0x00000004UL                           /**< Mode DEFAULT for ETM_ETMCCER */
+#define ETM_ETMCCER_EICEWPNT_DEFAULT                  (_ETM_ETMCCER_EICEWPNT_DEFAULT << 16)  /**< Shifted mode DEFAULT for ETM_ETMCCER */
+#define ETM_ETMCCER_TEICEWPNT                         (0x1UL << 20)                          /**< Trace Sart/Stop Block Uses EmbeddedICE watchpoint inputs */
+#define _ETM_ETMCCER_TEICEWPNT_SHIFT                  20                                     /**< Shift value for ETM_TEICEWPNT */
+#define _ETM_ETMCCER_TEICEWPNT_MASK                   0x100000UL                             /**< Bit mask for ETM_TEICEWPNT */
+#define _ETM_ETMCCER_TEICEWPNT_DEFAULT                0x00000001UL                           /**< Mode DEFAULT for ETM_ETMCCER */
+#define ETM_ETMCCER_TEICEWPNT_DEFAULT                 (_ETM_ETMCCER_TEICEWPNT_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMCCER */
+#define ETM_ETMCCER_EICEIMP                           (0x1UL << 21)                          /**< EmbeddedICE Behavior control Implemented */
+#define _ETM_ETMCCER_EICEIMP_SHIFT                    21                                     /**< Shift value for ETM_EICEIMP */
+#define _ETM_ETMCCER_EICEIMP_MASK                     0x200000UL                             /**< Bit mask for ETM_EICEIMP */
+#define _ETM_ETMCCER_EICEIMP_DEFAULT                  0x00000000UL                           /**< Mode DEFAULT for ETM_ETMCCER */
+#define ETM_ETMCCER_EICEIMP_DEFAULT                   (_ETM_ETMCCER_EICEIMP_DEFAULT << 21)   /**< Shifted mode DEFAULT for ETM_ETMCCER */
+#define ETM_ETMCCER_TIMP                              (0x1UL << 22)                          /**< Timestamping Implemented */
+#define _ETM_ETMCCER_TIMP_SHIFT                       22                                     /**< Shift value for ETM_TIMP */
+#define _ETM_ETMCCER_TIMP_MASK                        0x400000UL                             /**< Bit mask for ETM_TIMP */
+#define _ETM_ETMCCER_TIMP_DEFAULT                     0x00000001UL                           /**< Mode DEFAULT for ETM_ETMCCER */
+#define ETM_ETMCCER_TIMP_DEFAULT                      (_ETM_ETMCCER_TIMP_DEFAULT << 22)      /**< Shifted mode DEFAULT for ETM_ETMCCER */
+#define ETM_ETMCCER_RFCNT                             (0x1UL << 27)                          /**< Reduced Function Counter */
+#define _ETM_ETMCCER_RFCNT_SHIFT                      27                                     /**< Shift value for ETM_RFCNT */
+#define _ETM_ETMCCER_RFCNT_MASK                       0x8000000UL                            /**< Bit mask for ETM_RFCNT */
+#define _ETM_ETMCCER_RFCNT_DEFAULT                    0x00000001UL                           /**< Mode DEFAULT for ETM_ETMCCER */
+#define ETM_ETMCCER_RFCNT_DEFAULT                     (_ETM_ETMCCER_RFCNT_DEFAULT << 27)     /**< Shifted mode DEFAULT for ETM_ETMCCER */
+#define ETM_ETMCCER_TENC                              (0x1UL << 28)                          /**< Timestamp Encoding */
+#define _ETM_ETMCCER_TENC_SHIFT                       28                                     /**< Shift value for ETM_TENC */
+#define _ETM_ETMCCER_TENC_MASK                        0x10000000UL                           /**< Bit mask for ETM_TENC */
+#define _ETM_ETMCCER_TENC_DEFAULT                     0x00000001UL                           /**< Mode DEFAULT for ETM_ETMCCER */
+#define ETM_ETMCCER_TENC_DEFAULT                      (_ETM_ETMCCER_TENC_DEFAULT << 28)      /**< Shifted mode DEFAULT for ETM_ETMCCER */
+#define ETM_ETMCCER_TSIZE                             (0x1UL << 29)                          /**< Timestamp Size */
+#define _ETM_ETMCCER_TSIZE_SHIFT                      29                                     /**< Shift value for ETM_TSIZE */
+#define _ETM_ETMCCER_TSIZE_MASK                       0x20000000UL                           /**< Bit mask for ETM_TSIZE */
+#define _ETM_ETMCCER_TSIZE_DEFAULT                    0x00000000UL                           /**< Mode DEFAULT for ETM_ETMCCER */
+#define ETM_ETMCCER_TSIZE_DEFAULT                     (_ETM_ETMCCER_TSIZE_DEFAULT << 29)     /**< Shifted mode DEFAULT for ETM_ETMCCER */
+
+/* Bit fields for ETM ETMTESSEICR */
+#define _ETM_ETMTESSEICR_RESETVALUE                   0x00000000UL                              /**< Default value for ETM_ETMTESSEICR */
+#define _ETM_ETMTESSEICR_MASK                         0x000F000FUL                              /**< Mask for ETM_ETMTESSEICR */
+#define _ETM_ETMTESSEICR_STARTRSEL_SHIFT              0                                         /**< Shift value for ETM_STARTRSEL */
+#define _ETM_ETMTESSEICR_STARTRSEL_MASK               0xFUL                                     /**< Bit mask for ETM_STARTRSEL */
+#define _ETM_ETMTESSEICR_STARTRSEL_DEFAULT            0x00000000UL                              /**< Mode DEFAULT for ETM_ETMTESSEICR */
+#define ETM_ETMTESSEICR_STARTRSEL_DEFAULT             (_ETM_ETMTESSEICR_STARTRSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTESSEICR */
+#define _ETM_ETMTESSEICR_STOPRSEL_SHIFT               16                                        /**< Shift value for ETM_STOPRSEL */
+#define _ETM_ETMTESSEICR_STOPRSEL_MASK                0xF0000UL                                 /**< Bit mask for ETM_STOPRSEL */
+#define _ETM_ETMTESSEICR_STOPRSEL_DEFAULT             0x00000000UL                              /**< Mode DEFAULT for ETM_ETMTESSEICR */
+#define ETM_ETMTESSEICR_STOPRSEL_DEFAULT              (_ETM_ETMTESSEICR_STOPRSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMTESSEICR */
+
+/* Bit fields for ETM ETMTSEVR */
+#define _ETM_ETMTSEVR_RESETVALUE                      0x00000000UL                            /**< Default value for ETM_ETMTSEVR */
+#define _ETM_ETMTSEVR_MASK                            0x0001FFFFUL                            /**< Mask for ETM_ETMTSEVR */
+#define _ETM_ETMTSEVR_RESAEVT_SHIFT                   0                                       /**< Shift value for ETM_RESAEVT */
+#define _ETM_ETMTSEVR_RESAEVT_MASK                    0x7FUL                                  /**< Bit mask for ETM_RESAEVT */
+#define _ETM_ETMTSEVR_RESAEVT_DEFAULT                 0x00000000UL                            /**< Mode DEFAULT for ETM_ETMTSEVR */
+#define ETM_ETMTSEVR_RESAEVT_DEFAULT                  (_ETM_ETMTSEVR_RESAEVT_DEFAULT << 0)    /**< Shifted mode DEFAULT for ETM_ETMTSEVR */
+#define _ETM_ETMTSEVR_RESBEVT_SHIFT                   7                                       /**< Shift value for ETM_RESBEVT */
+#define _ETM_ETMTSEVR_RESBEVT_MASK                    0x3F80UL                                /**< Bit mask for ETM_RESBEVT */
+#define _ETM_ETMTSEVR_RESBEVT_DEFAULT                 0x00000000UL                            /**< Mode DEFAULT for ETM_ETMTSEVR */
+#define ETM_ETMTSEVR_RESBEVT_DEFAULT                  (_ETM_ETMTSEVR_RESBEVT_DEFAULT << 7)    /**< Shifted mode DEFAULT for ETM_ETMTSEVR */
+#define _ETM_ETMTSEVR_ETMFCNEVT_SHIFT                 14                                      /**< Shift value for ETM_ETMFCNEVT */
+#define _ETM_ETMTSEVR_ETMFCNEVT_MASK                  0x1C000UL                               /**< Bit mask for ETM_ETMFCNEVT */
+#define _ETM_ETMTSEVR_ETMFCNEVT_DEFAULT               0x00000000UL                            /**< Mode DEFAULT for ETM_ETMTSEVR */
+#define ETM_ETMTSEVR_ETMFCNEVT_DEFAULT                (_ETM_ETMTSEVR_ETMFCNEVT_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */
+
+/* Bit fields for ETM ETMTRACEIDR */
+#define _ETM_ETMTRACEIDR_RESETVALUE                   0x00000000UL                            /**< Default value for ETM_ETMTRACEIDR */
+#define _ETM_ETMTRACEIDR_MASK                         0x0000007FUL                            /**< Mask for ETM_ETMTRACEIDR */
+#define _ETM_ETMTRACEIDR_TRACEID_SHIFT                0                                       /**< Shift value for ETM_TRACEID */
+#define _ETM_ETMTRACEIDR_TRACEID_MASK                 0x7FUL                                  /**< Bit mask for ETM_TRACEID */
+#define _ETM_ETMTRACEIDR_TRACEID_DEFAULT              0x00000000UL                            /**< Mode DEFAULT for ETM_ETMTRACEIDR */
+#define ETM_ETMTRACEIDR_TRACEID_DEFAULT               (_ETM_ETMTRACEIDR_TRACEID_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTRACEIDR */
+
+/* Bit fields for ETM ETMIDR2 */
+#define _ETM_ETMIDR2_RESETVALUE                       0x00000000UL                    /**< Default value for ETM_ETMIDR2 */
+#define _ETM_ETMIDR2_MASK                             0x00000003UL                    /**< Mask for ETM_ETMIDR2 */
+#define ETM_ETMIDR2_RFE                               (0x1UL << 0)                    /**< RFE Transfer Order */
+#define _ETM_ETMIDR2_RFE_SHIFT                        0                               /**< Shift value for ETM_RFE */
+#define _ETM_ETMIDR2_RFE_MASK                         0x1UL                           /**< Bit mask for ETM_RFE */
+#define _ETM_ETMIDR2_RFE_DEFAULT                      0x00000000UL                    /**< Mode DEFAULT for ETM_ETMIDR2 */
+#define _ETM_ETMIDR2_RFE_PC                           0x00000000UL                    /**< Mode PC for ETM_ETMIDR2 */
+#define _ETM_ETMIDR2_RFE_CPSR                         0x00000001UL                    /**< Mode CPSR for ETM_ETMIDR2 */
+#define ETM_ETMIDR2_RFE_DEFAULT                       (_ETM_ETMIDR2_RFE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMIDR2 */
+#define ETM_ETMIDR2_RFE_PC                            (_ETM_ETMIDR2_RFE_PC << 0)      /**< Shifted mode PC for ETM_ETMIDR2 */
+#define ETM_ETMIDR2_RFE_CPSR                          (_ETM_ETMIDR2_RFE_CPSR << 0)    /**< Shifted mode CPSR for ETM_ETMIDR2 */
+#define ETM_ETMIDR2_SWP                               (0x1UL << 1)                    /**< SWP Transfer Order */
+#define _ETM_ETMIDR2_SWP_SHIFT                        1                               /**< Shift value for ETM_SWP */
+#define _ETM_ETMIDR2_SWP_MASK                         0x2UL                           /**< Bit mask for ETM_SWP */
+#define _ETM_ETMIDR2_SWP_DEFAULT                      0x00000000UL                    /**< Mode DEFAULT for ETM_ETMIDR2 */
+#define _ETM_ETMIDR2_SWP_LOAD                         0x00000000UL                    /**< Mode LOAD for ETM_ETMIDR2 */
+#define _ETM_ETMIDR2_SWP_STORE                        0x00000001UL                    /**< Mode STORE for ETM_ETMIDR2 */
+#define ETM_ETMIDR2_SWP_DEFAULT                       (_ETM_ETMIDR2_SWP_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMIDR2 */
+#define ETM_ETMIDR2_SWP_LOAD                          (_ETM_ETMIDR2_SWP_LOAD << 1)    /**< Shifted mode LOAD for ETM_ETMIDR2 */
+#define ETM_ETMIDR2_SWP_STORE                         (_ETM_ETMIDR2_SWP_STORE << 1)   /**< Shifted mode STORE for ETM_ETMIDR2 */
+
+/* Bit fields for ETM ETMPDSR */
+#define _ETM_ETMPDSR_RESETVALUE                       0x00000001UL                      /**< Default value for ETM_ETMPDSR */
+#define _ETM_ETMPDSR_MASK                             0x00000001UL                      /**< Mask for ETM_ETMPDSR */
+#define ETM_ETMPDSR_ETMUP                             (0x1UL << 0)                      /**< ETM Powered Up */
+#define _ETM_ETMPDSR_ETMUP_SHIFT                      0                                 /**< Shift value for ETM_ETMUP */
+#define _ETM_ETMPDSR_ETMUP_MASK                       0x1UL                             /**< Bit mask for ETM_ETMUP */
+#define _ETM_ETMPDSR_ETMUP_DEFAULT                    0x00000001UL                      /**< Mode DEFAULT for ETM_ETMPDSR */
+#define ETM_ETMPDSR_ETMUP_DEFAULT                     (_ETM_ETMPDSR_ETMUP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPDSR */
+
+/* Bit fields for ETM ETMISCIN */
+#define _ETM_ETMISCIN_RESETVALUE                      0x00000000UL                          /**< Default value for ETM_ETMISCIN */
+#define _ETM_ETMISCIN_MASK                            0x00000013UL                          /**< Mask for ETM_ETMISCIN */
+#define _ETM_ETMISCIN_EXTIN_SHIFT                     0                                     /**< Shift value for ETM_EXTIN */
+#define _ETM_ETMISCIN_EXTIN_MASK                      0x3UL                                 /**< Bit mask for ETM_EXTIN */
+#define _ETM_ETMISCIN_EXTIN_DEFAULT                   0x00000000UL                          /**< Mode DEFAULT for ETM_ETMISCIN */
+#define ETM_ETMISCIN_EXTIN_DEFAULT                    (_ETM_ETMISCIN_EXTIN_DEFAULT << 0)    /**< Shifted mode DEFAULT for ETM_ETMISCIN */
+#define ETM_ETMISCIN_COREHALT                         (0x1UL << 4)                          /**< Core Halt */
+#define _ETM_ETMISCIN_COREHALT_SHIFT                  4                                     /**< Shift value for ETM_COREHALT */
+#define _ETM_ETMISCIN_COREHALT_MASK                   0x10UL                                /**< Bit mask for ETM_COREHALT */
+#define _ETM_ETMISCIN_COREHALT_DEFAULT                0x00000000UL                          /**< Mode DEFAULT for ETM_ETMISCIN */
+#define ETM_ETMISCIN_COREHALT_DEFAULT                 (_ETM_ETMISCIN_COREHALT_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMISCIN */
+
+/* Bit fields for ETM ITTRIGOUT */
+#define _ETM_ITTRIGOUT_RESETVALUE                     0x00000000UL                             /**< Default value for ETM_ITTRIGOUT */
+#define _ETM_ITTRIGOUT_MASK                           0x00000001UL                             /**< Mask for ETM_ITTRIGOUT */
+#define ETM_ITTRIGOUT_TRIGGEROUT                      (0x1UL << 0)                             /**< Trigger output value */
+#define _ETM_ITTRIGOUT_TRIGGEROUT_SHIFT               0                                        /**< Shift value for ETM_TRIGGEROUT */
+#define _ETM_ITTRIGOUT_TRIGGEROUT_MASK                0x1UL                                    /**< Bit mask for ETM_TRIGGEROUT */
+#define _ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT             0x00000000UL                             /**< Mode DEFAULT for ETM_ITTRIGOUT */
+#define ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT              (_ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ITTRIGOUT */
+
+/* Bit fields for ETM ETMITATBCTR2 */
+#define _ETM_ETMITATBCTR2_RESETVALUE                  0x00000001UL                             /**< Default value for ETM_ETMITATBCTR2 */
+#define _ETM_ETMITATBCTR2_MASK                        0x00000001UL                             /**< Mask for ETM_ETMITATBCTR2 */
+#define ETM_ETMITATBCTR2_ATREADY                      (0x1UL << 0)                             /**< ATREADY Input Value */
+#define _ETM_ETMITATBCTR2_ATREADY_SHIFT               0                                        /**< Shift value for ETM_ATREADY */
+#define _ETM_ETMITATBCTR2_ATREADY_MASK                0x1UL                                    /**< Bit mask for ETM_ATREADY */
+#define _ETM_ETMITATBCTR2_ATREADY_DEFAULT             0x00000001UL                             /**< Mode DEFAULT for ETM_ETMITATBCTR2 */
+#define ETM_ETMITATBCTR2_ATREADY_DEFAULT              (_ETM_ETMITATBCTR2_ATREADY_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITATBCTR2 */
+
+/* Bit fields for ETM ETMITATBCTR0 */
+#define _ETM_ETMITATBCTR0_RESETVALUE                  0x00000000UL                             /**< Default value for ETM_ETMITATBCTR0 */
+#define _ETM_ETMITATBCTR0_MASK                        0x00000001UL                             /**< Mask for ETM_ETMITATBCTR0 */
+#define ETM_ETMITATBCTR0_ATVALID                      (0x1UL << 0)                             /**< ATVALID Output Value */
+#define _ETM_ETMITATBCTR0_ATVALID_SHIFT               0                                        /**< Shift value for ETM_ATVALID */
+#define _ETM_ETMITATBCTR0_ATVALID_MASK                0x1UL                                    /**< Bit mask for ETM_ATVALID */
+#define _ETM_ETMITATBCTR0_ATVALID_DEFAULT             0x00000000UL                             /**< Mode DEFAULT for ETM_ETMITATBCTR0 */
+#define ETM_ETMITATBCTR0_ATVALID_DEFAULT              (_ETM_ETMITATBCTR0_ATVALID_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITATBCTR0 */
+
+/* Bit fields for ETM ETMITCTRL */
+#define _ETM_ETMITCTRL_RESETVALUE                     0x00000000UL                       /**< Default value for ETM_ETMITCTRL */
+#define _ETM_ETMITCTRL_MASK                           0x00000001UL                       /**< Mask for ETM_ETMITCTRL */
+#define ETM_ETMITCTRL_ITEN                            (0x1UL << 0)                       /**< Integration Mode Enable */
+#define _ETM_ETMITCTRL_ITEN_SHIFT                     0                                  /**< Shift value for ETM_ITEN */
+#define _ETM_ETMITCTRL_ITEN_MASK                      0x1UL                              /**< Bit mask for ETM_ITEN */
+#define _ETM_ETMITCTRL_ITEN_DEFAULT                   0x00000000UL                       /**< Mode DEFAULT for ETM_ETMITCTRL */
+#define ETM_ETMITCTRL_ITEN_DEFAULT                    (_ETM_ETMITCTRL_ITEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITCTRL */
+
+/* Bit fields for ETM ETMCLAIMSET */
+#define _ETM_ETMCLAIMSET_RESETVALUE                   0x0000000FUL                           /**< Default value for ETM_ETMCLAIMSET */
+#define _ETM_ETMCLAIMSET_MASK                         0x000000FFUL                           /**< Mask for ETM_ETMCLAIMSET */
+#define _ETM_ETMCLAIMSET_SETTAG_SHIFT                 0                                      /**< Shift value for ETM_SETTAG */
+#define _ETM_ETMCLAIMSET_SETTAG_MASK                  0xFFUL                                 /**< Bit mask for ETM_SETTAG */
+#define _ETM_ETMCLAIMSET_SETTAG_DEFAULT               0x0000000FUL                           /**< Mode DEFAULT for ETM_ETMCLAIMSET */
+#define ETM_ETMCLAIMSET_SETTAG_DEFAULT                (_ETM_ETMCLAIMSET_SETTAG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCLAIMSET */
+
+/* Bit fields for ETM ETMCLAIMCLR */
+#define _ETM_ETMCLAIMCLR_RESETVALUE                   0x00000000UL                           /**< Default value for ETM_ETMCLAIMCLR */
+#define _ETM_ETMCLAIMCLR_MASK                         0x00000001UL                           /**< Mask for ETM_ETMCLAIMCLR */
+#define ETM_ETMCLAIMCLR_CLRTAG                        (0x1UL << 0)                           /**< Tag Bits */
+#define _ETM_ETMCLAIMCLR_CLRTAG_SHIFT                 0                                      /**< Shift value for ETM_CLRTAG */
+#define _ETM_ETMCLAIMCLR_CLRTAG_MASK                  0x1UL                                  /**< Bit mask for ETM_CLRTAG */
+#define _ETM_ETMCLAIMCLR_CLRTAG_DEFAULT               0x00000000UL                           /**< Mode DEFAULT for ETM_ETMCLAIMCLR */
+#define ETM_ETMCLAIMCLR_CLRTAG_DEFAULT                (_ETM_ETMCLAIMCLR_CLRTAG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCLAIMCLR */
+
+/* Bit fields for ETM ETMLAR */
+#define _ETM_ETMLAR_RESETVALUE                        0x00000000UL                   /**< Default value for ETM_ETMLAR */
+#define _ETM_ETMLAR_MASK                              0x00000001UL                   /**< Mask for ETM_ETMLAR */
+#define ETM_ETMLAR_KEY                                (0x1UL << 0)                   /**< Key Value */
+#define _ETM_ETMLAR_KEY_SHIFT                         0                              /**< Shift value for ETM_KEY */
+#define _ETM_ETMLAR_KEY_MASK                          0x1UL                          /**< Bit mask for ETM_KEY */
+#define _ETM_ETMLAR_KEY_DEFAULT                       0x00000000UL                   /**< Mode DEFAULT for ETM_ETMLAR */
+#define ETM_ETMLAR_KEY_DEFAULT                        (_ETM_ETMLAR_KEY_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMLAR */
+
+/* Bit fields for ETM ETMLSR */
+#define _ETM_ETMLSR_RESETVALUE                        0x00000003UL                       /**< Default value for ETM_ETMLSR */
+#define _ETM_ETMLSR_MASK                              0x00000003UL                       /**< Mask for ETM_ETMLSR */
+#define ETM_ETMLSR_LOCKIMP                            (0x1UL << 0)                       /**< ETM Locking Implemented */
+#define _ETM_ETMLSR_LOCKIMP_SHIFT                     0                                  /**< Shift value for ETM_LOCKIMP */
+#define _ETM_ETMLSR_LOCKIMP_MASK                      0x1UL                              /**< Bit mask for ETM_LOCKIMP */
+#define _ETM_ETMLSR_LOCKIMP_DEFAULT                   0x00000001UL                       /**< Mode DEFAULT for ETM_ETMLSR */
+#define ETM_ETMLSR_LOCKIMP_DEFAULT                    (_ETM_ETMLSR_LOCKIMP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMLSR */
+#define ETM_ETMLSR_LOCKED                             (0x1UL << 1)                       /**< ETM locked */
+#define _ETM_ETMLSR_LOCKED_SHIFT                      1                                  /**< Shift value for ETM_LOCKED */
+#define _ETM_ETMLSR_LOCKED_MASK                       0x2UL                              /**< Bit mask for ETM_LOCKED */
+#define _ETM_ETMLSR_LOCKED_DEFAULT                    0x00000001UL                       /**< Mode DEFAULT for ETM_ETMLSR */
+#define ETM_ETMLSR_LOCKED_DEFAULT                     (_ETM_ETMLSR_LOCKED_DEFAULT << 1)  /**< Shifted mode DEFAULT for ETM_ETMLSR */
+
+/* Bit fields for ETM ETMAUTHSTATUS */
+#define _ETM_ETMAUTHSTATUS_RESETVALUE                 0x000000C0UL                                      /**< Default value for ETM_ETMAUTHSTATUS */
+#define _ETM_ETMAUTHSTATUS_MASK                       0x000000FFUL                                      /**< Mask for ETM_ETMAUTHSTATUS */
+#define _ETM_ETMAUTHSTATUS_NONSECINVDBG_SHIFT         0                                                 /**< Shift value for ETM_NONSECINVDBG */
+#define _ETM_ETMAUTHSTATUS_NONSECINVDBG_MASK          0x3UL                                             /**< Bit mask for ETM_NONSECINVDBG */
+#define _ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT       0x00000000UL                                      /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */
+#define ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT        (_ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT << 0)    /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */
+#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_SHIFT      2                                                 /**< Shift value for ETM_NONSECNONINVDBG */
+#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_MASK       0xCUL                                             /**< Bit mask for ETM_NONSECNONINVDBG */
+#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT    0x00000000UL                                      /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */
+#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE    0x00000002UL                                      /**< Mode DISABLE for ETM_ETMAUTHSTATUS */
+#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE     0x00000003UL                                      /**< Mode ENABLE for ETM_ETMAUTHSTATUS */
+#define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT     (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT << 2) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */
+#define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE     (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE << 2) /**< Shifted mode DISABLE for ETM_ETMAUTHSTATUS */
+#define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE      (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE << 2)  /**< Shifted mode ENABLE for ETM_ETMAUTHSTATUS */
+#define _ETM_ETMAUTHSTATUS_SECINVDBG_SHIFT            4                                                 /**< Shift value for ETM_SECINVDBG */
+#define _ETM_ETMAUTHSTATUS_SECINVDBG_MASK             0x30UL                                            /**< Bit mask for ETM_SECINVDBG */
+#define _ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT          0x00000000UL                                      /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */
+#define ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT           (_ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT << 4)       /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */
+#define _ETM_ETMAUTHSTATUS_SECNONINVDBG_SHIFT         6                                                 /**< Shift value for ETM_SECNONINVDBG */
+#define _ETM_ETMAUTHSTATUS_SECNONINVDBG_MASK          0xC0UL                                            /**< Bit mask for ETM_SECNONINVDBG */
+#define _ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT       0x00000003UL                                      /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */
+#define ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT        (_ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT << 6)    /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */
+
+/* Bit fields for ETM ETMDEVTYPE */
+#define _ETM_ETMDEVTYPE_RESETVALUE                    0x00000013UL                             /**< Default value for ETM_ETMDEVTYPE */
+#define _ETM_ETMDEVTYPE_MASK                          0x000000FFUL                             /**< Mask for ETM_ETMDEVTYPE */
+#define _ETM_ETMDEVTYPE_TRACESRC_SHIFT                0                                        /**< Shift value for ETM_TRACESRC */
+#define _ETM_ETMDEVTYPE_TRACESRC_MASK                 0xFUL                                    /**< Bit mask for ETM_TRACESRC */
+#define _ETM_ETMDEVTYPE_TRACESRC_DEFAULT              0x00000003UL                             /**< Mode DEFAULT for ETM_ETMDEVTYPE */
+#define ETM_ETMDEVTYPE_TRACESRC_DEFAULT               (_ETM_ETMDEVTYPE_TRACESRC_DEFAULT << 0)  /**< Shifted mode DEFAULT for ETM_ETMDEVTYPE */
+#define _ETM_ETMDEVTYPE_PROCTRACE_SHIFT               4                                        /**< Shift value for ETM_PROCTRACE */
+#define _ETM_ETMDEVTYPE_PROCTRACE_MASK                0xF0UL                                   /**< Bit mask for ETM_PROCTRACE */
+#define _ETM_ETMDEVTYPE_PROCTRACE_DEFAULT             0x00000001UL                             /**< Mode DEFAULT for ETM_ETMDEVTYPE */
+#define ETM_ETMDEVTYPE_PROCTRACE_DEFAULT              (_ETM_ETMDEVTYPE_PROCTRACE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMDEVTYPE */
+
+/* Bit fields for ETM ETMPIDR4 */
+#define _ETM_ETMPIDR4_RESETVALUE                      0x00000004UL                          /**< Default value for ETM_ETMPIDR4 */
+#define _ETM_ETMPIDR4_MASK                            0x000000FFUL                          /**< Mask for ETM_ETMPIDR4 */
+#define _ETM_ETMPIDR4_CONTCODE_SHIFT                  0                                     /**< Shift value for ETM_CONTCODE */
+#define _ETM_ETMPIDR4_CONTCODE_MASK                   0xFUL                                 /**< Bit mask for ETM_CONTCODE */
+#define _ETM_ETMPIDR4_CONTCODE_DEFAULT                0x00000004UL                          /**< Mode DEFAULT for ETM_ETMPIDR4 */
+#define ETM_ETMPIDR4_CONTCODE_DEFAULT                 (_ETM_ETMPIDR4_CONTCODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR4 */
+#define _ETM_ETMPIDR4_COUNT_SHIFT                     4                                     /**< Shift value for ETM_COUNT */
+#define _ETM_ETMPIDR4_COUNT_MASK                      0xF0UL                                /**< Bit mask for ETM_COUNT */
+#define _ETM_ETMPIDR4_COUNT_DEFAULT                   0x00000000UL                          /**< Mode DEFAULT for ETM_ETMPIDR4 */
+#define ETM_ETMPIDR4_COUNT_DEFAULT                    (_ETM_ETMPIDR4_COUNT_DEFAULT << 4)    /**< Shifted mode DEFAULT for ETM_ETMPIDR4 */
+
+/* Bit fields for ETM ETMPIDR5 */
+#define _ETM_ETMPIDR5_RESETVALUE                      0x00000000UL /**< Default value for ETM_ETMPIDR5 */
+#define _ETM_ETMPIDR5_MASK                            0x00000000UL /**< Mask for ETM_ETMPIDR5 */
+
+/* Bit fields for ETM ETMPIDR6 */
+#define _ETM_ETMPIDR6_RESETVALUE                      0x00000000UL /**< Default value for ETM_ETMPIDR6 */
+#define _ETM_ETMPIDR6_MASK                            0x00000000UL /**< Mask for ETM_ETMPIDR6 */
+
+/* Bit fields for ETM ETMPIDR7 */
+#define _ETM_ETMPIDR7_RESETVALUE                      0x00000000UL /**< Default value for ETM_ETMPIDR7 */
+#define _ETM_ETMPIDR7_MASK                            0x00000000UL /**< Mask for ETM_ETMPIDR7 */
+
+/* Bit fields for ETM ETMPIDR0 */
+#define _ETM_ETMPIDR0_RESETVALUE                      0x00000025UL                         /**< Default value for ETM_ETMPIDR0 */
+#define _ETM_ETMPIDR0_MASK                            0x000000FFUL                         /**< Mask for ETM_ETMPIDR0 */
+#define _ETM_ETMPIDR0_PARTNUM_SHIFT                   0                                    /**< Shift value for ETM_PARTNUM */
+#define _ETM_ETMPIDR0_PARTNUM_MASK                    0xFFUL                               /**< Bit mask for ETM_PARTNUM */
+#define _ETM_ETMPIDR0_PARTNUM_DEFAULT                 0x00000025UL                         /**< Mode DEFAULT for ETM_ETMPIDR0 */
+#define ETM_ETMPIDR0_PARTNUM_DEFAULT                  (_ETM_ETMPIDR0_PARTNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR0 */
+
+/* Bit fields for ETM ETMPIDR1 */
+#define _ETM_ETMPIDR1_RESETVALUE                      0x000000B9UL                         /**< Default value for ETM_ETMPIDR1 */
+#define _ETM_ETMPIDR1_MASK                            0x000000FFUL                         /**< Mask for ETM_ETMPIDR1 */
+#define _ETM_ETMPIDR1_PARTNUM_SHIFT                   0                                    /**< Shift value for ETM_PARTNUM */
+#define _ETM_ETMPIDR1_PARTNUM_MASK                    0xFUL                                /**< Bit mask for ETM_PARTNUM */
+#define _ETM_ETMPIDR1_PARTNUM_DEFAULT                 0x00000009UL                         /**< Mode DEFAULT for ETM_ETMPIDR1 */
+#define ETM_ETMPIDR1_PARTNUM_DEFAULT                  (_ETM_ETMPIDR1_PARTNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR1 */
+#define _ETM_ETMPIDR1_IDCODE_SHIFT                    4                                    /**< Shift value for ETM_IDCODE */
+#define _ETM_ETMPIDR1_IDCODE_MASK                     0xF0UL                               /**< Bit mask for ETM_IDCODE */
+#define _ETM_ETMPIDR1_IDCODE_DEFAULT                  0x0000000BUL                         /**< Mode DEFAULT for ETM_ETMPIDR1 */
+#define ETM_ETMPIDR1_IDCODE_DEFAULT                   (_ETM_ETMPIDR1_IDCODE_DEFAULT << 4)  /**< Shifted mode DEFAULT for ETM_ETMPIDR1 */
+
+/* Bit fields for ETM ETMPIDR2 */
+#define _ETM_ETMPIDR2_RESETVALUE                      0x0000000BUL                         /**< Default value for ETM_ETMPIDR2 */
+#define _ETM_ETMPIDR2_MASK                            0x000000FFUL                         /**< Mask for ETM_ETMPIDR2 */
+#define _ETM_ETMPIDR2_IDCODE_SHIFT                    0                                    /**< Shift value for ETM_IDCODE */
+#define _ETM_ETMPIDR2_IDCODE_MASK                     0x7UL                                /**< Bit mask for ETM_IDCODE */
+#define _ETM_ETMPIDR2_IDCODE_DEFAULT                  0x00000003UL                         /**< Mode DEFAULT for ETM_ETMPIDR2 */
+#define ETM_ETMPIDR2_IDCODE_DEFAULT                   (_ETM_ETMPIDR2_IDCODE_DEFAULT << 0)  /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */
+#define ETM_ETMPIDR2_ALWAYS1                          (0x1UL << 3)                         /**< Always 1 */
+#define _ETM_ETMPIDR2_ALWAYS1_SHIFT                   3                                    /**< Shift value for ETM_ALWAYS1 */
+#define _ETM_ETMPIDR2_ALWAYS1_MASK                    0x8UL                                /**< Bit mask for ETM_ALWAYS1 */
+#define _ETM_ETMPIDR2_ALWAYS1_DEFAULT                 0x00000001UL                         /**< Mode DEFAULT for ETM_ETMPIDR2 */
+#define ETM_ETMPIDR2_ALWAYS1_DEFAULT                  (_ETM_ETMPIDR2_ALWAYS1_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */
+#define _ETM_ETMPIDR2_REV_SHIFT                       4                                    /**< Shift value for ETM_REV */
+#define _ETM_ETMPIDR2_REV_MASK                        0xF0UL                               /**< Bit mask for ETM_REV */
+#define _ETM_ETMPIDR2_REV_DEFAULT                     0x00000000UL                         /**< Mode DEFAULT for ETM_ETMPIDR2 */
+#define ETM_ETMPIDR2_REV_DEFAULT                      (_ETM_ETMPIDR2_REV_DEFAULT << 4)     /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */
+
+/* Bit fields for ETM ETMPIDR3 */
+#define _ETM_ETMPIDR3_RESETVALUE                      0x00000000UL                         /**< Default value for ETM_ETMPIDR3 */
+#define _ETM_ETMPIDR3_MASK                            0x000000FFUL                         /**< Mask for ETM_ETMPIDR3 */
+#define _ETM_ETMPIDR3_CUSTMOD_SHIFT                   0                                    /**< Shift value for ETM_CUSTMOD */
+#define _ETM_ETMPIDR3_CUSTMOD_MASK                    0xFUL                                /**< Bit mask for ETM_CUSTMOD */
+#define _ETM_ETMPIDR3_CUSTMOD_DEFAULT                 0x00000000UL                         /**< Mode DEFAULT for ETM_ETMPIDR3 */
+#define ETM_ETMPIDR3_CUSTMOD_DEFAULT                  (_ETM_ETMPIDR3_CUSTMOD_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR3 */
+#define _ETM_ETMPIDR3_REVAND_SHIFT                    4                                    /**< Shift value for ETM_REVAND */
+#define _ETM_ETMPIDR3_REVAND_MASK                     0xF0UL                               /**< Bit mask for ETM_REVAND */
+#define _ETM_ETMPIDR3_REVAND_DEFAULT                  0x00000000UL                         /**< Mode DEFAULT for ETM_ETMPIDR3 */
+#define ETM_ETMPIDR3_REVAND_DEFAULT                   (_ETM_ETMPIDR3_REVAND_DEFAULT << 4)  /**< Shifted mode DEFAULT for ETM_ETMPIDR3 */
+
+/* Bit fields for ETM ETMCIDR0 */
+#define _ETM_ETMCIDR0_RESETVALUE                      0x0000000DUL                        /**< Default value for ETM_ETMCIDR0 */
+#define _ETM_ETMCIDR0_MASK                            0x000000FFUL                        /**< Mask for ETM_ETMCIDR0 */
+#define _ETM_ETMCIDR0_PREAMB_SHIFT                    0                                   /**< Shift value for ETM_PREAMB */
+#define _ETM_ETMCIDR0_PREAMB_MASK                     0xFFUL                              /**< Bit mask for ETM_PREAMB */
+#define _ETM_ETMCIDR0_PREAMB_DEFAULT                  0x0000000DUL                        /**< Mode DEFAULT for ETM_ETMCIDR0 */
+#define ETM_ETMCIDR0_PREAMB_DEFAULT                   (_ETM_ETMCIDR0_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR0 */
+
+/* Bit fields for ETM ETMCIDR1 */
+#define _ETM_ETMCIDR1_RESETVALUE                      0x00000090UL                        /**< Default value for ETM_ETMCIDR1 */
+#define _ETM_ETMCIDR1_MASK                            0x000000FFUL                        /**< Mask for ETM_ETMCIDR1 */
+#define _ETM_ETMCIDR1_PREAMB_SHIFT                    0                                   /**< Shift value for ETM_PREAMB */
+#define _ETM_ETMCIDR1_PREAMB_MASK                     0xFFUL                              /**< Bit mask for ETM_PREAMB */
+#define _ETM_ETMCIDR1_PREAMB_DEFAULT                  0x00000090UL                        /**< Mode DEFAULT for ETM_ETMCIDR1 */
+#define ETM_ETMCIDR1_PREAMB_DEFAULT                   (_ETM_ETMCIDR1_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR1 */
+
+/* Bit fields for ETM ETMCIDR2 */
+#define _ETM_ETMCIDR2_RESETVALUE                      0x00000005UL                        /**< Default value for ETM_ETMCIDR2 */
+#define _ETM_ETMCIDR2_MASK                            0x000000FFUL                        /**< Mask for ETM_ETMCIDR2 */
+#define _ETM_ETMCIDR2_PREAMB_SHIFT                    0                                   /**< Shift value for ETM_PREAMB */
+#define _ETM_ETMCIDR2_PREAMB_MASK                     0xFFUL                              /**< Bit mask for ETM_PREAMB */
+#define _ETM_ETMCIDR2_PREAMB_DEFAULT                  0x00000005UL                        /**< Mode DEFAULT for ETM_ETMCIDR2 */
+#define ETM_ETMCIDR2_PREAMB_DEFAULT                   (_ETM_ETMCIDR2_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR2 */
+
+/* Bit fields for ETM ETMCIDR3 */
+#define _ETM_ETMCIDR3_RESETVALUE                      0x000000B1UL                        /**< Default value for ETM_ETMCIDR3 */
+#define _ETM_ETMCIDR3_MASK                            0x000000FFUL                        /**< Mask for ETM_ETMCIDR3 */
+#define _ETM_ETMCIDR3_PREAMB_SHIFT                    0                                   /**< Shift value for ETM_PREAMB */
+#define _ETM_ETMCIDR3_PREAMB_MASK                     0xFFUL                              /**< Bit mask for ETM_PREAMB */
+#define _ETM_ETMCIDR3_PREAMB_DEFAULT                  0x000000B1UL                        /**< Mode DEFAULT for ETM_ETMCIDR3 */
+#define ETM_ETMCIDR3_PREAMB_DEFAULT                   (_ETM_ETMCIDR3_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR3 */
+
+/** @} */
+/** @} End of group EFM32GG12B_ETM */
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+

cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b_fpueh.h

@@ -0,0 +1,208 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32GG12B_FPUEH register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFM32GG12B_FPUEH FPUEH
+ * @{
+ * @brief EFM32GG12B_FPUEH Register Declaration
+ ******************************************************************************/
+/** FPUEH Register Declaration */
+typedef struct {
+  __IM uint32_t  IF;  /**< Interrupt Flag Register  */
+  __IOM uint32_t IFS; /**< Interrupt Flag Set Register  */
+  __IOM uint32_t IFC; /**< Interrupt Flag Clear Register  */
+  __IOM uint32_t IEN; /**< Interrupt Enable Register  */
+} FPUEH_TypeDef;      /** @} */
+
+/***************************************************************************//**
+ * @addtogroup EFM32GG12B_FPUEH
+ * @{
+ * @defgroup EFM32GG12B_FPUEH_BitFields  FPUEH Bit Fields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for FPUEH IF */
+#define _FPUEH_IF_RESETVALUE        0x00000000UL                   /**< Default value for FPUEH_IF */
+#define _FPUEH_IF_MASK              0x0000003FUL                   /**< Mask for FPUEH_IF */
+#define FPUEH_IF_FPIOC              (0x1UL << 0)                   /**< FPU invalid operation */
+#define _FPUEH_IF_FPIOC_SHIFT       0                              /**< Shift value for FPUEH_FPIOC */
+#define _FPUEH_IF_FPIOC_MASK        0x1UL                          /**< Bit mask for FPUEH_FPIOC */
+#define _FPUEH_IF_FPIOC_DEFAULT     0x00000000UL                   /**< Mode DEFAULT for FPUEH_IF */
+#define FPUEH_IF_FPIOC_DEFAULT      (_FPUEH_IF_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IF */
+#define FPUEH_IF_FPDZC              (0x1UL << 1)                   /**< FPU divide-by-zero exception */
+#define _FPUEH_IF_FPDZC_SHIFT       1                              /**< Shift value for FPUEH_FPDZC */
+#define _FPUEH_IF_FPDZC_MASK        0x2UL                          /**< Bit mask for FPUEH_FPDZC */
+#define _FPUEH_IF_FPDZC_DEFAULT     0x00000000UL                   /**< Mode DEFAULT for FPUEH_IF */
+#define FPUEH_IF_FPDZC_DEFAULT      (_FPUEH_IF_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IF */
+#define FPUEH_IF_FPUFC              (0x1UL << 2)                   /**< FPU underflow exception */
+#define _FPUEH_IF_FPUFC_SHIFT       2                              /**< Shift value for FPUEH_FPUFC */
+#define _FPUEH_IF_FPUFC_MASK        0x4UL                          /**< Bit mask for FPUEH_FPUFC */
+#define _FPUEH_IF_FPUFC_DEFAULT     0x00000000UL                   /**< Mode DEFAULT for FPUEH_IF */
+#define FPUEH_IF_FPUFC_DEFAULT      (_FPUEH_IF_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IF */
+#define FPUEH_IF_FPOFC              (0x1UL << 3)                   /**< FPU overflow exception */
+#define _FPUEH_IF_FPOFC_SHIFT       3                              /**< Shift value for FPUEH_FPOFC */
+#define _FPUEH_IF_FPOFC_MASK        0x8UL                          /**< Bit mask for FPUEH_FPOFC */
+#define _FPUEH_IF_FPOFC_DEFAULT     0x00000000UL                   /**< Mode DEFAULT for FPUEH_IF */
+#define FPUEH_IF_FPOFC_DEFAULT      (_FPUEH_IF_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IF */
+#define FPUEH_IF_FPIDC              (0x1UL << 4)                   /**< FPU input denormal exception */
+#define _FPUEH_IF_FPIDC_SHIFT       4                              /**< Shift value for FPUEH_FPIDC */
+#define _FPUEH_IF_FPIDC_MASK        0x10UL                         /**< Bit mask for FPUEH_FPIDC */
+#define _FPUEH_IF_FPIDC_DEFAULT     0x00000000UL                   /**< Mode DEFAULT for FPUEH_IF */
+#define FPUEH_IF_FPIDC_DEFAULT      (_FPUEH_IF_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IF */
+#define FPUEH_IF_FPIXC              (0x1UL << 5)                   /**< FPU inexact exception */
+#define _FPUEH_IF_FPIXC_SHIFT       5                              /**< Shift value for FPUEH_FPIXC */
+#define _FPUEH_IF_FPIXC_MASK        0x20UL                         /**< Bit mask for FPUEH_FPIXC */
+#define _FPUEH_IF_FPIXC_DEFAULT     0x00000000UL                   /**< Mode DEFAULT for FPUEH_IF */
+#define FPUEH_IF_FPIXC_DEFAULT      (_FPUEH_IF_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IF */
+
+/* Bit fields for FPUEH IFS */
+#define _FPUEH_IFS_RESETVALUE       0x00000000UL                    /**< Default value for FPUEH_IFS */
+#define _FPUEH_IFS_MASK             0x0000003FUL                    /**< Mask for FPUEH_IFS */
+#define FPUEH_IFS_FPIOC             (0x1UL << 0)                    /**< Set FPIOC Interrupt Flag */
+#define _FPUEH_IFS_FPIOC_SHIFT      0                               /**< Shift value for FPUEH_FPIOC */
+#define _FPUEH_IFS_FPIOC_MASK       0x1UL                           /**< Bit mask for FPUEH_FPIOC */
+#define _FPUEH_IFS_FPIOC_DEFAULT    0x00000000UL                    /**< Mode DEFAULT for FPUEH_IFS */
+#define FPUEH_IFS_FPIOC_DEFAULT     (_FPUEH_IFS_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IFS */
+#define FPUEH_IFS_FPDZC             (0x1UL << 1)                    /**< Set FPDZC Interrupt Flag */
+#define _FPUEH_IFS_FPDZC_SHIFT      1                               /**< Shift value for FPUEH_FPDZC */
+#define _FPUEH_IFS_FPDZC_MASK       0x2UL                           /**< Bit mask for FPUEH_FPDZC */
+#define _FPUEH_IFS_FPDZC_DEFAULT    0x00000000UL                    /**< Mode DEFAULT for FPUEH_IFS */
+#define FPUEH_IFS_FPDZC_DEFAULT     (_FPUEH_IFS_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IFS */
+#define FPUEH_IFS_FPUFC             (0x1UL << 2)                    /**< Set FPUFC Interrupt Flag */
+#define _FPUEH_IFS_FPUFC_SHIFT      2                               /**< Shift value for FPUEH_FPUFC */
+#define _FPUEH_IFS_FPUFC_MASK       0x4UL                           /**< Bit mask for FPUEH_FPUFC */
+#define _FPUEH_IFS_FPUFC_DEFAULT    0x00000000UL                    /**< Mode DEFAULT for FPUEH_IFS */
+#define FPUEH_IFS_FPUFC_DEFAULT     (_FPUEH_IFS_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IFS */
+#define FPUEH_IFS_FPOFC             (0x1UL << 3)                    /**< Set FPOFC Interrupt Flag */
+#define _FPUEH_IFS_FPOFC_SHIFT      3                               /**< Shift value for FPUEH_FPOFC */
+#define _FPUEH_IFS_FPOFC_MASK       0x8UL                           /**< Bit mask for FPUEH_FPOFC */
+#define _FPUEH_IFS_FPOFC_DEFAULT    0x00000000UL                    /**< Mode DEFAULT for FPUEH_IFS */
+#define FPUEH_IFS_FPOFC_DEFAULT     (_FPUEH_IFS_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IFS */
+#define FPUEH_IFS_FPIDC             (0x1UL << 4)                    /**< Set FPIDC Interrupt Flag */
+#define _FPUEH_IFS_FPIDC_SHIFT      4                               /**< Shift value for FPUEH_FPIDC */
+#define _FPUEH_IFS_FPIDC_MASK       0x10UL                          /**< Bit mask for FPUEH_FPIDC */
+#define _FPUEH_IFS_FPIDC_DEFAULT    0x00000000UL                    /**< Mode DEFAULT for FPUEH_IFS */
+#define FPUEH_IFS_FPIDC_DEFAULT     (_FPUEH_IFS_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IFS */
+#define FPUEH_IFS_FPIXC             (0x1UL << 5)                    /**< Set FPIXC Interrupt Flag */
+#define _FPUEH_IFS_FPIXC_SHIFT      5                               /**< Shift value for FPUEH_FPIXC */
+#define _FPUEH_IFS_FPIXC_MASK       0x20UL                          /**< Bit mask for FPUEH_FPIXC */
+#define _FPUEH_IFS_FPIXC_DEFAULT    0x00000000UL                    /**< Mode DEFAULT for FPUEH_IFS */
+#define FPUEH_IFS_FPIXC_DEFAULT     (_FPUEH_IFS_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IFS */
+
+/* Bit fields for FPUEH IFC */
+#define _FPUEH_IFC_RESETVALUE       0x00000000UL                    /**< Default value for FPUEH_IFC */
+#define _FPUEH_IFC_MASK             0x0000003FUL                    /**< Mask for FPUEH_IFC */
+#define FPUEH_IFC_FPIOC             (0x1UL << 0)                    /**< Clear FPIOC Interrupt Flag */
+#define _FPUEH_IFC_FPIOC_SHIFT      0                               /**< Shift value for FPUEH_FPIOC */
+#define _FPUEH_IFC_FPIOC_MASK       0x1UL                           /**< Bit mask for FPUEH_FPIOC */
+#define _FPUEH_IFC_FPIOC_DEFAULT    0x00000000UL                    /**< Mode DEFAULT for FPUEH_IFC */
+#define FPUEH_IFC_FPIOC_DEFAULT     (_FPUEH_IFC_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IFC */
+#define FPUEH_IFC_FPDZC             (0x1UL << 1)                    /**< Clear FPDZC Interrupt Flag */
+#define _FPUEH_IFC_FPDZC_SHIFT      1                               /**< Shift value for FPUEH_FPDZC */
+#define _FPUEH_IFC_FPDZC_MASK       0x2UL                           /**< Bit mask for FPUEH_FPDZC */
+#define _FPUEH_IFC_FPDZC_DEFAULT    0x00000000UL                    /**< Mode DEFAULT for FPUEH_IFC */
+#define FPUEH_IFC_FPDZC_DEFAULT     (_FPUEH_IFC_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IFC */
+#define FPUEH_IFC_FPUFC             (0x1UL << 2)                    /**< Clear FPUFC Interrupt Flag */
+#define _FPUEH_IFC_FPUFC_SHIFT      2                               /**< Shift value for FPUEH_FPUFC */
+#define _FPUEH_IFC_FPUFC_MASK       0x4UL                           /**< Bit mask for FPUEH_FPUFC */
+#define _FPUEH_IFC_FPUFC_DEFAULT    0x00000000UL                    /**< Mode DEFAULT for FPUEH_IFC */
+#define FPUEH_IFC_FPUFC_DEFAULT     (_FPUEH_IFC_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IFC */
+#define FPUEH_IFC_FPOFC             (0x1UL << 3)                    /**< Clear FPOFC Interrupt Flag */
+#define _FPUEH_IFC_FPOFC_SHIFT      3                               /**< Shift value for FPUEH_FPOFC */
+#define _FPUEH_IFC_FPOFC_MASK       0x8UL                           /**< Bit mask for FPUEH_FPOFC */
+#define _FPUEH_IFC_FPOFC_DEFAULT    0x00000000UL                    /**< Mode DEFAULT for FPUEH_IFC */
+#define FPUEH_IFC_FPOFC_DEFAULT     (_FPUEH_IFC_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IFC */
+#define FPUEH_IFC_FPIDC             (0x1UL << 4)                    /**< Clear FPIDC Interrupt Flag */
+#define _FPUEH_IFC_FPIDC_SHIFT      4                               /**< Shift value for FPUEH_FPIDC */
+#define _FPUEH_IFC_FPIDC_MASK       0x10UL                          /**< Bit mask for FPUEH_FPIDC */
+#define _FPUEH_IFC_FPIDC_DEFAULT    0x00000000UL                    /**< Mode DEFAULT for FPUEH_IFC */
+#define FPUEH_IFC_FPIDC_DEFAULT     (_FPUEH_IFC_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IFC */
+#define FPUEH_IFC_FPIXC             (0x1UL << 5)                    /**< Clear FPIXC Interrupt Flag */
+#define _FPUEH_IFC_FPIXC_SHIFT      5                               /**< Shift value for FPUEH_FPIXC */
+#define _FPUEH_IFC_FPIXC_MASK       0x20UL                          /**< Bit mask for FPUEH_FPIXC */
+#define _FPUEH_IFC_FPIXC_DEFAULT    0x00000000UL                    /**< Mode DEFAULT for FPUEH_IFC */
+#define FPUEH_IFC_FPIXC_DEFAULT     (_FPUEH_IFC_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IFC */
+
+/* Bit fields for FPUEH IEN */
+#define _FPUEH_IEN_RESETVALUE       0x00000000UL                    /**< Default value for FPUEH_IEN */
+#define _FPUEH_IEN_MASK             0x0000003FUL                    /**< Mask for FPUEH_IEN */
+#define FPUEH_IEN_FPIOC             (0x1UL << 0)                    /**< FPIOC Interrupt Enable */
+#define _FPUEH_IEN_FPIOC_SHIFT      0                               /**< Shift value for FPUEH_FPIOC */
+#define _FPUEH_IEN_FPIOC_MASK       0x1UL                           /**< Bit mask for FPUEH_FPIOC */
+#define _FPUEH_IEN_FPIOC_DEFAULT    0x00000000UL                    /**< Mode DEFAULT for FPUEH_IEN */
+#define FPUEH_IEN_FPIOC_DEFAULT     (_FPUEH_IEN_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IEN */
+#define FPUEH_IEN_FPDZC             (0x1UL << 1)                    /**< FPDZC Interrupt Enable */
+#define _FPUEH_IEN_FPDZC_SHIFT      1                               /**< Shift value for FPUEH_FPDZC */
+#define _FPUEH_IEN_FPDZC_MASK       0x2UL                           /**< Bit mask for FPUEH_FPDZC */
+#define _FPUEH_IEN_FPDZC_DEFAULT    0x00000000UL                    /**< Mode DEFAULT for FPUEH_IEN */
+#define FPUEH_IEN_FPDZC_DEFAULT     (_FPUEH_IEN_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IEN */
+#define FPUEH_IEN_FPUFC             (0x1UL << 2)                    /**< FPUFC Interrupt Enable */
+#define _FPUEH_IEN_FPUFC_SHIFT      2                               /**< Shift value for FPUEH_FPUFC */
+#define _FPUEH_IEN_FPUFC_MASK       0x4UL                           /**< Bit mask for FPUEH_FPUFC */
+#define _FPUEH_IEN_FPUFC_DEFAULT    0x00000000UL                    /**< Mode DEFAULT for FPUEH_IEN */
+#define FPUEH_IEN_FPUFC_DEFAULT     (_FPUEH_IEN_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IEN */
+#define FPUEH_IEN_FPOFC             (0x1UL << 3)                    /**< FPOFC Interrupt Enable */
+#define _FPUEH_IEN_FPOFC_SHIFT      3                               /**< Shift value for FPUEH_FPOFC */
+#define _FPUEH_IEN_FPOFC_MASK       0x8UL                           /**< Bit mask for FPUEH_FPOFC */
+#define _FPUEH_IEN_FPOFC_DEFAULT    0x00000000UL                    /**< Mode DEFAULT for FPUEH_IEN */
+#define FPUEH_IEN_FPOFC_DEFAULT     (_FPUEH_IEN_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IEN */
+#define FPUEH_IEN_FPIDC             (0x1UL << 4)                    /**< FPIDC Interrupt Enable */
+#define _FPUEH_IEN_FPIDC_SHIFT      4                               /**< Shift value for FPUEH_FPIDC */
+#define _FPUEH_IEN_FPIDC_MASK       0x10UL                          /**< Bit mask for FPUEH_FPIDC */
+#define _FPUEH_IEN_FPIDC_DEFAULT    0x00000000UL                    /**< Mode DEFAULT for FPUEH_IEN */
+#define FPUEH_IEN_FPIDC_DEFAULT     (_FPUEH_IEN_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IEN */
+#define FPUEH_IEN_FPIXC             (0x1UL << 5)                    /**< FPIXC Interrupt Enable */
+#define _FPUEH_IEN_FPIXC_SHIFT      5                               /**< Shift value for FPUEH_FPIXC */
+#define _FPUEH_IEN_FPIXC_MASK       0x20UL                          /**< Bit mask for FPUEH_FPIXC */
+#define _FPUEH_IEN_FPIXC_DEFAULT    0x00000000UL                    /**< Mode DEFAULT for FPUEH_IEN */
+#define FPUEH_IEN_FPIXC_DEFAULT     (_FPUEH_IEN_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IEN */
+
+/** @} */
+/** @} End of group EFM32GG12B_FPUEH */
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+

cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b_gpcrc.h

@@ -0,0 +1,201 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32GG12B_GPCRC register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFM32GG12B_GPCRC GPCRC
+ * @{
+ * @brief EFM32GG12B_GPCRC Register Declaration
+ ******************************************************************************/
+/** GPCRC Register Declaration */
+typedef struct {
+  __IOM uint32_t CTRL;           /**< Control Register  */
+  __IOM uint32_t CMD;            /**< Command Register  */
+  __IOM uint32_t INIT;           /**< CRC Init Value  */
+  __IOM uint32_t POLY;           /**< CRC Polynomial Value  */
+  __IOM uint32_t INPUTDATA;      /**< Input 32-bit Data Register  */
+  __IOM uint32_t INPUTDATAHWORD; /**< Input 16-bit Data Register  */
+  __IOM uint32_t INPUTDATABYTE;  /**< Input 8-bit Data Register  */
+  __IM uint32_t  DATA;           /**< CRC Data Register  */
+  __IM uint32_t  DATAREV;        /**< CRC Data Reverse Register  */
+  __IM uint32_t  DATABYTEREV;    /**< CRC Data Byte Reverse Register  */
+} GPCRC_TypeDef;                 /** @} */
+
+/***************************************************************************//**
+ * @addtogroup EFM32GG12B_GPCRC
+ * @{
+ * @defgroup EFM32GG12B_GPCRC_BitFields  GPCRC Bit Fields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for GPCRC CTRL */
+#define _GPCRC_CTRL_RESETVALUE                          0x00000000UL                             /**< Default value for GPCRC_CTRL */
+#define _GPCRC_CTRL_MASK                                0x00002711UL                             /**< Mask for GPCRC_CTRL */
+#define GPCRC_CTRL_EN                                   (0x1UL << 0)                             /**< CRC Functionality Enable */
+#define _GPCRC_CTRL_EN_SHIFT                            0                                        /**< Shift value for GPCRC_EN */
+#define _GPCRC_CTRL_EN_MASK                             0x1UL                                    /**< Bit mask for GPCRC_EN */
+#define _GPCRC_CTRL_EN_DEFAULT                          0x00000000UL                             /**< Mode DEFAULT for GPCRC_CTRL */
+#define _GPCRC_CTRL_EN_DISABLE                          0x00000000UL                             /**< Mode DISABLE for GPCRC_CTRL */
+#define _GPCRC_CTRL_EN_ENABLE                           0x00000001UL                             /**< Mode ENABLE for GPCRC_CTRL */
+#define GPCRC_CTRL_EN_DEFAULT                           (_GPCRC_CTRL_EN_DEFAULT << 0)            /**< Shifted mode DEFAULT for GPCRC_CTRL */
+#define GPCRC_CTRL_EN_DISABLE                           (_GPCRC_CTRL_EN_DISABLE << 0)            /**< Shifted mode DISABLE for GPCRC_CTRL */
+#define GPCRC_CTRL_EN_ENABLE                            (_GPCRC_CTRL_EN_ENABLE << 0)             /**< Shifted mode ENABLE for GPCRC_CTRL */
+#define GPCRC_CTRL_POLYSEL                              (0x1UL << 4)                             /**< Polynomial Select */
+#define _GPCRC_CTRL_POLYSEL_SHIFT                       4                                        /**< Shift value for GPCRC_POLYSEL */
+#define _GPCRC_CTRL_POLYSEL_MASK                        0x10UL                                   /**< Bit mask for GPCRC_POLYSEL */
+#define _GPCRC_CTRL_POLYSEL_DEFAULT                     0x00000000UL                             /**< Mode DEFAULT for GPCRC_CTRL */
+#define _GPCRC_CTRL_POLYSEL_CRC32                       0x00000000UL                             /**< Mode CRC32 for GPCRC_CTRL */
+#define _GPCRC_CTRL_POLYSEL_16                          0x00000001UL                             /**< Mode 16 for GPCRC_CTRL */
+#define GPCRC_CTRL_POLYSEL_DEFAULT                      (_GPCRC_CTRL_POLYSEL_DEFAULT << 4)       /**< Shifted mode DEFAULT for GPCRC_CTRL */
+#define GPCRC_CTRL_POLYSEL_CRC32                        (_GPCRC_CTRL_POLYSEL_CRC32 << 4)         /**< Shifted mode CRC32 for GPCRC_CTRL */
+#define GPCRC_CTRL_POLYSEL_16                           (_GPCRC_CTRL_POLYSEL_16 << 4)            /**< Shifted mode 16 for GPCRC_CTRL */
+#define GPCRC_CTRL_BYTEMODE                             (0x1UL << 8)                             /**< Byte Mode Enable */
+#define _GPCRC_CTRL_BYTEMODE_SHIFT                      8                                        /**< Shift value for GPCRC_BYTEMODE */
+#define _GPCRC_CTRL_BYTEMODE_MASK                       0x100UL                                  /**< Bit mask for GPCRC_BYTEMODE */
+#define _GPCRC_CTRL_BYTEMODE_DEFAULT                    0x00000000UL                             /**< Mode DEFAULT for GPCRC_CTRL */
+#define GPCRC_CTRL_BYTEMODE_DEFAULT                     (_GPCRC_CTRL_BYTEMODE_DEFAULT << 8)      /**< Shifted mode DEFAULT for GPCRC_CTRL */
+#define GPCRC_CTRL_BITREVERSE                           (0x1UL << 9)                             /**< Byte-level Bit Reverse Enable */
+#define _GPCRC_CTRL_BITREVERSE_SHIFT                    9                                        /**< Shift value for GPCRC_BITREVERSE */
+#define _GPCRC_CTRL_BITREVERSE_MASK                     0x200UL                                  /**< Bit mask for GPCRC_BITREVERSE */
+#define _GPCRC_CTRL_BITREVERSE_DEFAULT                  0x00000000UL                             /**< Mode DEFAULT for GPCRC_CTRL */
+#define _GPCRC_CTRL_BITREVERSE_NORMAL                   0x00000000UL                             /**< Mode NORMAL for GPCRC_CTRL */
+#define _GPCRC_CTRL_BITREVERSE_REVERSED                 0x00000001UL                             /**< Mode REVERSED for GPCRC_CTRL */
+#define GPCRC_CTRL_BITREVERSE_DEFAULT                   (_GPCRC_CTRL_BITREVERSE_DEFAULT << 9)    /**< Shifted mode DEFAULT for GPCRC_CTRL */
+#define GPCRC_CTRL_BITREVERSE_NORMAL                    (_GPCRC_CTRL_BITREVERSE_NORMAL << 9)     /**< Shifted mode NORMAL for GPCRC_CTRL */
+#define GPCRC_CTRL_BITREVERSE_REVERSED                  (_GPCRC_CTRL_BITREVERSE_REVERSED << 9)   /**< Shifted mode REVERSED for GPCRC_CTRL */
+#define GPCRC_CTRL_BYTEREVERSE                          (0x1UL << 10)                            /**< Byte Reverse Mode */
+#define _GPCRC_CTRL_BYTEREVERSE_SHIFT                   10                                       /**< Shift value for GPCRC_BYTEREVERSE */
+#define _GPCRC_CTRL_BYTEREVERSE_MASK                    0x400UL                                  /**< Bit mask for GPCRC_BYTEREVERSE */
+#define _GPCRC_CTRL_BYTEREVERSE_DEFAULT                 0x00000000UL                             /**< Mode DEFAULT for GPCRC_CTRL */
+#define _GPCRC_CTRL_BYTEREVERSE_NORMAL                  0x00000000UL                             /**< Mode NORMAL for GPCRC_CTRL */
+#define _GPCRC_CTRL_BYTEREVERSE_REVERSED                0x00000001UL                             /**< Mode REVERSED for GPCRC_CTRL */
+#define GPCRC_CTRL_BYTEREVERSE_DEFAULT                  (_GPCRC_CTRL_BYTEREVERSE_DEFAULT << 10)  /**< Shifted mode DEFAULT for GPCRC_CTRL */
+#define GPCRC_CTRL_BYTEREVERSE_NORMAL                   (_GPCRC_CTRL_BYTEREVERSE_NORMAL << 10)   /**< Shifted mode NORMAL for GPCRC_CTRL */
+#define GPCRC_CTRL_BYTEREVERSE_REVERSED                 (_GPCRC_CTRL_BYTEREVERSE_REVERSED << 10) /**< Shifted mode REVERSED for GPCRC_CTRL */
+#define GPCRC_CTRL_AUTOINIT                             (0x1UL << 13)                            /**< Auto Init Enable */
+#define _GPCRC_CTRL_AUTOINIT_SHIFT                      13                                       /**< Shift value for GPCRC_AUTOINIT */
+#define _GPCRC_CTRL_AUTOINIT_MASK                       0x2000UL                                 /**< Bit mask for GPCRC_AUTOINIT */
+#define _GPCRC_CTRL_AUTOINIT_DEFAULT                    0x00000000UL                             /**< Mode DEFAULT for GPCRC_CTRL */
+#define GPCRC_CTRL_AUTOINIT_DEFAULT                     (_GPCRC_CTRL_AUTOINIT_DEFAULT << 13)     /**< Shifted mode DEFAULT for GPCRC_CTRL */
+
+/* Bit fields for GPCRC CMD */
+#define _GPCRC_CMD_RESETVALUE                           0x00000000UL                   /**< Default value for GPCRC_CMD */
+#define _GPCRC_CMD_MASK                                 0x00000001UL                   /**< Mask for GPCRC_CMD */
+#define GPCRC_CMD_INIT                                  (0x1UL << 0)                   /**< Initialization Enable */
+#define _GPCRC_CMD_INIT_SHIFT                           0                              /**< Shift value for GPCRC_INIT */
+#define _GPCRC_CMD_INIT_MASK                            0x1UL                          /**< Bit mask for GPCRC_INIT */
+#define _GPCRC_CMD_INIT_DEFAULT                         0x00000000UL                   /**< Mode DEFAULT for GPCRC_CMD */
+#define GPCRC_CMD_INIT_DEFAULT                          (_GPCRC_CMD_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_CMD */
+
+/* Bit fields for GPCRC INIT */
+#define _GPCRC_INIT_RESETVALUE                          0x00000000UL                    /**< Default value for GPCRC_INIT */
+#define _GPCRC_INIT_MASK                                0xFFFFFFFFUL                    /**< Mask for GPCRC_INIT */
+#define _GPCRC_INIT_INIT_SHIFT                          0                               /**< Shift value for GPCRC_INIT */
+#define _GPCRC_INIT_INIT_MASK                           0xFFFFFFFFUL                    /**< Bit mask for GPCRC_INIT */
+#define _GPCRC_INIT_INIT_DEFAULT                        0x00000000UL                    /**< Mode DEFAULT for GPCRC_INIT */
+#define GPCRC_INIT_INIT_DEFAULT                         (_GPCRC_INIT_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INIT */
+
+/* Bit fields for GPCRC POLY */
+#define _GPCRC_POLY_RESETVALUE                          0x00000000UL                    /**< Default value for GPCRC_POLY */
+#define _GPCRC_POLY_MASK                                0x0000FFFFUL                    /**< Mask for GPCRC_POLY */
+#define _GPCRC_POLY_POLY_SHIFT                          0                               /**< Shift value for GPCRC_POLY */
+#define _GPCRC_POLY_POLY_MASK                           0xFFFFUL                        /**< Bit mask for GPCRC_POLY */
+#define _GPCRC_POLY_POLY_DEFAULT                        0x00000000UL                    /**< Mode DEFAULT for GPCRC_POLY */
+#define GPCRC_POLY_POLY_DEFAULT                         (_GPCRC_POLY_POLY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_POLY */
+
+/* Bit fields for GPCRC INPUTDATA */
+#define _GPCRC_INPUTDATA_RESETVALUE                     0x00000000UL                              /**< Default value for GPCRC_INPUTDATA */
+#define _GPCRC_INPUTDATA_MASK                           0xFFFFFFFFUL                              /**< Mask for GPCRC_INPUTDATA */
+#define _GPCRC_INPUTDATA_INPUTDATA_SHIFT                0                                         /**< Shift value for GPCRC_INPUTDATA */
+#define _GPCRC_INPUTDATA_INPUTDATA_MASK                 0xFFFFFFFFUL                              /**< Bit mask for GPCRC_INPUTDATA */
+#define _GPCRC_INPUTDATA_INPUTDATA_DEFAULT              0x00000000UL                              /**< Mode DEFAULT for GPCRC_INPUTDATA */
+#define GPCRC_INPUTDATA_INPUTDATA_DEFAULT               (_GPCRC_INPUTDATA_INPUTDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATA */
+
+/* Bit fields for GPCRC INPUTDATAHWORD */
+#define _GPCRC_INPUTDATAHWORD_RESETVALUE                0x00000000UL                                        /**< Default value for GPCRC_INPUTDATAHWORD */
+#define _GPCRC_INPUTDATAHWORD_MASK                      0x0000FFFFUL                                        /**< Mask for GPCRC_INPUTDATAHWORD */
+#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_SHIFT      0                                                   /**< Shift value for GPCRC_INPUTDATAHWORD */
+#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_MASK       0xFFFFUL                                            /**< Bit mask for GPCRC_INPUTDATAHWORD */
+#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT    0x00000000UL                                        /**< Mode DEFAULT for GPCRC_INPUTDATAHWORD */
+#define GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT     (_GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATAHWORD */
+
+/* Bit fields for GPCRC INPUTDATABYTE */
+#define _GPCRC_INPUTDATABYTE_RESETVALUE                 0x00000000UL                                      /**< Default value for GPCRC_INPUTDATABYTE */
+#define _GPCRC_INPUTDATABYTE_MASK                       0x000000FFUL                                      /**< Mask for GPCRC_INPUTDATABYTE */
+#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_SHIFT        0                                                 /**< Shift value for GPCRC_INPUTDATABYTE */
+#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_MASK         0xFFUL                                            /**< Bit mask for GPCRC_INPUTDATABYTE */
+#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT      0x00000000UL                                      /**< Mode DEFAULT for GPCRC_INPUTDATABYTE */
+#define GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT       (_GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATABYTE */
+
+/* Bit fields for GPCRC DATA */
+#define _GPCRC_DATA_RESETVALUE                          0x00000000UL                    /**< Default value for GPCRC_DATA */
+#define _GPCRC_DATA_MASK                                0xFFFFFFFFUL                    /**< Mask for GPCRC_DATA */
+#define _GPCRC_DATA_DATA_SHIFT                          0                               /**< Shift value for GPCRC_DATA */
+#define _GPCRC_DATA_DATA_MASK                           0xFFFFFFFFUL                    /**< Bit mask for GPCRC_DATA */
+#define _GPCRC_DATA_DATA_DEFAULT                        0x00000000UL                    /**< Mode DEFAULT for GPCRC_DATA */
+#define GPCRC_DATA_DATA_DEFAULT                         (_GPCRC_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATA */
+
+/* Bit fields for GPCRC DATAREV */
+#define _GPCRC_DATAREV_RESETVALUE                       0x00000000UL                          /**< Default value for GPCRC_DATAREV */
+#define _GPCRC_DATAREV_MASK                             0xFFFFFFFFUL                          /**< Mask for GPCRC_DATAREV */
+#define _GPCRC_DATAREV_DATAREV_SHIFT                    0                                     /**< Shift value for GPCRC_DATAREV */
+#define _GPCRC_DATAREV_DATAREV_MASK                     0xFFFFFFFFUL                          /**< Bit mask for GPCRC_DATAREV */
+#define _GPCRC_DATAREV_DATAREV_DEFAULT                  0x00000000UL                          /**< Mode DEFAULT for GPCRC_DATAREV */
+#define GPCRC_DATAREV_DATAREV_DEFAULT                   (_GPCRC_DATAREV_DATAREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATAREV */
+
+/* Bit fields for GPCRC DATABYTEREV */
+#define _GPCRC_DATABYTEREV_RESETVALUE                   0x00000000UL                                  /**< Default value for GPCRC_DATABYTEREV */
+#define _GPCRC_DATABYTEREV_MASK                         0xFFFFFFFFUL                                  /**< Mask for GPCRC_DATABYTEREV */
+#define _GPCRC_DATABYTEREV_DATABYTEREV_SHIFT            0                                             /**< Shift value for GPCRC_DATABYTEREV */
+#define _GPCRC_DATABYTEREV_DATABYTEREV_MASK             0xFFFFFFFFUL                                  /**< Bit mask for GPCRC_DATABYTEREV */
+#define _GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT          0x00000000UL                                  /**< Mode DEFAULT for GPCRC_DATABYTEREV */
+#define GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT           (_GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATABYTEREV */
+
+/** @} */
+/** @} End of group EFM32GG12B_GPCRC */
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+

cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b_gpio_p.h

@@ -0,0 +1,68 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32GG12B_GPIO_P register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @brief GPIO_P GPIO P Register
+ * @ingroup EFM32GG12B_GPIO
+ ******************************************************************************/
+typedef struct {
+  __IOM uint32_t CTRL;          /**< Port Control Register  */
+  __IOM uint32_t MODEL;         /**< Port Pin Mode Low Register  */
+  __IOM uint32_t MODEH;         /**< Port Pin Mode High Register  */
+  __IOM uint32_t DOUT;          /**< Port Data Out Register  */
+  uint32_t       RESERVED0[2U]; /**< Reserved for future use **/
+  __IOM uint32_t DOUTTGL;       /**< Port Data Out Toggle Register  */
+  __IM uint32_t  DIN;           /**< Port Data in Register  */
+  __IOM uint32_t PINLOCKN;      /**< Port Unlocked Pins Register  */
+  uint32_t       RESERVED1[1U]; /**< Reserved for future use **/
+  __IOM uint32_t OVTDIS;        /**< Over Voltage Disable for All Modes  */
+  uint32_t       RESERVED2[1U]; /**< Reserved future */
+} GPIO_P_TypeDef;
+
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+

cpu/efm32/families/efm32gg12b/include/vendor/efm32gg12b_i2c.h

@@ -0,0 +1,841 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFM32GG12B_I2C register and bit field definitions
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software
+ *    in a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(__ICCARM__)
+#pragma system_include       /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header  /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFM32GG12B_I2C I2C
+ * @{
+ * @brief EFM32GG12B_I2C Register Declaration
+ ******************************************************************************/
+/** I2C Register Declaration */
+typedef struct {
+  __IOM uint32_t CTRL;      /**< Control Register  */
+  __IOM uint32_t CMD;       /**< Command Register  */
+  __IM uint32_t  STATE;     /**< State Register  */
+  __IM uint32_t  STATUS;    /**< Status Register  */
+  __IOM uint32_t CLKDIV;    /**< Clock Division Register  */
+  __IOM uint32_t SADDR;     /**< Slave Address Register  */
+  __IOM uint32_t SADDRMASK; /**< Slave Address Mask Register  */
+  __IM uint32_t  RXDATA;    /**< Receive Buffer Data Register  */
+  __IM uint32_t  RXDOUBLE;  /**< Receive Buffer Double Data Register  */
+  __IM uint32_t  RXDATAP;   /**< Receive Buffer Data Peek Register  */
+  __IM uint32_t  RXDOUBLEP; /**< Receive Buffer Double Data Peek Register  */
+  __IOM uint32_t TXDATA;    /**< Transmit Buffer Data Register  */
+  __IOM uint32_t TXDOUBLE;  /**< Transmit Buffer Double Data Register  */
+  __IM uint32_t  IF;        /**< Interrupt Flag Register  */
+  __IOM uint32_t IFS;       /**< Interrupt Flag Set Register  */
+  __IOM uint32_t IFC;       /**< Interrupt Flag Clear Register  */
+  __IOM uint32_t IEN;       /**< Interrupt Enable Register  */
+  __IOM uint32_t ROUTEPEN;  /**< I/O Routing Pin Enable Register  */
+  __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register  */
+} I2C_TypeDef;              /** @} */
+
+/***************************************************************************//**
+ * @addtogroup EFM32GG12B_I2C
+ * @{
+ * @defgroup EFM32GG12B_I2C_BitFields  I2C Bit Fields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for I2C CTRL */
+#define _I2C_CTRL_RESETVALUE               0x00000000UL                     /**< Default value for I2C_CTRL */
+#define _I2C_CTRL_MASK                     0x0007B3FFUL                     /**< Mask for I2C_CTRL */
+#define I2C_CTRL_EN                        (0x1UL << 0)                     /**< I2C Enable */
+#define _I2C_CTRL_EN_SHIFT                 0                                /**< Shift value for I2C_EN */
+#define _I2C_CTRL_EN_MASK                  0x1UL                            /**< Bit mask for I2C_EN */
+#define _I2C_CTRL_EN_DEFAULT               0x00000000UL                     /**< Mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_EN_DEFAULT                (_I2C_CTRL_EN_DEFAULT << 0)      /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_SLAVE                     (0x1UL << 1)                     /**< Addressable as Slave */
+#define _I2C_CTRL_SLAVE_SHIFT              1                                /**< Shift value for I2C_SLAVE */
+#define _I2C_CTRL_SLAVE_MASK               0x2UL                            /**< Bit mask for I2C_SLAVE */
+#define _I2C_CTRL_SLAVE_DEFAULT            0x00000000UL                     /**< Mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_SLAVE_DEFAULT             (_I2C_CTRL_SLAVE_DEFAULT << 1)   /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_AUTOACK                   (0x1UL << 2)                     /**< Automatic Acknowledge */
+#define _I2C_CTRL_AUTOACK_SHIFT            2                                /**< Shift value for I2C_AUTOACK */
+#define _I2C_CTRL_AUTOACK_MASK             0x4UL                            /**< Bit mask for I2C_AUTOACK */
+#define _I2C_CTRL_AUTOACK_DEFAULT          0x00000000UL                     /**< Mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_AUTOACK_DEFAULT           (_I2C_CTRL_AUTOACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_AUTOSE                    (0x1UL << 3)                     /**< Automatic STOP When Empty */
+#define _I2C_CTRL_AUTOSE_SHIFT             3                                /**< Shift value for I2C_AUTOSE */
+#define _I2C_CTRL_AUTOSE_MASK              0x8UL                            /**< Bit mask for I2C_AUTOSE */
+#define _I2C_CTRL_AUTOSE_DEFAULT           0x00000000UL                     /**< Mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_AUTOSE_DEFAULT            (_I2C_CTRL_AUTOSE_DEFAULT << 3)  /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_AUTOSN                    (0x1UL << 4)                     /**< Automatic STOP on NACK */
+#define _I2C_CTRL_AUTOSN_SHIFT             4                                /**< Shift value for I2C_AUTOSN */
+#define _I2C_CTRL_AUTOSN_MASK              0x10UL                           /**< Bit mask for I2C_AUTOSN */
+#define _I2C_CTRL_AUTOSN_DEFAULT           0x00000000UL                     /**< Mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_AUTOSN_DEFAULT            (_I2C_CTRL_AUTOSN_DEFAULT << 4)  /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_ARBDIS                    (0x1UL << 5)                     /**< Arbitration Disable */
+#define _I2C_CTRL_ARBDIS_SHIFT             5                                /**< Shift value for I2C_ARBDIS */
+#define _I2C_CTRL_ARBDIS_MASK              0x20UL                           /**< Bit mask for I2C_ARBDIS */
+#define _I2C_CTRL_ARBDIS_DEFAULT           0x00000000UL                     /**< Mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_ARBDIS_DEFAULT            (_I2C_CTRL_ARBDIS_DEFAULT << 5)  /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_GCAMEN                    (0x1UL << 6)                     /**< General Call Address Match Enable */
+#define _I2C_CTRL_GCAMEN_SHIFT             6                                /**< Shift value for I2C_GCAMEN */
+#define _I2C_CTRL_GCAMEN_MASK              0x40UL                           /**< Bit mask for I2C_GCAMEN */
+#define _I2C_CTRL_GCAMEN_DEFAULT           0x00000000UL                     /**< Mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_GCAMEN_DEFAULT            (_I2C_CTRL_GCAMEN_DEFAULT << 6)  /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_TXBIL                     (0x1UL << 7)                     /**< TX Buffer Interrupt Level */
+#define _I2C_CTRL_TXBIL_SHIFT              7                                /**< Shift value for I2C_TXBIL */
+#define _I2C_CTRL_TXBIL_MASK               0x80UL                           /**< Bit mask for I2C_TXBIL */
+#define _I2C_CTRL_TXBIL_DEFAULT            0x00000000UL                     /**< Mode DEFAULT for I2C_CTRL */
+#define _I2C_CTRL_TXBIL_EMPTY              0x00000000UL                     /**< Mode EMPTY for I2C_CTRL */
+#define _I2C_CTRL_TXBIL_HALFFULL           0x00000001UL                     /**< Mode HALFFULL for I2C_CTRL */
+#define I2C_CTRL_TXBIL_DEFAULT             (_I2C_CTRL_TXBIL_DEFAULT << 7)   /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_TXBIL_EMPTY               (_I2C_CTRL_TXBIL_EMPTY << 7)     /**< Shifted mode EMPTY for I2C_CTRL */
+#define I2C_CTRL_TXBIL_HALFFULL            (_I2C_CTRL_TXBIL_HALFFULL << 7)  /**< Shifted mode HALFFULL for I2C_CTRL */
+#define _I2C_CTRL_CLHR_SHIFT               8                                /**< Shift value for I2C_CLHR */
+#define _I2C_CTRL_CLHR_MASK                0x300UL                          /**< Bit mask for I2C_CLHR */
+#define _I2C_CTRL_CLHR_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_CTRL */
+#define _I2C_CTRL_CLHR_STANDARD            0x00000000UL                     /**< Mode STANDARD for I2C_CTRL */
+#define _I2C_CTRL_CLHR_ASYMMETRIC          0x00000001UL                     /**< Mode ASYMMETRIC for I2C_CTRL */
+#define _I2C_CTRL_CLHR_FAST                0x00000002UL                     /**< Mode FAST for I2C_CTRL */
+#define I2C_CTRL_CLHR_DEFAULT              (_I2C_CTRL_CLHR_DEFAULT << 8)    /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_CLHR_STANDARD             (_I2C_CTRL_CLHR_STANDARD << 8)   /**< Shifted mode STANDARD for I2C_CTRL */
+#define I2C_CTRL_CLHR_ASYMMETRIC           (_I2C_CTRL_CLHR_ASYMMETRIC << 8) /**< Shifted mode ASYMMETRIC for I2C_CTRL */
+#define I2C_CTRL_CLHR_FAST                 (_I2C_CTRL_CLHR_FAST << 8)       /**< Shifted mode FAST for I2C_CTRL */
+#define _I2C_CTRL_BITO_SHIFT               12                               /**< Shift value for I2C_BITO */
+#define _I2C_CTRL_BITO_MASK                0x3000UL                         /**< Bit mask for I2C_BITO */
+#define _I2C_CTRL_BITO_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_CTRL */
+#define _I2C_CTRL_BITO_OFF                 0x00000000UL                     /**< Mode OFF for I2C_CTRL */
+#define _I2C_CTRL_BITO_40PCC               0x00000001UL                     /**< Mode 40PCC for I2C_CTRL */
+#define _I2C_CTRL_BITO_80PCC               0x00000002UL                     /**< Mode 80PCC for I2C_CTRL */
+#define _I2C_CTRL_BITO_160PCC              0x00000003UL                     /**< Mode 160PCC for I2C_CTRL */
+#define I2C_CTRL_BITO_DEFAULT              (_I2C_CTRL_BITO_DEFAULT << 12)   /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_BITO_OFF                  (_I2C_CTRL_BITO_OFF << 12)       /**< Shifted mode OFF for I2C_CTRL */
+#define I2C_CTRL_BITO_40PCC                (_I2C_CTRL_BITO_40PCC << 12)     /**< Shifted mode 40PCC for I2C_CTRL */
+#define I2C_CTRL_BITO_80PCC                (_I2C_CTRL_BITO_80PCC << 12)     /**< Shifted mode 80PCC for I2C_CTRL */
+#define I2C_CTRL_BITO_160PCC               (_I2C_CTRL_BITO_160PCC << 12)    /**< Shifted mode 160PCC for I2C_CTRL */
+#define I2C_CTRL_GIBITO                    (0x1UL << 15)                    /**< Go Idle on Bus Idle Timeout */
+#define _I2C_CTRL_GIBITO_SHIFT             15                               /**< Shift value for I2C_GIBITO */
+#define _I2C_CTRL_GIBITO_MASK              0x8000UL                         /**< Bit mask for I2C_GIBITO */
+#define _I2C_CTRL_GIBITO_DEFAULT           0x00000000UL                     /**< Mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_GIBITO_DEFAULT            (_I2C_CTRL_GIBITO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_CTRL */
+#define _I2C_CTRL_CLTO_SHIFT               16                               /**< Shift value for I2C_CLTO */
+#define _I2C_CTRL_CLTO_MASK                0x70000UL                        /**< Bit mask for I2C_CLTO */
+#define _I2C_CTRL_CLTO_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_CTRL */
+#define _I2C_CTRL_CLTO_OFF                 0x00000000UL                     /**< Mode OFF for I2C_CTRL */
+#define _I2C_CTRL_CLTO_40PCC               0x00000001UL                     /**< Mode 40PCC for I2C_CTRL */
+#define _I2C_CTRL_CLTO_80PCC               0x00000002UL                     /**< Mode 80PCC for I2C_CTRL */
+#define _I2C_CTRL_CLTO_160PCC              0x00000003UL                     /**< Mode 160PCC for I2C_CTRL */
+#define _I2C_CTRL_CLTO_320PCC              0x00000004UL                     /**< Mode 320PCC for I2C_CTRL */
+#define _I2C_CTRL_CLTO_1024PCC             0x00000005UL                     /**< Mode 1024PCC for I2C_CTRL */
+#define I2C_CTRL_CLTO_DEFAULT              (_I2C_CTRL_CLTO_DEFAULT << 16)   /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_CLTO_OFF                  (_I2C_CTRL_CLTO_OFF << 16)       /**< Shifted mode OFF for I2C_CTRL */
+#define I2C_CTRL_CLTO_40PCC                (_I2C_CTRL_CLTO_40PCC << 16)     /**< Shifted mode 40PCC for I2C_CTRL */
+#define I2C_CTRL_CLTO_80PCC                (_I2C_CTRL_CLTO_80PCC << 16)     /**< Shifted mode 80PCC for I2C_CTRL */
+#define I2C_CTRL_CLTO_160PCC               (_I2C_CTRL_CLTO_160PCC << 16)    /**< Shifted mode 160PCC for I2C_CTRL */
+#define I2C_CTRL_CLTO_320PCC               (_I2C_CTRL_CLTO_320PCC << 16)    /**< Shifted mode 320PCC for I2C_CTRL */
+#define I2C_CTRL_CLTO_1024PCC              (_I2C_CTRL_CLTO_1024PCC << 16)   /**< Shifted mode 1024PCC for I2C_CTRL */
+
+/* Bit fields for I2C CMD */
+#define _I2C_CMD_RESETVALUE                0x00000000UL                    /**< Default value for I2C_CMD */
+#define _I2C_CMD_MASK                      0x000000FFUL                    /**< Mask for I2C_CMD */
+#define I2C_CMD_START                      (0x1UL << 0)                    /**< Send Start Condition */
+#define _I2C_CMD_START_SHIFT               0                               /**< Shift value for I2C_START */
+#define _I2C_CMD_START_MASK                0x1UL                           /**< Bit mask for I2C_START */
+#define _I2C_CMD_START_DEFAULT             0x00000000UL                    /**< Mode DEFAULT for I2C_CMD */
+#define I2C_CMD_START_DEFAULT              (_I2C_CMD_START_DEFAULT << 0)   /**< Shifted mode DEFAULT for I2C_CMD */
+#define I2C_CMD_STOP                       (0x1UL << 1)                    /**< Send Stop Condition */
+#define _I2C_CMD_STOP_SHIFT                1                               /**< Shift value for I2C_STOP */
+#define _I2C_CMD_STOP_MASK                 0x2UL                           /**< Bit mask for I2C_STOP */
+#define _I2C_CMD_STOP_DEFAULT              0x00000000UL                    /**< Mode DEFAULT for I2C_CMD */
+#define I2C_CMD_STOP_DEFAULT               (_I2C_CMD_STOP_DEFAULT << 1)    /**< Shifted mode DEFAULT for I2C_CMD */
+#define I2C_CMD_ACK                        (0x1UL << 2)                    /**< Send ACK */
+#define _I2C_CMD_ACK_SHIFT                 2                               /**< Shift value for I2C_ACK */
+#define _I2C_CMD_ACK_MASK                  0x4UL                           /**< Bit mask for I2C_ACK */
+#define _I2C_CMD_ACK_DEFAULT               0x00000000UL                    /**< Mode DEFAULT for I2C_CMD */
+#define I2C_CMD_ACK_DEFAULT                (_I2C_CMD_ACK_DEFAULT << 2)     /**< Shifted mode DEFAULT for I2C_CMD */
+#define I2C_CMD_NACK                       (0x1UL << 3)                    /**< Send NACK */
+#define _I2C_CMD_NACK_SHIFT                3                               /**< Shift value for I2C_NACK */
+#define _I2C_CMD_NACK_MASK                 0x8UL                           /**< Bit mask for I2C_NACK */
+#define _I2C_CMD_NACK_DEFAULT              0x00000000UL                    /**< Mode DEFAULT for I2C_CMD */
+#define I2C_CMD_NACK_DEFAULT               (_I2C_CMD_NACK_DEFAULT << 3)    /**< Shifted mode DEFAULT for I2C_CMD */
+#define I2C_CMD_CONT                       (0x1UL << 4)                    /**< Continue Transmission */
+#define _I2C_CMD_CONT_SHIFT                4                               /**< Shift value for I2C_CONT */
+#define _I2C_CMD_CONT_MASK                 0x10UL                          /**< Bit mask for I2C_CONT */
+#define _I2C_CMD_CONT_DEFAULT              0x00000000UL                    /**< Mode DEFAULT for I2C_CMD */
+#define I2C_CMD_CONT_DEFAULT               (_I2C_CMD_CONT_DEFAULT << 4)    /**< Shifted mode DEFAULT for I2C_CMD */
+#define I2C_CMD_ABORT                      (0x1UL << 5)                    /**< Abort Transmission */
+#define _I2C_CMD_ABORT_SHIFT               5                               /**< Shift value for I2C_ABORT */
+#define _I2C_CMD_ABORT_MASK                0x20UL                          /**< Bit mask for I2C_ABORT */
+#define _I2C_CMD_ABORT_DEFAULT             0x00000000UL                    /**< Mode DEFAULT for I2C_CMD */
+#define I2C_CMD_ABORT_DEFAULT              (_I2C_CMD_ABORT_DEFAULT << 5)   /**< Shifted mode DEFAULT for I2C_CMD */
+#define I2C_CMD_CLEARTX                    (0x1UL << 6)                    /**< Clear TX */
+#define _I2C_CMD_CLEARTX_SHIFT             6                               /**< Shift value for I2C_CLEARTX */
+#define _I2C_CMD_CLEARTX_MASK              0x40UL                          /**< Bit mask for I2C_CLEARTX */
+#define _I2C_CMD_CLEARTX_DEFAULT           0x00000000UL                    /**< Mode DEFAULT for I2C_CMD */
+#define I2C_CMD_CLEARTX_DEFAULT            (_I2C_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CMD */
+#define I2C_CMD_CLEARPC                    (0x1UL << 7)                    /**< Clear Pending Commands */
+#define _I2C_CMD_CLEARPC_SHIFT             7                               /**< Shift value for I2C_CLEARPC */
+#define _I2C_CMD_CLEARPC_MASK              0x80UL                          /**< Bit mask for I2C_CLEARPC */
+#define _I2C_CMD_CLEARPC_DEFAULT           0x00000000UL                    /**< Mode DEFAULT for I2C_CMD */
+#define I2C_CMD_CLEARPC_DEFAULT            (_I2C_CMD_CLEARPC_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CMD */
+
+/* Bit fields for I2C STATE */
+#define _I2C_STATE_RESETVALUE              0x00000001UL                          /**< Default value for I2C_STATE */
+#define _I2C_STATE_MASK                    0x000000FFUL                          /**< Mask for I2C_STATE */
+#define I2C_STATE_BUSY                     (0x1UL << 0)                          /**< Bus Busy */
+#define _I2C_STATE_BUSY_SHIFT              0                                     /**< Shift value for I2C_BUSY */
+#define _I2C_STATE_BUSY_MASK               0x1UL                                 /**< Bit mask for I2C_BUSY */
+#define _I2C_STATE_BUSY_DEFAULT            0x00000001UL                          /**< Mode DEFAULT for I2C_STATE */
+#define I2C_STATE_BUSY_DEFAULT             (_I2C_STATE_BUSY_DEFAULT << 0)        /**< Shifted mode DEFAULT for I2C_STATE */
+#define I2C_STATE_MASTER                   (0x1UL << 1)                          /**< Master */
+#define _I2C_STATE_MASTER_SHIFT            1                                     /**< Shift value for I2C_MASTER */
+#define _I2C_STATE_MASTER_MASK             0x2UL                                 /**< Bit mask for I2C_MASTER */
+#define _I2C_STATE_MASTER_DEFAULT          0x00000000UL                          /**< Mode DEFAULT for I2C_STATE */
+#define I2C_STATE_MASTER_DEFAULT           (_I2C_STATE_MASTER_DEFAULT << 1)      /**< Shifted mode DEFAULT for I2C_STATE */
+#define I2C_STATE_TRANSMITTER              (0x1UL << 2)                          /**< Transmitter */
+#define _I2C_STATE_TRANSMITTER_SHIFT       2                                     /**< Shift value for I2C_TRANSMITTER */
+#define _I2C_STATE_TRANSMITTER_MASK        0x4UL                                 /**< Bit mask for I2C_TRANSMITTER */
+#define _I2C_STATE_TRANSMITTER_DEFAULT     0x00000000UL                          /**< Mode DEFAULT for I2C_STATE */
+#define I2C_STATE_TRANSMITTER_DEFAULT      (_I2C_STATE_TRANSMITTER_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATE */
+#define I2C_STATE_NACKED                   (0x1UL << 3)                          /**< Nack Received */
+#define _I2C_STATE_NACKED_SHIFT            3                                     /**< Shift value for I2C_NACKED */
+#define _I2C_STATE_NACKED_MASK             0x8UL                                 /**< Bit mask for I2C_NACKED */
+#define _I2C_STATE_NACKED_DEFAULT          0x00000000UL                          /**< Mode DEFAULT for I2C_STATE */
+#define I2C_STATE_NACKED_DEFAULT           (_I2C_STATE_NACKED_DEFAULT << 3)      /**< Shifted mode DEFAULT for I2C_STATE */
+#define I2C_STATE_BUSHOLD                  (0x1UL << 4)                          /**< Bus Held */
+#define _I2C_STATE_BUSHOLD_SHIFT           4                                     /**< Shift value for I2C_BUSHOLD */
+#define _I2C_STATE_BUSHOLD_MASK            0x10UL                                /**< Bit mask for I2C_BUSHOLD */
+#define _I2C_STATE_BUSHOLD_DEFAULT         0x00000000UL                          /**< Mode DEFAULT for I2C_STATE */
+#define I2C_STATE_BUSHOLD_DEFAULT          (_I2C_STATE_BUSHOLD_DEFAULT << 4)     /**< Shifted mode DEFAULT for I2C_STATE */
+#define _I2C_STATE_STATE_SHIFT             5                                     /**< Shift value for I2C_STATE */
+#define _I2C_STATE_STATE_MASK              0xE0UL                                /**< Bit mask for I2C_STATE */
+#define _I2C_STATE_STATE_DEFAULT           0x00000000UL                          /**< Mode DEFAULT for I2C_STATE */
+#define _I2C_STATE_STATE_IDLE              0x00000000UL                          /**< Mode IDLE for I2C_STATE */
+#define _I2C_STATE_STATE_WAIT              0x00000001UL                          /**< Mode WAIT for I2C_STATE */
+#define _I2C_STATE_STATE_START             0x00000002UL                          /**< Mode START for I2C_STATE */
+#define _I2C_STATE_STATE_ADDR              0x00000003UL                          /**< Mode ADDR for I2C_STATE */
+#define _I2C_STATE_STATE_ADDRACK           0x00000004UL                          /**< Mode ADDRACK for I2C_STATE */
+#define _I2C_STATE_STATE_DATA              0x00000005UL                          /**< Mode DATA for I2C_STATE */
+#define _I2C_STATE_STATE_DATAACK           0x00000006UL                          /**< Mode DATAACK for I2C_STATE */
+#define I2C_STATE_STATE_DEFAULT            (_I2C_STATE_STATE_DEFAULT << 5)       /**< Shifted mode DEFAULT for I2C_STATE */
+#define I2C_STATE_STATE_IDLE               (_I2C_STATE_STATE_IDLE << 5)          /**< Shifted mode IDLE for I2C_STATE */
+#define I2C_STATE_STATE_WAIT               (_I2C_STATE_STATE_WAIT << 5)          /**< Shifted mode WAIT for I2C_STATE */
+#define I2C_STATE_STATE_START              (_I2C_STATE_STATE_START << 5)         /**< Shifted mode START for I2C_STATE */
+#define I2C_STATE_STATE_ADDR               (_I2C_STATE_STATE_ADDR << 5)          /**< Shifted mode ADDR for I2C_STATE */
+#define I2C_STATE_STATE_ADDRACK            (_I2C_STATE_STATE_ADDRACK << 5)       /**< Shifted mode ADDRACK for I2C_STATE */
+#define I2C_STATE_STATE_DATA               (_I2C_STATE_STATE_DATA << 5)          /**< Shifted mode DATA for I2C_STATE */
+#define I2C_STATE_STATE_DATAACK            (_I2C_STATE_STATE_DATAACK << 5)       /**< Shifted mode DATAACK for I2C_STATE */
+
+/* Bit fields for I2C STATUS */
+#define _I2C_STATUS_RESETVALUE             0x00000080UL                       /**< Default value for I2C_STATUS */
+#define _I2C_STATUS_MASK                   0x000003FFUL                       /**< Mask for I2C_STATUS */
+#define I2C_STATUS_PSTART                  (0x1UL << 0)                       /**< Pending START */
+#define _I2C_STATUS_PSTART_SHIFT           0                                  /**< Shift value for I2C_PSTART */
+#define _I2C_STATUS_PSTART_MASK            0x1UL                              /**< Bit mask for I2C_PSTART */
+#define _I2C_STATUS_PSTART_DEFAULT         0x00000000UL                       /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PSTART_DEFAULT          (_I2C_STATUS_PSTART_DEFAULT << 0)  /**< Shifted mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PSTOP                   (0x1UL << 1)                       /**< Pending STOP */
+#define _I2C_STATUS_PSTOP_SHIFT            1                                  /**< Shift value for I2C_PSTOP */
+#define _I2C_STATUS_PSTOP_MASK             0x2UL                              /**< Bit mask for I2C_PSTOP */
+#define _I2C_STATUS_PSTOP_DEFAULT          0x00000000UL                       /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PSTOP_DEFAULT           (_I2C_STATUS_PSTOP_DEFAULT << 1)   /**< Shifted mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PACK                    (0x1UL << 2)                       /**< Pending ACK */
+#define _I2C_STATUS_PACK_SHIFT             2                                  /**< Shift value for I2C_PACK */
+#define _I2C_STATUS_PACK_MASK              0x4UL                              /**< Bit mask for I2C_PACK */
+#define _I2C_STATUS_PACK_DEFAULT           0x00000000UL                       /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PACK_DEFAULT            (_I2C_STATUS_PACK_DEFAULT << 2)    /**< Shifted mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PNACK                   (0x1UL << 3)                       /**< Pending NACK */
+#define _I2C_STATUS_PNACK_SHIFT            3                                  /**< Shift value for I2C_PNACK */
+#define _I2C_STATUS_PNACK_MASK             0x8UL                              /**< Bit mask for I2C_PNACK */
+#define _I2C_STATUS_PNACK_DEFAULT          0x00000000UL                       /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PNACK_DEFAULT           (_I2C_STATUS_PNACK_DEFAULT << 3)   /**< Shifted mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PCONT                   (0x1UL << 4)                       /**< Pending Continue */
+#define _I2C_STATUS_PCONT_SHIFT            4                                  /**< Shift value for I2C_PCONT */
+#define _I2C_STATUS_PCONT_MASK             0x10UL                             /**< Bit mask for I2C_PCONT */
+#define _I2C_STATUS_PCONT_DEFAULT          0x00000000UL                       /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PCONT_DEFAULT           (_I2C_STATUS_PCONT_DEFAULT << 4)   /**< Shifted mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PABORT                  (0x1UL << 5)                       /**< Pending Abort */
+#define _I2C_STATUS_PABORT_SHIFT           5                                  /**< Shift value for I2C_PABORT */
+#define _I2C_STATUS_PABORT_MASK            0x20UL                             /**< Bit mask for I2C_PABORT */
+#define _I2C_STATUS_PABORT_DEFAULT         0x00000000UL                       /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PABORT_DEFAULT          (_I2C_STATUS_PABORT_DEFAULT << 5)  /**< Shifted mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_TXC                     (0x1UL << 6)                       /**< TX Complete */
+#define _I2C_STATUS_TXC_SHIFT              6                                  /**< Shift value for I2C_TXC */
+#define _I2C_STATUS_TXC_MASK               0x40UL                             /**< Bit mask for I2C_TXC */
+#define _I2C_STATUS_TXC_DEFAULT            0x00000000UL                       /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_TXC_DEFAULT             (_I2C_STATUS_TXC_DEFAULT << 6)     /**< Shifted mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_TXBL                    (0x1UL << 7)                       /**< TX Buffer Level */
+#define _I2C_STATUS_TXBL_SHIFT             7                                  /**< Shift value for I2C_TXBL */
+#define _I2C_STATUS_TXBL_MASK              0x80UL                             /**< Bit mask for I2C_TXBL */
+#define _I2C_STATUS_TXBL_DEFAULT           0x00000001UL                       /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_TXBL_DEFAULT            (_I2C_STATUS_TXBL_DEFAULT << 7)    /**< Shifted mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_RXDATAV                 (0x1UL << 8)                       /**< RX Data Valid */
+#define _I2C_STATUS_RXDATAV_SHIFT          8                                  /**< Shift value for I2C_RXDATAV */
+#define _I2C_STATUS_RXDATAV_MASK           0x100UL                            /**< Bit mask for I2C_RXDATAV */
+#define _I2C_STATUS_RXDATAV_DEFAULT        0x00000000UL                       /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_RXDATAV_DEFAULT         (_I2C_STATUS_RXDATAV_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_RXFULL                  (0x1UL << 9)                       /**< RX FIFO Full */
+#define _I2C_STATUS_RXFULL_SHIFT           9                                  /**< Shift value for I2C_RXFULL */
+#define _I2C_STATUS_RXFULL_MASK            0x200UL                            /**< Bit mask for I2C_RXFULL */
+#define _I2C_STATUS_RXFULL_DEFAULT         0x00000000UL                       /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_RXFULL_DEFAULT          (_I2C_STATUS_RXFULL_DEFAULT << 9)  /**< Shifted mode DEFAULT for I2C_STATUS */
+
+/* Bit fields for I2C CLKDIV */
+#define _I2C_CLKDIV_RESETVALUE             0x00000000UL                   /**< Default value for I2C_CLKDIV */
+#define _I2C_CLKDIV_MASK                   0x000001FFUL                   /**< Mask for I2C_CLKDIV */
+#define _I2C_CLKDIV_DIV_SHIFT              0                              /**< Shift value for I2C_DIV */
+#define _I2C_CLKDIV_DIV_MASK               0x1FFUL                        /**< Bit mask for I2C_DIV */
+#define _I2C_CLKDIV_DIV_DEFAULT            0x00000000UL                   /**< Mode DEFAULT for I2C_CLKDIV */
+#define I2C_CLKDIV_DIV_DEFAULT             (_I2C_CLKDIV_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CLKDIV */
+
+/* Bit fields for I2C SADDR */
+#define _I2C_SADDR_RESETVALUE              0x00000000UL                   /**< Default value for I2C_SADDR */
+#define _I2C_SADDR_MASK                    0x000000FEUL                   /**< Mask for I2C_SADDR */
+#define _I2C_SADDR_ADDR_SHIFT              1                              /**< Shift value for I2C_ADDR */
+#define _I2C_SADDR_ADDR_MASK               0xFEUL                         /**< Bit mask for I2C_ADDR */
+#define _I2C_SADDR_ADDR_DEFAULT            0x00000000UL                   /**< Mode DEFAULT for I2C_SADDR */
+#define I2C_SADDR_ADDR_DEFAULT             (_I2C_SADDR_ADDR_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDR */
+
+/* Bit fields for I2C SADDRMASK */
+#define _I2C_SADDRMASK_RESETVALUE          0x00000000UL                       /**< Default value for I2C_SADDRMASK */
+#define _I2C_SADDRMASK_MASK                0x000000FEUL                       /**< Mask for I2C_SADDRMASK */
+#define _I2C_SADDRMASK_MASK_SHIFT          1                                  /**< Shift value for I2C_MASK */
+#define _I2C_SADDRMASK_MASK_MASK           0xFEUL                             /**< Bit mask for I2C_MASK */
+#define _I2C_SADDRMASK_MASK_DEFAULT        0x00000000UL                       /**< Mode DEFAULT for I2C_SADDRMASK */
+#define I2C_SADDRMASK_MASK_DEFAULT         (_I2C_SADDRMASK_MASK_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDRMASK */
+
+/* Bit fields for I2C RXDATA */
+#define _I2C_RXDATA_RESETVALUE             0x00000000UL                      /**< Default value for I2C_RXDATA */
+#define _I2C_RXDATA_MASK                   0x000000FFUL                      /**< Mask for I2C_RXDATA */
+#define _I2C_RXDATA_RXDATA_SHIFT           0                                 /**< Shift value for I2C_RXDATA */
+#define _I2C_RXDATA_RXDATA_MASK            0xFFUL                            /**< Bit mask for I2C_RXDATA */
+#define _I2C_RXDATA_RXDATA_DEFAULT         0x00000000UL                      /**< Mode DEFAULT for I2C_RXDATA */
+#define I2C_RXDATA_RXDATA_DEFAULT          (_I2C_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATA */
+
+/* Bit fields for I2C RXDOUBLE */
+#define _I2C_RXDOUBLE_RESETVALUE           0x00000000UL                         /**< Default value for I2C_RXDOUBLE */
+#define _I2C_RXDOUBLE_MASK                 0x0000FFFFUL                         /**< Mask for I2C_RXDOUBLE */
+#define _I2C_RXDOUBLE_RXDATA0_SHIFT        0                                    /**< Shift value for I2C_RXDATA0 */
+#define _I2C_RXDOUBLE_RXDATA0_MASK         0xFFUL                               /**< Bit mask for I2C_RXDATA0 */
+#define _I2C_RXDOUBLE_RXDATA0_DEFAULT      0x00000000UL                         /**< Mode DEFAULT for I2C_RXDOUBLE */
+#define I2C_RXDOUBLE_RXDATA0_DEFAULT       (_I2C_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */
+#define _I2C_RXDOUBLE_RXDATA1_SHIFT        8                                    /**< Shift value for I2C_RXDATA1 */
+#define _I2C_RXDOUBLE_RXDATA1_MASK         0xFF00UL                             /**< Bit mask for I2C_RXDATA1 */
+#define _I2C_RXDOUBLE_RXDATA1_DEFAULT      0x00000000UL                         /**< Mode DEFAULT for I2C_RXDOUBLE */
+#define I2C_RXDOUBLE_RXDATA1_DEFAULT       (_I2C_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */
+
+/* Bit fields for I2C RXDATAP */
+#define _I2C_RXDATAP_RESETVALUE            0x00000000UL                        /**< Default value for I2C_RXDATAP */
+#define _I2C_RXDATAP_MASK                  0x000000FFUL                        /**< Mask for I2C_RXDATAP */
+#define _I2C_RXDATAP_RXDATAP_SHIFT         0                                   /**< Shift value for I2C_RXDATAP */
+#define _I2C_RXDATAP_RXDATAP_MASK          0xFFUL                              /**< Bit mask for I2C_RXDATAP */
+#define _I2C_RXDATAP_RXDATAP_DEFAULT       0x00000000UL                        /**< Mode DEFAULT for I2C_RXDATAP */
+#define I2C_RXDATAP_RXDATAP_DEFAULT        (_I2C_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATAP */
+
+/* Bit fields for I2C RXDOUBLEP */
+#define _I2C_RXDOUBLEP_RESETVALUE          0x00000000UL                           /**< Default value for I2C_RXDOUBLEP */
+#define _I2C_RXDOUBLEP_MASK                0x0000FFFFUL                           /**< Mask for I2C_RXDOUBLEP */
+#define _I2C_RXDOUBLEP_RXDATAP0_SHIFT      0                                      /**< Shift value for I2C_RXDATAP0 */
+#define _I2C_RXDOUBLEP_RXDATAP0_MASK       0xFFUL                                 /**< Bit mask for I2C_RXDATAP0 */
+#define _I2C_RXDOUBLEP_RXDATAP0_DEFAULT    0x00000000UL                           /**< Mode DEFAULT for I2C_RXDOUBLEP */
+#define I2C_RXDOUBLEP_RXDATAP0_DEFAULT     (_I2C_RXDOUBLEP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */
+#define _I2C_RXDOUBLEP_RXDATAP1_SHIFT      8                                      /**< Shift value for I2C_RXDATAP1 */
+#define _I2C_RXDOUBLEP_RXDATAP1_MASK       0xFF00UL                               /**< Bit mask for I2C_RXDATAP1 */
+#define _I2C_RXDOUBLEP_RXDATAP1_DEFAULT    0x00000000UL                           /**< Mode DEFAULT for I2C_RXDOUBLEP */
+#define I2C_RXDOUBLEP_RXDATAP1_DEFAULT     (_I2C_RXDOUBLEP_RXDATAP1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */
+
+/* Bit fields for I2C TXDATA */
+#define _I2C_TXDATA_RESETVALUE             0x00000000UL                      /**< Default value for I2C_TXDATA */
+#define _I2C_TXDATA_MASK                   0x000000FFUL                      /**< Mask for I2C_TXDATA */
+#define _I2C_TXDATA_TXDATA_SHIFT           0                                 /**< Shift value for I2C_TXDATA */
+#define _I2C_TXDATA_TXDATA_MASK            0xFFUL                            /**< Bit mask for I2C_TXDATA */
+#define _I2C_TXDATA_TXDATA_DEFAULT         0x00000000UL                      /**< Mode DEFAULT for I2C_TXDATA */
+#define I2C_TXDATA_TXDATA_DEFAULT          (_I2C_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDATA */
+
+/* Bit fields for I2C TXDOUBLE */
+#define _I2C_TXDOUBLE_RESETVALUE           0x00000000UL                         /**< Default value for I2C_TXDOUBLE */
+#define _I2C_TXDOUBLE_MASK                 0x0000FFFFUL                         /**< Mask for I2C_TXDOUBLE */
+#define _I2C_TXDOUBLE_TXDATA0_SHIFT        0                                    /**< Shift value for I2C_TXDATA0 */
+#define _I2C_TXDOUBLE_TXDATA0_MASK         0xFFUL                               /**< Bit mask for I2C_TXDATA0 */
+#define _I2C_TXDOUBLE_TXDATA0_DEFAULT      0x00000000UL                         /**< Mode DEFAULT for I2C_TXDOUBLE */
+#define I2C_TXDOUBLE_TXDATA0_DEFAULT       (_I2C_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */
+#define _I2C_TXDOUBLE_TXDATA1_SHIFT        8                                    /**< Shift value for I2C_TXDATA1 */
+#define _I2C_TXDOUBLE_TXDATA1_MASK         0xFF00UL                             /**< Bit mask for I2C_TXDATA1 */
+#define _I2C_TXDOUBLE_TXDATA1_DEFAULT      0x00000000UL                         /**< Mode DEFAULT for I2C_TXDOUBLE */
+#define I2C_TXDOUBLE_TXDATA1_DEFAULT       (_I2C_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */
+
+/* Bit fields for I2C IF */
+#define _I2C_IF_RESETVALUE                 0x00000010UL                    /**< Default value for I2C_IF */
+#define _I2C_IF_MASK                       0x0007FFFFUL                    /**< Mask for I2C_IF */
+#define I2C_IF_START                       (0x1UL << 0)                    /**< START Condition Interrupt Flag */
+#define _I2C_IF_START_SHIFT                0                               /**< Shift value for I2C_START */
+#define _I2C_IF_START_MASK                 0x1UL                           /**< Bit mask for I2C_START */
+#define _I2C_IF_START_DEFAULT              0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_START_DEFAULT               (_I2C_IF_START_DEFAULT << 0)    /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_RSTART                      (0x1UL << 1)                    /**< Repeated START Condition Interrupt Flag */
+#define _I2C_IF_RSTART_SHIFT               1                               /**< Shift value for I2C_RSTART */
+#define _I2C_IF_RSTART_MASK                0x2UL                           /**< Bit mask for I2C_RSTART */
+#define _I2C_IF_RSTART_DEFAULT             0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_RSTART_DEFAULT              (_I2C_IF_RSTART_DEFAULT << 1)   /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_ADDR                        (0x1UL << 2)                    /**< Address Interrupt Flag */
+#define _I2C_IF_ADDR_SHIFT                 2                               /**< Shift value for I2C_ADDR */
+#define _I2C_IF_ADDR_MASK                  0x4UL                           /**< Bit mask for I2C_ADDR */
+#define _I2C_IF_ADDR_DEFAULT               0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_ADDR_DEFAULT                (_I2C_IF_ADDR_DEFAULT << 2)     /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_TXC                         (0x1UL << 3)                    /**< Transfer Completed Interrupt Flag */
+#define _I2C_IF_TXC_SHIFT                  3                               /**< Shift value for I2C_TXC */
+#define _I2C_IF_TXC_MASK                   0x8UL                           /**< Bit mask for I2C_TXC */
+#define _I2C_IF_TXC_DEFAULT                0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_TXC_DEFAULT                 (_I2C_IF_TXC_DEFAULT << 3)      /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_TXBL                        (0x1UL << 4)                    /**< Transmit Buffer Level Interrupt Flag */
+#define _I2C_IF_TXBL_SHIFT                 4                               /**< Shift value for I2C_TXBL */
+#define _I2C_IF_TXBL_MASK                  0x10UL                          /**< Bit mask for I2C_TXBL */
+#define _I2C_IF_TXBL_DEFAULT               0x00000001UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_TXBL_DEFAULT                (_I2C_IF_TXBL_DEFAULT << 4)     /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_RXDATAV                     (0x1UL << 5)                    /**< Receive Data Valid Interrupt Flag */
+#define _I2C_IF_RXDATAV_SHIFT              5                               /**< Shift value for I2C_RXDATAV */
+#define _I2C_IF_RXDATAV_MASK               0x20UL                          /**< Bit mask for I2C_RXDATAV */
+#define _I2C_IF_RXDATAV_DEFAULT            0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_RXDATAV_DEFAULT             (_I2C_IF_RXDATAV_DEFAULT << 5)  /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_ACK                         (0x1UL << 6)                    /**< Acknowledge Received Interrupt Flag */
+#define _I2C_IF_ACK_SHIFT                  6                               /**< Shift value for I2C_ACK */
+#define _I2C_IF_ACK_MASK                   0x40UL                          /**< Bit mask for I2C_ACK */
+#define _I2C_IF_ACK_DEFAULT                0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_ACK_DEFAULT                 (_I2C_IF_ACK_DEFAULT << 6)      /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_NACK                        (0x1UL << 7)                    /**< Not Acknowledge Received Interrupt Flag */
+#define _I2C_IF_NACK_SHIFT                 7                               /**< Shift value for I2C_NACK */
+#define _I2C_IF_NACK_MASK                  0x80UL                          /**< Bit mask for I2C_NACK */
+#define _I2C_IF_NACK_DEFAULT               0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_NACK_DEFAULT                (_I2C_IF_NACK_DEFAULT << 7)     /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_MSTOP                       (0x1UL << 8)                    /**< Master STOP Condition Interrupt Flag */
+#define _I2C_IF_MSTOP_SHIFT                8                               /**< Shift value for I2C_MSTOP */
+#define _I2C_IF_MSTOP_MASK                 0x100UL                         /**< Bit mask for I2C_MSTOP */
+#define _I2C_IF_MSTOP_DEFAULT              0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_MSTOP_DEFAULT               (_I2C_IF_MSTOP_DEFAULT << 8)    /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_ARBLOST                     (0x1UL << 9)                    /**< Arbitration Lost Interrupt Flag */
+#define _I2C_IF_ARBLOST_SHIFT              9                               /**< Shift value for I2C_ARBLOST */
+#define _I2C_IF_ARBLOST_MASK               0x200UL                         /**< Bit mask for I2C_ARBLOST */
+#define _I2C_IF_ARBLOST_DEFAULT            0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_ARBLOST_DEFAULT             (_I2C_IF_ARBLOST_DEFAULT << 9)  /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_BUSERR                      (0x1UL << 10)                   /**< Bus Error Interrupt Flag */
+#define _I2C_IF_BUSERR_SHIFT               10                              /**< Shift value for I2C_BUSERR */
+#define _I2C_IF_BUSERR_MASK                0x400UL                         /**< Bit mask for I2C_BUSERR */
+#define _I2C_IF_BUSERR_DEFAULT             0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_BUSERR_DEFAULT              (_I2C_IF_BUSERR_DEFAULT << 10)  /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_BUSHOLD                     (0x1UL << 11)                   /**< Bus Held Interrupt Flag */
+#define _I2C_IF_BUSHOLD_SHIFT              11                              /**< Shift value for I2C_BUSHOLD */
+#define _I2C_IF_BUSHOLD_MASK               0x800UL                         /**< Bit mask for I2C_BUSHOLD */
+#define _I2C_IF_BUSHOLD_DEFAULT            0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_BUSHOLD_DEFAULT             (_I2C_IF_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_TXOF                        (0x1UL << 12)                   /**< Transmit Buffer Overflow Interrupt Flag */
+#define _I2C_IF_TXOF_SHIFT                 12                              /**< Shift value for I2C_TXOF */
+#define _I2C_IF_TXOF_MASK                  0x1000UL                        /**< Bit mask for I2C_TXOF */
+#define _I2C_IF_TXOF_DEFAULT               0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_TXOF_DEFAULT                (_I2C_IF_TXOF_DEFAULT << 12)    /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_RXUF                        (0x1UL << 13)                   /**< Receive Buffer Underflow Interrupt Flag */
+#define _I2C_IF_RXUF_SHIFT                 13                              /**< Shift value for I2C_RXUF */
+#define _I2C_IF_RXUF_MASK                  0x2000UL                        /**< Bit mask for I2C_RXUF */
+#define _I2C_IF_RXUF_DEFAULT               0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_RXUF_DEFAULT                (_I2C_IF_RXUF_DEFAULT << 13)    /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_BITO                        (0x1UL << 14)                   /**< Bus Idle Timeout Interrupt Flag */
+#define _I2C_IF_BITO_SHIFT                 14                              /**< Shift value for I2C_BITO */
+#define _I2C_IF_BITO_MASK                  0x4000UL                        /**< Bit mask for I2C_BITO */
+#define _I2C_IF_BITO_DEFAULT               0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_BITO_DEFAULT                (_I2C_IF_BITO_DEFAULT << 14)    /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_CLTO                        (0x1UL << 15)                   /**< Clock Low Timeout Interrupt Flag */
+#define _I2C_IF_CLTO_SHIFT                 15                              /**< Shift value for I2C_CLTO */
+#define _I2C_IF_CLTO_MASK                  0x8000UL                        /**< Bit mask for I2C_CLTO */
+#define _I2C_IF_CLTO_DEFAULT               0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_CLTO_DEFAULT                (_I2C_IF_CLTO_DEFAULT << 15)    /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_SSTOP                       (0x1UL << 16)                   /**< Slave STOP Condition Interrupt Flag */
+#define _I2C_IF_SSTOP_SHIFT                16                              /**< Shift value for I2C_SSTOP */
+#define _I2C_IF_SSTOP_MASK                 0x10000UL                       /**< Bit mask for I2C_SSTOP */
+#define _I2C_IF_SSTOP_DEFAULT              0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_SSTOP_DEFAULT               (_I2C_IF_SSTOP_DEFAULT << 16)   /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_RXFULL                      (0x1UL << 17)                   /**< Receive Buffer Full Interrupt Flag */
+#define _I2C_IF_RXFULL_SHIFT               17                              /**< Shift value for I2C_RXFULL */
+#define _I2C_IF_RXFULL_MASK                0x20000UL                       /**< Bit mask for I2C_RXFULL */
+#define _I2C_IF_RXFULL_DEFAULT             0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_RXFULL_DEFAULT              (_I2C_IF_RXFULL_DEFAULT << 17)  /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_CLERR                       (0x1UL << 18)                   /**< Clock Low Error Interrupt Flag */
+#define _I2C_IF_CLERR_SHIFT                18                              /**< Shift value for I2C_CLERR */
+#define _I2C_IF_CLERR_MASK                 0x40000UL                       /**< Bit mask for I2C_CLERR */
+#define _I2C_IF_CLERR_DEFAULT              0x00000000UL                    /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_CLERR_DEFAULT               (_I2C_IF_CLERR_DEFAULT << 18)   /**< Shifted mode DEFAULT for I2C_IF */
+
+/* Bit fields for I2C IFS */
+#define _I2C_IFS_RESETVALUE                0x00000000UL                     /**< Default value for I2C_IFS */
+#define _I2C_IFS_MASK                      0x0007FFCFUL                     /**< Mask for I2C_IFS */
+#define I2C_IFS_START                      (0x1UL << 0)                     /**< Set START Interrupt Flag */
+#define _I2C_IFS_START_SHIFT               0                                /**< Shift value for I2C_START */
+#define _I2C_IFS_START_MASK                0x1UL                            /**< Bit mask for I2C_START */
+#define _I2C_IFS_START_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_START_DEFAULT              (_I2C_IFS_START_DEFAULT << 0)    /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_RSTART                     (0x1UL << 1)                     /**< Set RSTART Interrupt Flag */
+#define _I2C_IFS_RSTART_SHIFT              1                                /**< Shift value for I2C_RSTART */
+#define _I2C_IFS_RSTART_MASK               0x2UL                            /**< Bit mask for I2C_RSTART */
+#define _I2C_IFS_RSTART_DEFAULT            0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_RSTART_DEFAULT             (_I2C_IFS_RSTART_DEFAULT << 1)   /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_ADDR                       (0x1UL << 2)                     /**< Set ADDR Interrupt Flag */
+#define _I2C_IFS_ADDR_SHIFT                2                                /**< Shift value for I2C_ADDR */
+#define _I2C_IFS_ADDR_MASK                 0x4UL                            /**< Bit mask for I2C_ADDR */
+#define _I2C_IFS_ADDR_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_ADDR_DEFAULT               (_I2C_IFS_ADDR_DEFAULT << 2)     /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_TXC                        (0x1UL << 3)                     /**< Set TXC Interrupt Flag */
+#define _I2C_IFS_TXC_SHIFT                 3                                /**< Shift value for I2C_TXC */
+#define _I2C_IFS_TXC_MASK                  0x8UL                            /**< Bit mask for I2C_TXC */
+#define _I2C_IFS_TXC_DEFAULT               0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_TXC_DEFAULT                (_I2C_IFS_TXC_DEFAULT << 3)      /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_ACK                        (0x1UL << 6)                     /**< Set ACK Interrupt Flag */
+#define _I2C_IFS_ACK_SHIFT                 6                                /**< Shift value for I2C_ACK */
+#define _I2C_IFS_ACK_MASK                  0x40UL                           /**< Bit mask for I2C_ACK */
+#define _I2C_IFS_ACK_DEFAULT               0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_ACK_DEFAULT                (_I2C_IFS_ACK_DEFAULT << 6)      /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_NACK                       (0x1UL << 7)                     /**< Set NACK Interrupt Flag */
+#define _I2C_IFS_NACK_SHIFT                7                                /**< Shift value for I2C_NACK */
+#define _I2C_IFS_NACK_MASK                 0x80UL                           /**< Bit mask for I2C_NACK */
+#define _I2C_IFS_NACK_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_NACK_DEFAULT               (_I2C_IFS_NACK_DEFAULT << 7)     /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_MSTOP                      (0x1UL << 8)                     /**< Set MSTOP Interrupt Flag */
+#define _I2C_IFS_MSTOP_SHIFT               8                                /**< Shift value for I2C_MSTOP */
+#define _I2C_IFS_MSTOP_MASK                0x100UL                          /**< Bit mask for I2C_MSTOP */
+#define _I2C_IFS_MSTOP_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_MSTOP_DEFAULT              (_I2C_IFS_MSTOP_DEFAULT << 8)    /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_ARBLOST                    (0x1UL << 9)                     /**< Set ARBLOST Interrupt Flag */
+#define _I2C_IFS_ARBLOST_SHIFT             9                                /**< Shift value for I2C_ARBLOST */
+#define _I2C_IFS_ARBLOST_MASK              0x200UL                          /**< Bit mask for I2C_ARBLOST */
+#define _I2C_IFS_ARBLOST_DEFAULT           0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_ARBLOST_DEFAULT            (_I2C_IFS_ARBLOST_DEFAULT << 9)  /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_BUSERR                     (0x1UL << 10)                    /**< Set BUSERR Interrupt Flag */
+#define _I2C_IFS_BUSERR_SHIFT              10                               /**< Shift value for I2C_BUSERR */
+#define _I2C_IFS_BUSERR_MASK               0x400UL                          /**< Bit mask for I2C_BUSERR */
+#define _I2C_IFS_BUSERR_DEFAULT            0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_BUSERR_DEFAULT             (_I2C_IFS_BUSERR_DEFAULT << 10)  /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_BUSHOLD                    (0x1UL << 11)                    /**< Set BUSHOLD Interrupt Flag */
+#define _I2C_IFS_BUSHOLD_SHIFT             11                               /**< Shift value for I2C_BUSHOLD */
+#define _I2C_IFS_BUSHOLD_MASK              0x800UL                          /**< Bit mask for I2C_BUSHOLD */
+#define _I2C_IFS_BUSHOLD_DEFAULT           0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_BUSHOLD_DEFAULT            (_I2C_IFS_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_TXOF                       (0x1UL << 12)                    /**< Set TXOF Interrupt Flag */
+#define _I2C_IFS_TXOF_SHIFT                12                               /**< Shift value for I2C_TXOF */
+#define _I2C_IFS_TXOF_MASK                 0x1000UL                         /**< Bit mask for I2C_TXOF */
+#define _I2C_IFS_TXOF_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_TXOF_DEFAULT               (_I2C_IFS_TXOF_DEFAULT << 12)    /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_RXUF                       (0x1UL << 13)                    /**< Set RXUF Interrupt Flag */
+#define _I2C_IFS_RXUF_SHIFT                13                               /**< Shift value for I2C_RXUF */
+#define _I2C_IFS_RXUF_MASK                 0x2000UL                         /**< Bit mask for I2C_RXUF */
+#define _I2C_IFS_RXUF_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_RXUF_DEFAULT               (_I2C_IFS_RXUF_DEFAULT << 13)    /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_BITO                       (0x1UL << 14)                    /**< Set BITO Interrupt Flag */
+#define _I2C_IFS_BITO_SHIFT                14                               /**< Shift value for I2C_BITO */
+#define _I2C_IFS_BITO_MASK                 0x4000UL                         /**< Bit mask for I2C_BITO */
+#define _I2C_IFS_BITO_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_BITO_DEFAULT               (_I2C_IFS_BITO_DEFAULT << 14)    /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_CLTO                       (0x1UL << 15)                    /**< Set CLTO Interrupt Flag */
+#define _I2C_IFS_CLTO_SHIFT                15                               /**< Shift value for I2C_CLTO */
+#define _I2C_IFS_CLTO_MASK                 0x8000UL                         /**< Bit mask for I2C_CLTO */
+#define _I2C_IFS_CLTO_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_CLTO_DEFAULT               (_I2C_IFS_CLTO_DEFAULT << 15)    /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_SSTOP                      (0x1UL << 16)                    /**< Set SSTOP Interrupt Flag */
+#define _I2C_IFS_SSTOP_SHIFT               16                               /**< Shift value for I2C_SSTOP */
+#define _I2C_IFS_SSTOP_MASK                0x10000UL                        /**< Bit mask for I2C_SSTOP */
+#define _I2C_IFS_SSTOP_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_SSTOP_DEFAULT              (_I2C_IFS_SSTOP_DEFAULT << 16)   /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_RXFULL                     (0x1UL << 17)                    /**< Set RXFULL Interrupt Flag */
+#define _I2C_IFS_RXFULL_SHIFT              17                               /**< Shift value for I2C_RXFULL */
+#define _I2C_IFS_RXFULL_MASK               0x20000UL                        /**< Bit mask for I2C_RXFULL */
+#define _I2C_IFS_RXFULL_DEFAULT            0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_RXFULL_DEFAULT             (_I2C_IFS_RXFULL_DEFAULT << 17)  /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_CLERR                      (0x1UL << 18)                    /**< Set CLERR Interrupt Flag */
+#define _I2C_IFS_CLERR_SHIFT               18                               /**< Shift value for I2C_CLERR */
+#define _I2C_IFS_CLERR_MASK                0x40000UL                        /**< Bit mask for I2C_CLERR */
+#define _I2C_IFS_CLERR_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_CLERR_DEFAULT              (_I2C_IFS_CLERR_DEFAULT << 18)   /**< Shifted mode DEFAULT for I2C_IFS */
+
+/* Bit fields for I2C IFC */
+#define _I2C_IFC_RESETVALUE                0x00000000UL                     /**< Default value for I2C_IFC */
+#define _I2C_IFC_MASK                      0x0007FFCFUL                     /**< Mask for I2C_IFC */
+#define I2C_IFC_START                      (0x1UL << 0)                     /**< Clear START Interrupt Flag */
+#define _I2C_IFC_START_SHIFT               0                                /**< Shift value for I2C_START */
+#define _I2C_IFC_START_MASK                0x1UL                            /**< Bit mask for I2C_START */
+#define _I2C_IFC_START_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_START_DEFAULT              (_I2C_IFC_START_DEFAULT << 0)    /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_RSTART                     (0x1UL << 1)                     /**< Clear RSTART Interrupt Flag */
+#define _I2C_IFC_RSTART_SHIFT              1                                /**< Shift value for I2C_RSTART */
+#define _I2C_IFC_RSTART_MASK               0x2UL                            /**< Bit mask for I2C_RSTART */
+#define _I2C_IFC_RSTART_DEFAULT            0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_RSTART_DEFAULT             (_I2C_IFC_RSTART_DEFAULT << 1)   /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_ADDR                       (0x1UL << 2)                     /**< Clear ADDR Interrupt Flag */
+#define _I2C_IFC_ADDR_SHIFT                2                                /**< Shift value for I2C_ADDR */
+#define _I2C_IFC_ADDR_MASK                 0x4UL                            /**< Bit mask for I2C_ADDR */
+#define _I2C_IFC_ADDR_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_ADDR_DEFAULT               (_I2C_IFC_ADDR_DEFAULT << 2)     /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_TXC                        (0x1UL << 3)                     /**< Clear TXC Interrupt Flag */
+#define _I2C_IFC_TXC_SHIFT                 3                                /**< Shift value for I2C_TXC */
+#define _I2C_IFC_TXC_MASK                  0x8UL                            /**< Bit mask for I2C_TXC */
+#define _I2C_IFC_TXC_DEFAULT               0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_TXC_DEFAULT                (_I2C_IFC_TXC_DEFAULT << 3)      /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_ACK                        (0x1UL << 6)                     /**< Clear ACK Interrupt Flag */
+#define _I2C_IFC_ACK_SHIFT                 6                                /**< Shift value for I2C_ACK */
+#define _I2C_IFC_ACK_MASK                  0x40UL                           /**< Bit mask for I2C_ACK */
+#define _I2C_IFC_ACK_DEFAULT               0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_ACK_DEFAULT                (_I2C_IFC_ACK_DEFAULT << 6)      /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_NACK                       (0x1UL << 7)                     /**< Clear NACK Interrupt Flag */
+#define _I2C_IFC_NACK_SHIFT                7                                /**< Shift value for I2C_NACK */
+#define _I2C_IFC_NACK_MASK                 0x80UL                           /**< Bit mask for I2C_NACK */
+#define _I2C_IFC_NACK_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_NACK_DEFAULT               (_I2C_IFC_NACK_DEFAULT << 7)     /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_MSTOP                      (0x1UL << 8)                     /**< Clear MSTOP Interrupt Flag */
+#define _I2C_IFC_MSTOP_SHIFT               8                                /**< Shift value for I2C_MSTOP */
+#define _I2C_IFC_MSTOP_MASK                0x100UL                          /**< Bit mask for I2C_MSTOP */
+#define _I2C_IFC_MSTOP_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_MSTOP_DEFAULT              (_I2C_IFC_MSTOP_DEFAULT << 8)    /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_ARBLOST                    (0x1UL << 9)                     /**< Clear ARBLOST Interrupt Flag */
+#define _I2C_IFC_ARBLOST_SHIFT             9                                /**< Shift value for I2C_ARBLOST */
+#define _I2C_IFC_ARBLOST_MASK              0x200UL                          /**< Bit mask for I2C_ARBLOST */
+#define _I2C_IFC_ARBLOST_DEFAULT           0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_ARBLOST_DEFAULT            (_I2C_IFC_ARBLOST_DEFAULT << 9)  /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_BUSERR                     (0x1UL << 10)                    /**< Clear BUSERR Interrupt Flag */
+#define _I2C_IFC_BUSERR_SHIFT              10                               /**< Shift value for I2C_BUSERR */
+#define _I2C_IFC_BUSERR_MASK               0x400UL                          /**< Bit mask for I2C_BUSERR */
+#define _I2C_IFC_BUSERR_DEFAULT            0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_BUSERR_DEFAULT             (_I2C_IFC_BUSERR_DEFAULT << 10)  /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_BUSHOLD                    (0x1UL << 11)                    /**< Clear BUSHOLD Interrupt Flag */
+#define _I2C_IFC_BUSHOLD_SHIFT             11                               /**< Shift value for I2C_BUSHOLD */
+#define _I2C_IFC_BUSHOLD_MASK              0x800UL                          /**< Bit mask for I2C_BUSHOLD */
+#define _I2C_IFC_BUSHOLD_DEFAULT           0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_BUSHOLD_DEFAULT            (_I2C_IFC_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_TXOF                       (0x1UL << 12)                    /**< Clear TXOF Interrupt Flag */
+#define _I2C_IFC_TXOF_SHIFT                12                               /**< Shift value for I2C_TXOF */
+#define _I2C_IFC_TXOF_MASK                 0x1000UL                         /**< Bit mask for I2C_TXOF */
+#define _I2C_IFC_TXOF_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_TXOF_DEFAULT               (_I2C_IFC_TXOF_DEFAULT << 12)    /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_RXUF                       (0x1UL << 13)                    /**< Clear RXUF Interrupt Flag */
+#define _I2C_IFC_RXUF_SHIFT                13                               /**< Shift value for I2C_RXUF */
+#define _I2C_IFC_RXUF_MASK                 0x2000UL                         /**< Bit mask for I2C_RXUF */
+#define _I2C_IFC_RXUF_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_RXUF_DEFAULT               (_I2C_IFC_RXUF_DEFAULT << 13)    /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_BITO                       (0x1UL << 14)                    /**< Clear BITO Interrupt Flag */
+#define _I2C_IFC_BITO_SHIFT                14                               /**< Shift value for I2C_BITO */
+#define _I2C_IFC_BITO_MASK                 0x4000UL                         /**< Bit mask for I2C_BITO */
+#define _I2C_IFC_BITO_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_BITO_DEFAULT               (_I2C_IFC_BITO_DEFAULT << 14)    /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_CLTO                       (0x1UL << 15)                    /**< Clear CLTO Interrupt Flag */
+#define _I2C_IFC_CLTO_SHIFT                15                               /**< Shift value for I2C_CLTO */
+#define _I2C_IFC_CLTO_MASK                 0x8000UL                         /**< Bit mask for I2C_CLTO */
+#define _I2C_IFC_CLTO_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_CLTO_DEFAULT               (_I2C_IFC_CLTO_DEFAULT << 15)    /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_SSTOP                      (0x1UL << 16)                    /**< Clear SSTOP Interrupt Flag */
+#define _I2C_IFC_SSTOP_SHIFT               16                               /**< Shift value for I2C_SSTOP */
+#define _I2C_IFC_SSTOP_MASK                0x10000UL                        /**< Bit mask for I2C_SSTOP */
+#define _I2C_IFC_SSTOP_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_SSTOP_DEFAULT              (_I2C_IFC_SSTOP_DEFAULT << 16)   /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_RXFULL                     (0x1UL << 17)                    /**< Clear RXFULL Interrupt Flag */
+#define _I2C_IFC_RXFULL_SHIFT              17                               /**< Shift value for I2C_RXFULL */
+#define _I2C_IFC_RXFULL_MASK               0x20000UL                        /**< Bit mask for I2C_RXFULL */
+#define _I2C_IFC_RXFULL_DEFAULT            0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_RXFULL_DEFAULT             (_I2C_IFC_RXFULL_DEFAULT << 17)  /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_CLERR                      (0x1UL << 18)                    /**< Clear CLERR Interrupt Flag */
+#define _I2C_IFC_CLERR_SHIFT               18                               /**< Shift value for I2C_CLERR */
+#define _I2C_IFC_CLERR_MASK                0x40000UL                        /**< Bit mask for I2C_CLERR */
+#define _I2C_IFC_CLERR_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_CLERR_DEFAULT              (_I2C_IFC_CLERR_DEFAULT << 18)   /**< Shifted mode DEFAULT for I2C_IFC */
+
+/* Bit fields for I2C IEN */
+#define _I2C_IEN_RESETVALUE                0x00000000UL                     /**< Default value for I2C_IEN */
+#define _I2C_IEN_MASK                      0x0007FFFFUL                     /**< Mask for I2C_IEN */
+#define I2C_IEN_START                      (0x1UL << 0)                     /**< START Interrupt Enable */
+#define _I2C_IEN_START_SHIFT               0                                /**< Shift value for I2C_START */
+#define _I2C_IEN_START_MASK                0x1UL                            /**< Bit mask for I2C_START */
+#define _I2C_IEN_START_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_START_DEFAULT              (_I2C_IEN_START_DEFAULT << 0)    /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_RSTART                     (0x1UL << 1)                     /**< RSTART Interrupt Enable */
+#define _I2C_IEN_RSTART_SHIFT              1                                /**< Shift value for I2C_RSTART */
+#define _I2C_IEN_RSTART_MASK               0x2UL                            /**< Bit mask for I2C_RSTART */
+#define _I2C_IEN_RSTART_DEFAULT            0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_RSTART_DEFAULT             (_I2C_IEN_RSTART_DEFAULT << 1)   /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_ADDR                       (0x1UL << 2)                     /**< ADDR Interrupt Enable */
+#define _I2C_IEN_ADDR_SHIFT                2                                /**< Shift value for I2C_ADDR */
+#define _I2C_IEN_ADDR_MASK                 0x4UL                            /**< Bit mask for I2C_ADDR */
+#define _I2C_IEN_ADDR_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_ADDR_DEFAULT               (_I2C_IEN_ADDR_DEFAULT << 2)     /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_TXC                        (0x1UL << 3)                     /**< TXC Interrupt Enable */
+#define _I2C_IEN_TXC_SHIFT                 3                                /**< Shift value for I2C_TXC */
+#define _I2C_IEN_TXC_MASK                  0x8UL                            /**< Bit mask for I2C_TXC */
+#define _I2C_IEN_TXC_DEFAULT               0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_TXC_DEFAULT                (_I2C_IEN_TXC_DEFAULT << 3)      /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_TXBL                       (0x1UL << 4)                     /**< TXBL Interrupt Enable */
+#define _I2C_IEN_TXBL_SHIFT                4                                /**< Shift value for I2C_TXBL */
+#define _I2C_IEN_TXBL_MASK                 0x10UL                           /**< Bit mask for I2C_TXBL */
+#define _I2C_IEN_TXBL_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_TXBL_DEFAULT               (_I2C_IEN_TXBL_DEFAULT << 4)     /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_RXDATAV                    (0x1UL << 5)                     /**< RXDATAV Interrupt Enable */
+#define _I2C_IEN_RXDATAV_SHIFT             5                                /**< Shift value for I2C_RXDATAV */
+#define _I2C_IEN_RXDATAV_MASK              0x20UL                           /**< Bit mask for I2C_RXDATAV */
+#define _I2C_IEN_RXDATAV_DEFAULT           0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_RXDATAV_DEFAULT            (_I2C_IEN_RXDATAV_DEFAULT << 5)  /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_ACK                        (0x1UL << 6)                     /**< ACK Interrupt Enable */
+#define _I2C_IEN_ACK_SHIFT                 6                                /**< Shift value for I2C_ACK */
+#define _I2C_IEN_ACK_MASK                  0x40UL                           /**< Bit mask for I2C_ACK */
+#define _I2C_IEN_ACK_DEFAULT               0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_ACK_DEFAULT                (_I2C_IEN_ACK_DEFAULT << 6)      /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_NACK                       (0x1UL << 7)                     /**< NACK Interrupt Enable */
+#define _I2C_IEN_NACK_SHIFT                7                                /**< Shift value for I2C_NACK */
+#define _I2C_IEN_NACK_MASK                 0x80UL                           /**< Bit mask for I2C_NACK */
+#define _I2C_IEN_NACK_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_NACK_DEFAULT               (_I2C_IEN_NACK_DEFAULT << 7)     /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_MSTOP                      (0x1UL << 8)                     /**< MSTOP Interrupt Enable */
+#define _I2C_IEN_MSTOP_SHIFT               8                                /**< Shift value for I2C_MSTOP */
+#define _I2C_IEN_MSTOP_MASK                0x100UL                          /**< Bit mask for I2C_MSTOP */
+#define _I2C_IEN_MSTOP_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_MSTOP_DEFAULT              (_I2C_IEN_MSTOP_DEFAULT << 8)    /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_ARBLOST                    (0x1UL << 9)                     /**< ARBLOST Interrupt Enable */
+#define _I2C_IEN_ARBLOST_SHIFT             9                                /**< Shift value for I2C_ARBLOST */
+#define _I2C_IEN_ARBLOST_MASK              0x200UL                          /**< Bit mask for I2C_ARBLOST */
+#define _I2C_IEN_ARBLOST_DEFAULT           0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_ARBLOST_DEFAULT            (_I2C_IEN_ARBLOST_DEFAULT << 9)  /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_BUSERR                     (0x1UL << 10)                    /**< BUSERR Interrupt Enable */
+#define _I2C_IEN_BUSERR_SHIFT              10                               /**< Shift value for I2C_BUSERR */
+#define _I2C_IEN_BUSERR_MASK               0x400UL                          /**< Bit mask for I2C_BUSERR */
+#define _I2C_IEN_BUSERR_DEFAULT            0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_BUSERR_DEFAULT             (_I2C_IEN_BUSERR_DEFAULT << 10)  /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_BUSHOLD                    (0x1UL << 11)                    /**< BUSHOLD Interrupt Enable */
+#define _I2C_IEN_BUSHOLD_SHIFT             11                               /**< Shift value for I2C_BUSHOLD */
+#define _I2C_IEN_BUSHOLD_MASK              0x800UL                          /**< Bit mask for I2C_BUSHOLD */
+#define _I2C_IEN_BUSHOLD_DEFAULT           0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_BUSHOLD_DEFAULT            (_I2C_IEN_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_TXOF                       (0x1UL << 12)                    /**< TXOF Interrupt Enable */
+#define _I2C_IEN_TXOF_SHIFT                12                               /**< Shift value for I2C_TXOF */
+#define _I2C_IEN_TXOF_MASK                 0x1000UL                         /**< Bit mask for I2C_TXOF */
+#define _I2C_IEN_TXOF_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_TXOF_DEFAULT               (_I2C_IEN_TXOF_DEFAULT << 12)    /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_RXUF                       (0x1UL << 13)                    /**< RXUF Interrupt Enable */
+#define _I2C_IEN_RXUF_SHIFT                13                               /**< Shift value for I2C_RXUF */
+#define _I2C_IEN_RXUF_MASK                 0x2000UL                         /**< Bit mask for I2C_RXUF */
+#define _I2C_IEN_RXUF_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_RXUF_DEFAULT               (_I2C_IEN_RXUF_DEFAULT << 13)    /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_BITO                       (0x1UL << 14)                    /**< BITO Interrupt Enable */
+#define _I2C_IEN_BITO_SHIFT                14                               /**< Shift value for I2C_BITO */
+#define _I2C_IEN_BITO_MASK                 0x4000UL                         /**< Bit mask for I2C_BITO */
+#define _I2C_IEN_BITO_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_BITO_DEFAULT               (_I2C_IEN_BITO_DEFAULT << 14)    /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_CLTO                       (0x1UL << 15)                    /**< CLTO Interrupt Enable */
+#define _I2C_IEN_CLTO_SHIFT                15                               /**< Shift value for I2C_CLTO */
+#define _I2C_IEN_CLTO_MASK                 0x8000UL                         /**< Bit mask for I2C_CLTO */
+#define _I2C_IEN_CLTO_DEFAULT              0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_CLTO_DEFAULT               (_I2C_IEN_CLTO_DEFAULT << 15)    /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_SSTOP                      (0x1UL << 16)                    /**< SSTOP Interrupt Enable */
+#define _I2C_IEN_SSTOP_SHIFT               16                               /**< Shift value for I2C_SSTOP */
+#define _I2C_IEN_SSTOP_MASK                0x10000UL                        /**< Bit mask for I2C_SSTOP */
+#define _I2C_IEN_SSTOP_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_SSTOP_DEFAULT              (_I2C_IEN_SSTOP_DEFAULT << 16)   /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_RXFULL                     (0x1UL << 17)                    /**< RXFULL Interrupt Enable */
+#define _I2C_IEN_RXFULL_SHIFT              17                               /**< Shift value for I2C_RXFULL */
+#define _I2C_IEN_RXFULL_MASK               0x20000UL                        /**< Bit mask for I2C_RXFULL */
+#define _I2C_IEN_RXFULL_DEFAULT            0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_RXFULL_DEFAULT             (_I2C_IEN_RXFULL_DEFAULT << 17)  /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_CLERR                      (0x1UL << 18)                    /**< CLERR Interrupt Enable */
+#define _I2C_IEN_CLERR_SHIFT               18                               /**< Shift value for I2C_CLERR */
+#define _I2C_IEN_CLERR_MASK                0x40000UL                        /**< Bit mask for I2C_CLERR */
+#define _I2C_IEN_CLERR_DEFAULT             0x00000000UL                     /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_CLERR_DEFAULT              (_I2C_IEN_CLERR_DEFAULT << 18)   /**< Shifted mode DEFAULT for I2C_IEN */
+
+/* Bit fields for I2C ROUTEPEN */
+#define _I2C_ROUTEPEN_RESETVALUE           0x00000000UL                        /**< Default value for I2C_ROUTEPEN */
+#define _I2C_ROUTEPEN_MASK                 0x00000003UL                        /**< Mask for I2C_ROUTEPEN */
+#define I2C_ROUTEPEN_SDAPEN                (0x1UL << 0)                        /**< SDA Pin Enable */
+#define _I2C_ROUTEPEN_SDAPEN_SHIFT         0                                   /**< Shift value for I2C_SDAPEN */
+#define _I2C_ROUTEPEN_SDAPEN_MASK          0x1UL                               /**< Bit mask for I2C_SDAPEN */
+#define _I2C_ROUTEPEN_SDAPEN_DEFAULT       0x00000000UL                        /**< Mode DEFAULT for I2C_ROUTEPEN */
+#define I2C_ROUTEPEN_SDAPEN_DEFAULT        (_I2C_ROUTEPEN_SDAPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_ROUTEPEN */
+#define I2C_ROUTEPEN_SCLPEN                (0x1UL << 1)                        /**< SCL Pin Enable */
+#define _I2C_ROUTEPEN_SCLPEN_SHIFT         1                                   /**< Shift value for I2C_SCLPEN */
+#define _I2C_ROUTEPEN_SCLPEN_MASK          0x2UL                               /**< Bit mask for I2C_SCLPEN */
+#define _I2C_ROUTEPEN_SCLPEN_DEFAULT       0x00000000UL                        /**< Mode DEFAULT for I2C_ROUTEPEN */
+#define I2C_ROUTEPEN_SCLPEN_DEFAULT        (_I2C_ROUTEPEN_SCLPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_ROUTEPEN */
+
+/* Bit fields for I2C ROUTELOC0 */
+#define _I2C_ROUTELOC0_RESETVALUE          0x00000000UL                         /**< Default value for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_MASK                0x00000707UL                         /**< Mask for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_SHIFT        0                                    /**< Shift value for I2C_SDALOC */
+#define _I2C_ROUTELOC0_SDALOC_MASK         0x7UL                                /**< Bit mask for I2C_SDALOC */
+#define _I2C_ROUTELOC0_SDALOC_LOC0         0x00000000UL                         /**< Mode LOC0 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_DEFAULT      0x00000000UL                         /**< Mode DEFAULT for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC1         0x00000001UL                         /**< Mode LOC1 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC2         0x00000002UL                         /**< Mode LOC2 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC3         0x00000003UL                         /**< Mode LOC3 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC4         0x00000004UL                         /**< Mode LOC4 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC5         0x00000005UL                         /**< Mode LOC5 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC6         0x00000006UL                         /**< Mode LOC6 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC7         0x00000007UL                         /**< Mode LOC7 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC0          (_I2C_ROUTELOC0_SDALOC_LOC0 << 0)    /**< Shifted mode LOC0 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_DEFAULT       (_I2C_ROUTELOC0_SDALOC_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC1          (_I2C_ROUTELOC0_SDALOC_LOC1 << 0)    /**< Shifted mode LOC1 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC2          (_I2C_ROUTELOC0_SDALOC_LOC2 << 0)    /**< Shifted mode LOC2 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC3          (_I2C_ROUTELOC0_SDALOC_LOC3 << 0)    /**< Shifted mode LOC3 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC4          (_I2C_ROUTELOC0_SDALOC_LOC4 << 0)    /**< Shifted mode LOC4 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC5          (_I2C_ROUTELOC0_SDALOC_LOC5 << 0)    /**< Shifted mode LOC5 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC6          (_I2C_ROUTELOC0_SDALOC_LOC6 << 0)    /**< Shifted mode LOC6 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC7          (_I2C_ROUTELOC0_SDALOC_LOC7 << 0)    /**< Shifted mode LOC7 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_SHIFT        8                                    /**< Shift value for I2C_SCLLOC */
+#define _I2C_ROUTELOC0_SCLLOC_MASK         0x700UL                              /**< Bit mask for I2C_SCLLOC */
+#define _I2C_ROUTELOC0_SCLLOC_LOC0         0x00000000UL                         /**< Mode LOC0 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_DEFAULT      0x00000000UL                         /**< Mode DEFAULT for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC1         0x00000001UL                         /**< Mode LOC1 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC2         0x00000002UL                         /**< Mode LOC2 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC3         0x00000003UL                         /**< Mode LOC3 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC4         0x00000004UL                         /**< Mode LOC4 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC5         0x00000005UL                         /**< Mode LOC5 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC6         0x00000006UL                         /**< Mode LOC6 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC7         0x00000007UL                         /**< Mode LOC7 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC0          (_I2C_ROUTELOC0_SCLLOC_LOC0 << 8)    /**< Shifted mode LOC0 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_DEFAULT       (_I2C_ROUTELOC0_SCLLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC1          (_I2C_ROUTELOC0_SCLLOC_LOC1 << 8)    /**< Shifted mode LOC1 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC2          (_I2C_ROUTELOC0_SCLLOC_LOC2 << 8)    /**< Shifted mode LOC2 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC3          (_I2C_ROUTELOC0_SCLLOC_LOC3 << 8)    /**< Shifted mode LOC3 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC4          (_I2C_ROUTELOC0_SCLLOC_LOC4 << 8)    /**< Shifted mode LOC4 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC5          (_I2C_ROUTELOC0_SCLLOC_LOC5 << 8)    /**< Shifted mode LOC5 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC6          (_I2C_ROUTELOC0_SCLLOC_LOC6 << 8)    /**< Shifted mode LOC6 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC7          (_I2C_ROUTELOC0_SCLLOC_LOC7 << 8)    /**< Shifted mode LOC7 for I2C_ROUTELOC0 */
+
+/** @} */
+/** @} End of group EFM32GG12B_I2C */
+/** @} End of group Parts */
+#ifdef __cplusplus
+}
+#endif
+