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cpu/stm32f0: Use {} notation for empty while loops

This commit is contained in:
Joakim Nohlgård 2016-01-26 19:58:29 +01:00
parent f551850642
commit aba4e719eb
5 changed files with 15 additions and 16 deletions

View File

@ -72,7 +72,7 @@ static void clock_init(void)
RCC->CR |= RCC_CR_HSEON;
/* wait for HSE to be ready */
while (!(RCC->CR & RCC_CR_HSERDY));
while (!(RCC->CR & RCC_CR_HSERDY)) {}
/* setup the peripheral bus prescalers */
@ -92,7 +92,7 @@ static void clock_init(void)
/* enable PLL again */
RCC->CR |= RCC_CR_PLLON;
/* wait until PLL is stable */
while(!(RCC->CR & RCC_CR_PLLRDY));
while(!(RCC->CR & RCC_CR_PLLRDY)) {}
/* configure flash latency */
@ -106,5 +106,5 @@ static void clock_init(void)
RCC->CFGR |= RCC_CFGR_SW_PLL;
/* wait for sysclock to be stable */
while (!(RCC->CFGR & RCC_CFGR_SWS_PLL));
while (!(RCC->CFGR & RCC_CFGR_SWS_PLL)) {}
}

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@ -131,7 +131,7 @@ int adc_sample(adc_t dev, int channel)
/* start single conversion */
adc->CR |= ADC_CR_ADSTART;
/* wait until conversion is complete */
while (!(adc->ISR & ADC_ISR_EOC));
while (!(adc->ISR & ADC_ISR_EOC)) {}
/* read and return result */
return (int)adc->DR;
}

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@ -64,7 +64,7 @@ void rtc_init(void)
RCC->BDCR &= ~(RCC_BDCR_LSEON);
RCC->BDCR &= ~(RCC_BDCR_LSEBYP);
RCC->BDCR |= RCC_BDCR_LSEON;
while ( (RCC->BDCR & RCC_BDCR_LSERDY) == 0 );
while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0) {}
/* Switch RTC to LSE clock source */
RCC->BDCR &= ~(RCC_BDCR_RTCSEL);
@ -80,7 +80,7 @@ void rtc_init(void)
/* Enter RTC Init mode */
RTC->ISR = 0;
RTC->ISR |= RTC_ISR_INIT;
while ( (RTC->ISR & RTC_ISR_INITF) == 0 );
while ((RTC->ISR & RTC_ISR_INITF) == 0) {}
/* Set 24-h clock */
RTC->CR |= RTC_CR_FMT;
@ -111,7 +111,7 @@ int rtc_set_time(struct tm *time)
/* Enter RTC Init mode */
RTC->ISR |= RTC_ISR_INIT;
while ( (RTC->ISR & RTC_ISR_INITF) == 0 );
while ((RTC->ISR & RTC_ISR_INITF) == 0) {}
RTC->DR = ( (((uint32_t)byte2bcd(time->tm_year - MCU_YEAR_OFFSET) << 16) & (RTC_DR_YT | RTC_DR_YU) ) |
@ -155,10 +155,10 @@ int rtc_set_alarm(struct tm *time, rtc_alarm_cb_t cb, void *arg)
/* Enter RTC Init mode */
RTC->ISR |= RTC_ISR_INIT;
while ( (RTC->ISR & RTC_ISR_INITF) == 0 );
while ((RTC->ISR & RTC_ISR_INITF) == 0) {}
RTC->CR &= ~(RTC_CR_ALRAE);
while ( (RTC->ISR & RTC_ISR_ALRAWF) == 0 );
while ((RTC->ISR & RTC_ISR_ALRAWF) == 0) {}
RTC->ALRMAR &= ~(RTC_ALRMAR_MSK1 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK4);
RTC->ALRMAR = ( (((uint32_t)byte2bcd(time->tm_mday) << 24) & (RTC_ALRMAR_DT | RTC_ALRMAR_DU) ) |
(((uint32_t)byte2bcd(time->tm_hour) << 16) & (RTC_ALRMAR_HT | RTC_ALRMAR_HU) ) |
@ -251,8 +251,7 @@ static uint8_t byte2bcd(uint8_t value)
{
uint8_t bcdhigh = 0;
while (value >= 10)
{
while (value >= 10) {
bcdhigh++;
value -= 10;
}

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@ -199,11 +199,11 @@ int spi_transfer_byte(spi_t dev, char out, char *in)
}
/* wait for an eventually previous byte to be readily transferred */
while(!(spi->SR & SPI_SR_TXE));
while(!(spi->SR & SPI_SR_TXE)) {}
/* put next byte into the output register */
*((volatile uint8_t *)(&spi->DR)) = (uint8_t)out;
/* wait until the current byte was successfully transferred */
while(!(spi->SR & SPI_SR_RXNE) );
while(!(spi->SR & SPI_SR_RXNE)) {}
/* read response byte to reset flags */
tmp = *((volatile uint8_t *)(&spi->DR));
/* 'return' response byte if wished for */
@ -240,13 +240,13 @@ void spi_poweroff(spi_t dev)
switch (dev) {
#if SPI_0_EN
case SPI_0:
while (SPI_0_DEV->SR & SPI_SR_BSY);
while (SPI_0_DEV->SR & SPI_SR_BSY) {}
SPI_0_CLKDIS();
break;
#endif
#if SPI_1_EN
case SPI_1:
while (SPI_1_DEV->SR & SPI_SR_BSY);
while (SPI_1_DEV->SR & SPI_SR_BSY) {}
SPI_1_CLKDIS();
break;
#endif

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@ -151,7 +151,7 @@ void uart_write(uart_t uart, const uint8_t *data, size_t len)
USART_TypeDef *dev = uart_port[uart];
for (size_t i = 0; i < len; i++) {
while (!(dev->ISR & USART_ISR_TXE));
while (!(dev->ISR & USART_ISR_TXE)) {}
dev->TDR = data[i];
}
}