diff --git a/cpu/efm32/families/efm32gg/Makefile b/cpu/efm32/families/efm32gg/Makefile new file mode 100644 index 0000000000..9c3e6434cd --- /dev/null +++ b/cpu/efm32/families/efm32gg/Makefile @@ -0,0 +1,6 @@ +MODULE = cpu_efm32gg + +# (file triggers compiler bug. see #5775) +SRC_NOLTO += vectors.c + +include $(RIOTBASE)/Makefile.base diff --git a/cpu/efm32/families/efm32gg/cpus.txt b/cpu/efm32/families/efm32gg/cpus.txt new file mode 100644 index 0000000000..183ee5fb2e --- /dev/null +++ b/cpu/efm32/families/efm32gg/cpus.txt @@ -0,0 +1,50 @@ +# This file is automatically generated, and should not be changed. There is +# propbably little reason to edit this file anyway, since it should already +# contain all information for the EFM32GG family of CPUs. + +# The intended usage is to grep for the exact model name, and split by spaces +# to get the required information. + +# CPU - Family - Series - Architecture - Flash base - Flash size - SRAM base - SRAM size - Crypto? - TRNG? - Radio? +efm32gg330f512 efm32gg 0 cortex-m3 0x00000000 0x00080000 0x20000000 0x00020000 0 0 0 +efm32gg295f512 efm32gg 0 cortex-m3 0x00000000 0x00080000 0x20000000 0x00020000 0 0 0 +efm32gg940f1024 efm32gg 0 cortex-m3 0x00000000 0x00100000 0x20000000 0x00020000 0 0 0 +efm32gg840f1024 efm32gg 0 cortex-m3 0x00000000 0x00100000 0x20000000 0x00020000 0 0 0 +efm32gg332f512 efm32gg 0 cortex-m3 0x00000000 0x00080000 0x20000000 0x00020000 0 0 0 +efm32gg990f512 efm32gg 0 cortex-m3 0x00000000 0x00080000 0x20000000 0x00020000 0 0 0 +efm32gg890f512 efm32gg 0 cortex-m3 0x00000000 0x00080000 0x20000000 0x00020000 0 0 0 +efm32gg232f512 efm32gg 0 cortex-m3 0x00000000 0x00080000 0x20000000 0x00020000 0 0 0 +efm32gg942f1024 efm32gg 0 cortex-m3 0x00000000 0x00100000 0x20000000 0x00020000 0 0 0 +efm32gg842f1024 efm32gg 0 cortex-m3 0x00000000 0x00100000 0x20000000 0x00020000 0 0 0 +efm32gg395f1024 efm32gg 0 cortex-m3 0x00000000 0x00100000 0x20000000 0x00020000 0 0 0 +efm32gg295f1024 efm32gg 0 cortex-m3 0x00000000 0x00100000 0x20000000 0x00020000 0 0 0 +efm32gg995f1024 efm32gg 0 cortex-m3 0x00000000 0x00100000 0x20000000 0x00020000 0 0 0 +efm32gg895f1024 efm32gg 0 cortex-m3 0x00000000 0x00100000 0x20000000 0x00020000 0 0 0 +efm32gg395f512 efm32gg 0 cortex-m3 0x00000000 0x00080000 0x20000000 0x00020000 0 0 0 +efm32gg230f512 efm32gg 0 cortex-m3 0x00000000 0x00080000 0x20000000 0x00020000 0 0 0 +efm32gg895f512 efm32gg 0 cortex-m3 0x00000000 0x00080000 0x20000000 0x00020000 0 0 0 +efm32gg390f512 efm32gg 0 cortex-m3 0x00000000 0x00080000 0x20000000 0x00020000 0 0 0 +efm32gg290f512 efm32gg 0 cortex-m3 0x00000000 0x00080000 0x20000000 0x00020000 0 0 0 +efm32gg995f512 efm32gg 0 cortex-m3 0x00000000 0x00080000 0x20000000 0x00020000 0 0 0 +efm32gg980f512 efm32gg 0 cortex-m3 0x00000000 0x00080000 0x20000000 0x00020000 0 0 0 +efm32gg940f512 efm32gg 0 cortex-m3 0x00000000 0x00080000 0x20000000 0x00020000 0 0 0 +efm32gg942f512 efm32gg 0 cortex-m3 0x00000000 0x00080000 0x20000000 0x00020000 0 0 0 +efm32gg330f1024 efm32gg 0 cortex-m3 0x00000000 0x00100000 0x20000000 0x00020000 0 0 0 +efm32gg230f1024 efm32gg 0 cortex-m3 0x00000000 0x00100000 0x20000000 0x00020000 0 0 0 +efm32gg842f512 efm32gg 0 cortex-m3 0x00000000 0x00080000 0x20000000 0x00020000 0 0 0 +efm32gg332f1024 efm32gg 0 cortex-m3 0x00000000 0x00100000 0x20000000 0x00020000 0 0 0 +efm32gg232f1024 efm32gg 0 cortex-m3 0x00000000 0x00100000 0x20000000 0x00020000 0 0 0 +efm32gg880f512 efm32gg 0 cortex-m3 0x00000000 0x00080000 0x20000000 0x00020000 0 0 0 +efm32gg840f512 efm32gg 0 cortex-m3 0x00000000 0x00080000 0x20000000 0x00020000 0 0 0 +efm32gg380f512 efm32gg 0 cortex-m3 0x00000000 0x00080000 0x20000000 0x00020000 0 0 0 +efm32gg890f1024 efm32gg 0 cortex-m3 0x00000000 0x00100000 0x20000000 0x00020000 0 0 0 +efm32gg990f1024 efm32gg 0 cortex-m3 0x00000000 0x00100000 0x20000000 0x00020000 0 0 0 +efm32gg290f1024 efm32gg 0 cortex-m3 0x00000000 0x00100000 0x20000000 0x00020000 0 0 0 +efm32gg390f1024 efm32gg 0 cortex-m3 0x00000000 0x00100000 0x20000000 0x00020000 0 0 0 +efm32gg900f1024 efm32gg 0 cortex-m3 0x00000000 0x00100000 0x20000000 0x00020000 0 0 0 +efm32gg900f512 efm32gg 0 cortex-m3 0x00000000 0x00080000 0x20000000 0x00020000 0 0 0 +efm32gg380f1024 efm32gg 0 cortex-m3 0x00000000 0x00100000 0x20000000 0x00020000 0 0 0 +efm32gg280f1024 efm32gg 0 cortex-m3 0x00000000 0x00100000 0x20000000 0x00020000 0 0 0 +efm32gg280f512 efm32gg 0 cortex-m3 0x00000000 0x00080000 0x20000000 0x00020000 0 0 0 +efm32gg980f1024 efm32gg 0 cortex-m3 0x00000000 0x00100000 0x20000000 0x00020000 0 0 0 +efm32gg880f1024 efm32gg 0 cortex-m3 0x00000000 0x00100000 0x20000000 0x00020000 0 0 0 diff --git a/cpu/efm32/families/efm32gg/system.c b/cpu/efm32/families/efm32gg/system.c new file mode 100644 index 0000000000..d453151880 --- /dev/null +++ b/cpu/efm32/families/efm32gg/system.c @@ -0,0 +1,392 @@ +/***************************************************************************//** + * @file system_efm32gg.c + * @brief CMSIS Cortex-M3 System Layer for EFM32GG devices. + * @version 5.3.3 + ****************************************************************************** + * # License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ + +#include +#include "em_device.h" + +/******************************************************************************* + ****************************** DEFINES ************************************ + ******************************************************************************/ + +/** LFRCO frequency, tuned to below frequency during manufacturing. */ +#define EFM32_LFRCO_FREQ (32768UL) +/** ULFRCO frequency. */ +#define EFM32_ULFRCO_FREQ (1000UL) + +/******************************************************************************* + ************************** LOCAL VARIABLES ******************************** + ******************************************************************************/ + +/* System oscillator frequencies. These frequencies are normally constant */ +/* for a target, but they are made configurable in order to allow run-time */ +/* handling of different boards. The crystal oscillator clocks can be set */ +/* compile time to a non-default value by defining respective EFM32_nFXO_FREQ */ +/* values according to board design. By defining the EFM32_nFXO_FREQ to 0, */ +/* one indicates that the oscillator is not present, in order to save some */ +/* SW footprint. */ + +#ifndef EFM32_HFXO_FREQ +/** HFXO frequency. */ +#define EFM32_HFXO_FREQ (48000000UL) +#endif + +/** Maximum HFRCO frequency. */ +#define EFM32_HFRCO_MAX_FREQ (28000000UL) + +/* Do not define variable if HF crystal oscillator not present */ +#if (EFM32_HFXO_FREQ > 0) +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/** System HFXO clock. */ +static uint32_t SystemHFXOClock = EFM32_HFXO_FREQ; +/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */ +#endif + +#ifndef EFM32_LFXO_FREQ +/** LFXO frequency. */ +#define EFM32_LFXO_FREQ (EFM32_LFRCO_FREQ) +#endif + +/* Do not define variable if LF crystal oscillator not present */ +#if (EFM32_LFXO_FREQ > 0) +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/** System LFXO clock. */ +static uint32_t SystemLFXOClock = EFM32_LFXO_FREQ; +/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */ +#endif + +/* Inline function to get the chip's Production Revision. */ +__STATIC_INLINE uint8_t GetProdRev(void) +{ + return ((DEVINFO->PART & _DEVINFO_PART_PROD_REV_MASK) + >> _DEVINFO_PART_PROD_REV_SHIFT); +} + +/******************************************************************************* + ************************** GLOBAL VARIABLES ******************************* + ******************************************************************************/ + +/** + * @brief + * System System Clock Frequency (Core Clock). + * + * @details + * Required CMSIS global variable that must be kept up-to-date. + */ +uint32_t SystemCoreClock = 14000000UL; + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Get the current core clock frequency. + * + * @details + * Calculate and get the current core clock frequency based on the current + * configuration. Assuming that the SystemCoreClock global variable is + * maintained, the core clock frequency is stored in that variable as well. + * This function will however calculate the core clock based on actual HW + * configuration. It will also update the SystemCoreClock global variable. + * + * @note + * This is an EFM32 proprietary function, not part of the CMSIS definition. + * + * @return + * The current core clock frequency in Hz. + ******************************************************************************/ +uint32_t SystemCoreClockGet(void) +{ + uint32_t ret; + + ret = SystemHFClockGet(); + ret >>= (CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) + >> _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT; + + /* Keep CMSIS variable up-to-date just in case */ + SystemCoreClock = ret; + + return ret; +} + +/***************************************************************************//** + * @brief + * Get the maximum core clock frequency. + * + * @note + * This is an EFM32 proprietary function, not part of the CMSIS definition. + * + * @return + * The maximum core clock frequency in Hz. + ******************************************************************************/ +uint32_t SystemMaxCoreClockGet(void) +{ + return (EFM32_HFRCO_MAX_FREQ > EFM32_HFXO_FREQ \ + ? EFM32_HFRCO_MAX_FREQ : EFM32_HFXO_FREQ); +} + +/***************************************************************************//** + * @brief + * Get the current HFCLK frequency. + * + * @note + * This is an EFM32 proprietary function, not part of the CMSIS definition. + * + * @return + * The current HFCLK frequency in Hz. + ******************************************************************************/ +uint32_t SystemHFClockGet(void) +{ + uint32_t ret; + + switch (CMU->STATUS & (CMU_STATUS_HFRCOSEL | CMU_STATUS_HFXOSEL + | CMU_STATUS_LFRCOSEL | CMU_STATUS_LFXOSEL)) { + case CMU_STATUS_LFXOSEL: +#if (EFM32_LFXO_FREQ > 0) + ret = SystemLFXOClock; +#else + /* We should not get here, since core should not be clocked. May */ + /* be caused by a misconfiguration though. */ + ret = 0; +#endif + break; + + case CMU_STATUS_LFRCOSEL: + ret = EFM32_LFRCO_FREQ; + break; + + case CMU_STATUS_HFXOSEL: +#if (EFM32_HFXO_FREQ > 0) + ret = SystemHFXOClock; +#else + /* We should not get here, since core should not be clocked. May */ + /* be caused by a misconfiguration though. */ + ret = 0; +#endif + break; + + default: /* CMU_STATUS_HFRCOSEL */ + switch (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_BAND_MASK) { + case CMU_HFRCOCTRL_BAND_28MHZ: + ret = 28000000; + break; + + case CMU_HFRCOCTRL_BAND_21MHZ: + ret = 21000000; + break; + + case CMU_HFRCOCTRL_BAND_14MHZ: + ret = 14000000; + break; + + case CMU_HFRCOCTRL_BAND_11MHZ: + ret = 11000000; + break; + + case CMU_HFRCOCTRL_BAND_7MHZ: + if ( GetProdRev() >= 19 ) { + ret = 6600000; + } else { + ret = 7000000; + } + break; + + case CMU_HFRCOCTRL_BAND_1MHZ: + if ( GetProdRev() >= 19 ) { + ret = 1200000; + } else { + ret = 1000000; + } + break; + + default: + ret = 0; + break; + } + break; + } + + return ret / (1U + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK) + >> _CMU_CTRL_HFCLKDIV_SHIFT)); +} + +/**************************************************************************//** + * @brief + * Get high frequency crystal oscillator clock frequency for target system. + * + * @note + * This is an EFM32 proprietary function, not part of the CMSIS definition. + * + * @return + * HFXO frequency in Hz. + *****************************************************************************/ +uint32_t SystemHFXOClockGet(void) +{ + /* External crystal oscillator present? */ +#if (EFM32_HFXO_FREQ > 0) + return SystemHFXOClock; +#else + return 0; +#endif +} + +/**************************************************************************//** + * @brief + * Set high frequency crystal oscillator clock frequency for target system. + * + * @note + * This function is mainly provided for being able to handle target systems + * with different HF crystal oscillator frequencies run-time. If used, it + * should probably only be used once during system startup. + * + * @note + * This is an EFM32 proprietary function, not part of the CMSIS definition. + * + * @param[in] freq + * HFXO frequency in Hz used for target. + *****************************************************************************/ +void SystemHFXOClockSet(uint32_t freq) +{ + /* External crystal oscillator present? */ +#if (EFM32_HFXO_FREQ > 0) + SystemHFXOClock = freq; + + /* Update core clock frequency if HFXO is used to clock core */ + if (CMU->STATUS & CMU_STATUS_HFXOSEL) { + /* The function will update the global variable */ + SystemCoreClockGet(); + } +#else + (void)freq; /* Unused parameter */ +#endif +} + +/**************************************************************************//** + * @brief + * Initialize the system. + * + * @details + * Do required generic HW system init. + * + * @note + * This function is invoked during system init, before the main() routine + * and any data has been initialized. For this reason, it cannot do any + * initialization of variables etc. + *****************************************************************************/ +void SystemInit(void) +{ +} + +/**************************************************************************//** + * @brief + * Get low frequency RC oscillator clock frequency for target system. + * + * @note + * This is an EFM32 proprietary function, not part of the CMSIS definition. + * + * @return + * LFRCO frequency in Hz. + *****************************************************************************/ +uint32_t SystemLFRCOClockGet(void) +{ + /* Currently we assume that this frequency is properly tuned during */ + /* manufacturing and is not changed after reset. If future requirements */ + /* for re-tuning by user, we can add support for that. */ + return EFM32_LFRCO_FREQ; +} + +/**************************************************************************//** + * @brief + * Get ultra low frequency RC oscillator clock frequency for target system. + * + * @note + * This is an EFM32 proprietary function, not part of the CMSIS definition. + * + * @return + * ULFRCO frequency in Hz. + *****************************************************************************/ +uint32_t SystemULFRCOClockGet(void) +{ + /* The ULFRCO frequency is not tuned, and can be very inaccurate */ + return EFM32_ULFRCO_FREQ; +} + +/**************************************************************************//** + * @brief + * Get low frequency crystal oscillator clock frequency for target system. + * + * @note + * This is an EFM32 proprietary function, not part of the CMSIS definition. + * + * @return + * LFXO frequency in Hz. + *****************************************************************************/ +uint32_t SystemLFXOClockGet(void) +{ + /* External crystal oscillator present? */ +#if (EFM32_LFXO_FREQ > 0) + return SystemLFXOClock; +#else + return 0; +#endif +} + +/**************************************************************************//** + * @brief + * Set low frequency crystal oscillator clock frequency for target system. + * + * @note + * This function is mainly provided for being able to handle target systems + * with different HF crystal oscillator frequencies run-time. If used, it + * should probably only be used once during system startup. + * + * @note + * This is an EFM32 proprietary function, not part of the CMSIS definition. + * + * @param[in] freq + * LFXO frequency in Hz used for target. + *****************************************************************************/ +void SystemLFXOClockSet(uint32_t freq) +{ + /* External crystal oscillator present? */ +#if (EFM32_LFXO_FREQ > 0) + SystemLFXOClock = freq; + + /* Update core clock frequency if LFXO is used to clock core */ + if (CMU->STATUS & CMU_STATUS_LFXOSEL) { + /* The function will update the global variable */ + SystemCoreClockGet(); + } +#else + (void)freq; /* Unused parameter */ +#endif +} diff --git a/cpu/efm32/families/efm32gg/vectors.c b/cpu/efm32/families/efm32gg/vectors.c new file mode 100644 index 0000000000..c1b235bbc0 --- /dev/null +++ b/cpu/efm32/families/efm32gg/vectors.c @@ -0,0 +1,113 @@ +/* + * Copyright (C) 2015-2017 Freie Universität Berlin + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup cpu_efm32gg + * @{ + * + * @file + * @brief Startup code and interrupt vector definition + * + * @author Hauke Petersen + * @author Bas Stottelaar + * + * @} + */ + +#include "vectors_cortexm.h" + +/* define a local dummy handler as it needs to be in the same compilation unit + * as the alias definition */ +void dummy_handler(void) +{ + dummy_handler_default(); +} + +/* Silicon Labs specific interrupt vector */ +WEAK_DEFAULT void isr_dma(void); +WEAK_DEFAULT void isr_gpio_even(void); +WEAK_DEFAULT void isr_timer0(void); +WEAK_DEFAULT void isr_usart0_rx(void); +WEAK_DEFAULT void isr_usart0_tx(void); +WEAK_DEFAULT void isr_usb(void); +WEAK_DEFAULT void isr_acmp0(void); +WEAK_DEFAULT void isr_adc0(void); +WEAK_DEFAULT void isr_dac0(void); +WEAK_DEFAULT void isr_i2c0(void); +WEAK_DEFAULT void isr_i2c1(void); +WEAK_DEFAULT void isr_gpio_odd(void); +WEAK_DEFAULT void isr_timer1(void); +WEAK_DEFAULT void isr_timer2(void); +WEAK_DEFAULT void isr_timer3(void); +WEAK_DEFAULT void isr_usart1_rx(void); +WEAK_DEFAULT void isr_usart1_tx(void); +WEAK_DEFAULT void isr_lesense(void); +WEAK_DEFAULT void isr_usart2_rx(void); +WEAK_DEFAULT void isr_usart2_tx(void); +WEAK_DEFAULT void isr_uart0_rx(void); +WEAK_DEFAULT void isr_uart0_tx(void); +WEAK_DEFAULT void isr_uart1_rx(void); +WEAK_DEFAULT void isr_uart1_tx(void); +WEAK_DEFAULT void isr_leuart0(void); +WEAK_DEFAULT void isr_leuart1(void); +WEAK_DEFAULT void isr_letimer0(void); +WEAK_DEFAULT void isr_pcnt0(void); +WEAK_DEFAULT void isr_pcnt1(void); +WEAK_DEFAULT void isr_pcnt2(void); +WEAK_DEFAULT void isr_rtc(void); +WEAK_DEFAULT void isr_burtc(void); +WEAK_DEFAULT void isr_cmu(void); +WEAK_DEFAULT void isr_vcmp(void); +WEAK_DEFAULT void isr_lcd(void); +WEAK_DEFAULT void isr_msc(void); +WEAK_DEFAULT void isr_aes(void); +WEAK_DEFAULT void isr_ebi(void); +WEAK_DEFAULT void isr_emu(void); + +/* interrupt vector table */ +ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = { + [ 0] = isr_dma, /* DMA */ + [ 1] = isr_gpio_even, /* GPIO_EVEN */ + [ 2] = isr_timer0, /* TIMER0 */ + [ 3] = isr_usart0_rx, /* USART0_RX */ + [ 4] = isr_usart0_tx, /* USART0_TX */ + [ 5] = isr_usb, /* USB */ + [ 6] = isr_acmp0, /* ACMP0 */ + [ 7] = isr_adc0, /* ADC0 */ + [ 8] = isr_dac0, /* DAC0 */ + [ 9] = isr_i2c0, /* I2C0 */ + [10] = isr_i2c1, /* I2C1 */ + [11] = isr_gpio_odd, /* GPIO_ODD */ + [12] = isr_timer1, /* TIMER1 */ + [13] = isr_timer2, /* TIMER2 */ + [14] = isr_timer3, /* TIMER3 */ + [15] = isr_usart1_rx, /* USART1_RX */ + [16] = isr_usart1_tx, /* USART1_TX */ + [17] = isr_lesense, /* LESENSE */ + [18] = isr_usart2_rx, /* USART2_RX */ + [19] = isr_usart2_tx, /* USART2_TX */ + [20] = isr_uart0_rx, /* UART0_RX */ + [21] = isr_uart0_tx, /* UART0_TX */ + [22] = isr_uart1_rx, /* UART1_RX */ + [23] = isr_uart1_tx, /* UART1_TX */ + [24] = isr_leuart0, /* LEUART0 */ + [25] = isr_leuart1, /* LEUART1 */ + [26] = isr_letimer0, /* LETIMER0 */ + [27] = isr_pcnt0, /* PCNT0 */ + [28] = isr_pcnt1, /* PCNT1 */ + [29] = isr_pcnt2, /* PCNT2 */ + [30] = isr_rtc, /* RTC */ + [31] = isr_burtc, /* BURTC */ + [32] = isr_cmu, /* CMU */ + [33] = isr_vcmp, /* VCMP */ + [34] = isr_lcd, /* LCD */ + [35] = isr_msc, /* MSC */ + [36] = isr_aes, /* AES */ + [37] = isr_ebi, /* EBI */ + [38] = isr_emu, /* EMU */ +};