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19789: cpu/nrf5x/periph/wdt: enable support for nRF53/nRF9160 r=benpicco a=dylad ### Contribution description This PR enables support for the watchdog driver on nRF53. This MCU has two watchdog peripherals, for now, it only uses the first one. The use of the second watchdog can be add in a followup PR later. ### Testing procedure Flash and play with `tests/periph/wdt` application. ### Issues/PRs references None. 19796: boards/b_u585i_ iot02a/periph usbdev r=benpicco a=gschorcht ### Contribution description This PR adds the USB OTG support for STM32U5 and the `b_u585i_iot02a` board. This PR includes PR #19795 since it uses directly the changes made in PR #19795. ### Testing procedure Compile and flash ``` BOARD=b-u585i-iot02a make -C tests/sys/usbus_cdc_ecm/ flash term ``` Use the `sudo dmesg` command to get the kernel messages. ```pyhon [766948.556645] usb 1-2.2: new full-speed USB device number 108 using xhci_hcd [766948.658688] usb 1-2.2: New USB device found, idVendor=1209, idProduct=7d00, bcdDevice= 1.00 [766948.658696] usb 1-2.2: New USB device strings: Mfr=3, Product=2, SerialNumber=4 [766948.658699] usb 1-2.2: Product: b-u585i-iot02a [766948.658702] usb 1-2.2: Manufacturer: RIOT-os.org [766948.658704] usb 1-2.2: SerialNumber: AA140057DA41D467 [766948.668681] cdc_ether 1-2.2:1.0 usb0: register 'cdc_ether' at usb-0000:00:14.0-2.2, CDC Ethernet Device, ea:dc:44:71:d9:24 [766948.743250] cdc_ether 1-2.2:1.0 enxeadc4471d924: renamed from usb0 ``` Use the `ifconfig` command on the node to determine the IPv6 LLUA and ping the node. ``` ping6 -c 3 fe80::e8dc:44ff:fe71:c524%enxeadc4471d924 PING fe80::e8dc:44ff:fe71:c524%enxeadc4471d924(fe80::e8dc:44ff:fe71:c524%enxeadc4471d924) 56 data bytes 64 bytes from fe80::e8dc:44ff:fe71:c524%enxeadc4471d924: icmp_seq=1 ttl=64 time=0.523 ms 64 bytes from fe80::e8dc:44ff:fe71:c524%enxeadc4471d924: icmp_seq=2 ttl=64 time=0.546 ms 64 bytes from fe80::e8dc:44ff:fe71:c524%enxeadc4471d924: icmp_seq=3 ttl=64 time=0.599 ms ``` ### Issues/PRs references Includes PR #19795 19802: cpu/nrf53: enable flashpage support r=benpicco a=dylad ### Contribution description This PR enables flashpage support on nRF53 family. The peripheral is identical to nRF52, just add the flashpage configuration and enable the module in both Makefiles.features and Kconfig. ### Testing procedure run `/tests/periph/flashpage` on `nrf5340dk-app` output of `make BOARD=nrf5340dk-app flash test` ``` /home/dylan/work/RIOT/dist/tools/pyterm/pyterm -p "/dev/ttyACM0" -b "115200" --no-reconnect --noprefix --no-repeat-command-on-empty-line Twisted not available, please install it if you want to use pyterm's JSON capabilities Connect to serial port /dev/ttyACM0 Welcome to pyterm! Type '/exit' to exit. > > test_last_raw > test_last_raw wrote raw short buffer to last flash page > help help Command Description --------------------------------------- info Show information about pages dump Dump the selected page to STDOUT dump_local Dump the local page buffer to STDOUT read Copy the given page to the local page buffer and dump to STDOUT write Write the local page buffer to the given page write_raw Write (ASCII, max 64B) data to the given address erase Erase the given page buffer edit Write bytes to the local page buffer test Write and verify test pattern test_last_pagewise Write and verify test pattern on last page available test_last_pagewise test_reserved_pagewise Write and verify short write on reserved page test_last_raw Write and verify raw short write on last page available > test_last_pagewise wrote local page buffer to last flash page > help help Command Description --------------------------------------- info Show information about pages dump Dump the selected page to STDOUT dump_local Dump the local page buffer to STDOUT read Copy the given page to the local page buffer and dump to STDOUT write Write the local page buffer to the given page write_raw Write (ASCII, max 64B) data to the given address erase Erase the given page buffer edit Write bytes to the local page buffer test Write and verify test pattern test_last_pagewise Write and verify test pattern on last page available test_reserved_pagewise Write and verify short write on reserved page test_reserved_pagewise test_last_raw Write and verify raw short write on last page available > test_reserved_pagewise Reserved page num: 5 Since the last firmware update this test has been run 0 times wrote local page buffer to reserved flash page When running on a bootloader, as an extra check, try restarting the board and check whether this application still comes up. > help help Command Description --------------------------------------- info Show information about pages dump Dump the selected page to STDOUT dump_local Dump the local page buffer to STDOUT read Copy the given page to the local page buffer and dump to STDOUT write Write the local page buffer to the given page write_raw Write (ASCII, max 64B) data to the given address erase Erase the given page buffer edit Write bytes to the local page buffer test Write and verify test pattern test_last_pagewise Write and verify test pattern on last page available test_reserved_pagewise Write and verify short write on reserved page test_last_raw Write and verify raw short write on last page available > make : on quitte le répertoire « /home/dylan/work/RIOT/tests/periph/flashpage » ``` ### Issues/PRs references None. 19803: cpu/nrf5x_common: rework LFCLK source selection r=benpicco a=dylad ### Contribution description This PR changes the source selection of LFCLK for all nRF families. This idea is to use the values provided by Nordic vendor files to properly populate the source of the LFCLK. Then setup a per CPU check to ensure the value provided at board level is fine. In the end, the LFCLK source selection is a mere assignment. The selection of the LFCLK source is still done at board level. I also add a bit of documentation to help users to select another value if needed. I'll provide in a followup PR, `periph_rtt` support for both nRF9160 and nRF53. ### Testing procedure CI should be enough I think. Otherwise, one can ran tests/periph/rtt on any nRF51-based board and any nRF52-based board. You can also change the LFCLK source at board level to ensure the guards are doing their jobs. ### Issues/PRs references None. Co-authored-by: Dylan Laduranty <dylan.laduranty@mesotic.com> Co-authored-by: Gunar Schorcht <gunar@schorcht.net>
This commit is contained in:
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commit
a345e00fa6
@ -17,6 +17,10 @@ config BOARD_B_U585I_IOT02A
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select HAS_PERIPH_I2C
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select HAS_PERIPH_TIMER
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select HAS_PERIPH_UART
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select HAS_PERIPH_USBDEV
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# Put other features for this board (in alphabetical order)
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select HAS_TINYUSB_DEVICE
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# Clock configuration
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select BOARD_HAS_LSE
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@ -5,5 +5,7 @@ CPU_MODEL = stm32u585ai
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FEATURES_PROVIDED += periph_i2c
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FEATURES_PROVIDED += periph_timer
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FEATURES_PROVIDED += periph_uart
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FEATURES_PROVIDED += periph_usbdev
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# Put other features for this board (in alphabetical order)
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FEATURES_PROVIDED += tinyusb_device
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@ -27,6 +27,7 @@
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#include "periph_cpu.h"
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#include "clk_conf.h"
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#include "cfg_timer_tim5.h"
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#include "cfg_usb_otg_fs_u5.h"
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#ifdef __cplusplus
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extern "C" {
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@ -34,7 +34,12 @@ extern "C" {
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* @{
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*/
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#define CLOCK_HFCLK (1) /* external crystal */
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#define CLOCK_LFCLK (0) /* internal RC oscillator */
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/* LFCLK Source clock selection:*/
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/* - CLOCK_LFCLKSRC_SRC_RC: internal RC oscillator
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* - CLOCK_LFCLKSRC_SRC_Xtal: 32.768 kHz crystal
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* - CLOCK_LFCLKSRC_SRC_Synth: derived from HFCLK */
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#define CLOCK_LFCLK (CLOCK_LFCLKSRC_SRC_RC) /**< LFCLK Source */
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/** @} */
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/**
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@ -35,9 +35,11 @@
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#define CLOCK_HFCLK (16U) /* set to 0: internal RC oscillator
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16: 16MHz crystal
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32: 32MHz crystal */
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#define CLOCK_LFCLK (0) /* set to 0: internal RC oscillator
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* 1: 32.768 kHz crystal
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* 2: derived from HFCLK */
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/* LFCLK Source clock selection:*/
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/* - CLOCK_LFCLKSRC_SRC_RC: internal RC oscillator
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* - CLOCK_LFCLKSRC_SRC_Xtal: 32.768 kHz crystal
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* - CLOCK_LFCLKSRC_SRC_Synth: derived from HFCLK */
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#define CLOCK_LFCLK (CLOCK_LFCLKSRC_SRC_RC) /**< LFCLK Source */
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/** @} */
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#ifdef __cplusplus
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@ -35,9 +35,11 @@
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#define CLOCK_HFCLK (16U) /* set to 0: internal RC oscillator
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16: 16MHz crystal
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32: 32MHz crystal */
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#define CLOCK_LFCLK (1) /* set to 0: internal RC oscillator
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* 1: 32.768 kHz crystal
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* 2: derived from HFCLK */
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/* LFCLK Source clock selection:*/
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/* - CLOCK_LFCLKSRC_SRC_RC: internal RC oscillator
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* - CLOCK_LFCLKSRC_SRC_Xtal: 32.768 kHz crystal
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* - CLOCK_LFCLKSRC_SRC_Synth: derived from HFCLK */
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#define CLOCK_LFCLK (CLOCK_LFCLKSRC_SRC_Xtal) /**< LFCLK Source */
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/** @} */
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#ifdef __cplusplus
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@ -33,9 +33,11 @@ extern "C" {
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*/
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#define CLOCK_HFCLK (32U) /* set to 0: internal RC oscillator
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* 32: 32MHz crystal */
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#define CLOCK_LFCLK (0) /* set to 0: internal RC oscillator
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* 1: 32.768 kHz crystal
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* 2: derived from HFCLK */
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/* LFCLK Source clock selection:*/
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/* - CLOCK_LFCLKSRC_SRC_RC: internal RC oscillator
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* - CLOCK_LFCLKSRC_SRC_Xtal: 32.768 kHz crystal
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* - CLOCK_LFCLKSRC_SRC_Synth: derived from HFCLK */
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#define CLOCK_LFCLK (CLOCK_LFCLKSRC_SRC_RC) /**< LFCLK Source */
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/** @} */
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#ifdef __cplusplus
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@ -33,9 +33,11 @@ extern "C" {
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*/
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#define CLOCK_HFCLK (32U) /* set to 0: internal RC oscillator
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* 32: 32MHz crystal */
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#define CLOCK_LFCLK (1) /* set to 0: internal RC oscillator
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* 1: 32.768 kHz crystal
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* 2: derived from HFCLK */
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/* LFCLK Source clock selection:*/
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/* - CLOCK_LFCLKSRC_SRC_RC: internal RC oscillator
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* - CLOCK_LFCLKSRC_SRC_Xtal: 32.768 kHz crystal
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* - CLOCK_LFCLKSRC_SRC_Synth: derived from HFCLK */
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#define CLOCK_LFCLK (CLOCK_LFCLKSRC_SRC_Xtal) /**< LFCLK Source */
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/** @} */
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#ifdef __cplusplus
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63
boards/common/stm32/include/cfg_usb_otg_fs_u5.h
Normal file
63
boards/common/stm32/include/cfg_usb_otg_fs_u5.h
Normal file
@ -0,0 +1,63 @@
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/*
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* Copyright (C) 2019 Koen Zandberg
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* 2023 Gunar Schorcht
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_common_stm32
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* @{
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*
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* @file
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* @brief Common configuration for STM32 OTG FS peripheral for U5 family
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*
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* @author Koen Zandberg <koen@bergzand.net>
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* @author Gunar Schorcht <gunar@schorcht.net>
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*/
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#ifndef CFG_USB_OTG_FS_U5_H
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#define CFG_USB_OTG_FS_U5_H
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#include "periph_cpu.h"
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#include "usbdev_synopsys_dwc2.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Enable the full speed USB OTG peripheral
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*/
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#define DWC2_USB_OTG_FS_ENABLED
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/**
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* @brief Common USB OTG FS configuration
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*/
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static const dwc2_usb_otg_fshs_config_t dwc2_usb_otg_fshs_config[] = {
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{
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.periph = USB_OTG_FS_BASE,
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.type = DWC2_USB_OTG_FS,
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.phy = DWC2_USB_OTG_PHY_BUILTIN,
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.rcc_mask = RCC_AHB2ENR1_OTGEN,
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.irqn = OTG_FS_IRQn,
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.ahb = AHB2,
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.dm = GPIO_PIN(PORT_A, 11),
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.dp = GPIO_PIN(PORT_A, 12),
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.af = GPIO_AF10,
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}
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};
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/**
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* @brief Number of available USB OTG peripherals
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*/
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#define USBDEV_NUMOF ARRAY_SIZE(dwc2_usb_otg_fshs_config)
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#ifdef __cplusplus
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}
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#endif
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#endif /* CFG_USB_OTG_FS_U5_H */
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/** @} */
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@ -31,7 +31,7 @@ extern "C" {
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#define CLOCK_CORECLOCK MHZ(128)
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/**
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* @name HF Clock configuration
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* @name Clock configuration
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*
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*
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* @{
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@ -40,7 +40,12 @@ extern "C" {
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/* CLOCK_HFCLKSRC_SRC_HFXO to use external 32MHz crystal
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* CLOCK_HFCLKSRC_SRC_HFINT to use internal crystal */
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#define CLOCK_HFCLK (CLOCK_HFCLKSRC_SRC_HFXO) /**< HFCLK Source selection */
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#define CLOCK_LFCLK (3) /**< LFCLK Source selection */
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/* LFCLK Source clock selection:*/
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/* - CLOCK_LFCLKSRC_SRC_LFRC: 32.768 kHz RC oscillator
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* - CLOCK_LFCLKSRC_SRC_LFXO: 32.768 kHz crystal oscillator
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* - CLOCK_LFCLKSRC_SRC_LFSYNT: 32.768 kHz synthesized from HFCLK*/
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#define CLOCK_LFCLK (CLOCK_LFCLKSRC_SRC_LFXO) /**< LFCLK Source */
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/** @} */
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/**
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@ -34,8 +34,10 @@ extern "C" {
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*/
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#define CLOCK_HFCLK (32U) /**< set to 0: internal RC oscillator
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* 32: 32MHz crystal */
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#define CLOCK_LFCLK (3) /**< set to 0: internal RC oscillator
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* 3: High Accuracy oscillator */
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/* LFCLK Source clock selection:*/
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/* - CLOCK_LFCLKSRC_SRC_LFRC: 32.768 kHz RC oscillator
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* - CLOCK_LFCLKSRC_SRC_LFXO: 32.768 kHz crystal oscillator */
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#define CLOCK_LFCLK (CLOCK_LFCLKSRC_SRC_LFXO) /**< LFCLK Source */
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/** @} */
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/**
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@ -25,6 +25,15 @@
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#include "periph/init.h"
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#include "stdio_base.h"
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/**
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* @brief LFCLK Clock selection configuration guard
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*/
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#if ((CLOCK_LFCLK != CLOCK_LFCLKSRC_SRC_RC) && \
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(CLOCK_LFCLK != CLOCK_LFCLKSRC_SRC_Xtal) && \
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(CLOCK_LFCLK != CLOCK_LFCLKSRC_SRC_Synth))
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#error "LFCLK init: CLOCK_LFCLK has invalid value"
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#endif
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/**
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* @brief Initialize the CPU, set IRQ priorities
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*/
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@ -35,6 +35,15 @@ static bool ftpan_32(void);
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static bool ftpan_37(void);
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static bool ftpan_36(void);
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/**
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* @brief LFCLK Clock selection configuration guard
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*/
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#if ((CLOCK_LFCLK != CLOCK_LFCLKSRC_SRC_RC) && \
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(CLOCK_LFCLK != CLOCK_LFCLKSRC_SRC_Xtal) && \
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(CLOCK_LFCLK != CLOCK_LFCLKSRC_SRC_Synth))
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#error "LFCLK init: CLOCK_LFCLK has invalid value"
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#endif
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/**
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* @brief Initialize the CPU, set IRQ priorities
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*/
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@ -10,10 +10,15 @@ config CPU_FAM_NRF53
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bool
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select HAS_CPU_NRF53
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select HAS_PERIPH_CPUID
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select HAS_PERIPH_FLASHPAGE
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select HAS_PERIPH_FLASHPAGE_IN_ADDRESS_SPACE
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select HAS_PERIPH_FLASHPAGE_PAGEWISE
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select HAS_PERIPH_GPIO
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select HAS_PERIPH_GPIO_IRQ
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select HAS_PERIPH_TIMER_PERIODIC
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select HAS_PERIPH_UART_MODECFG
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select HAS_PERIPH_WDT
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select HAS_PERIPH_WDT_CB
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## CPU Models
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config CPU_MODEL_NRF5340_APP
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@ -27,6 +27,15 @@
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#include "stdio_base.h"
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#include "board.h"
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/**
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* @brief LFCLK Clock selection configuration guard
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*/
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#if ((CLOCK_LFCLK != CLOCK_LFCLKSRC_SRC_LFRC) && \
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(CLOCK_LFCLK != CLOCK_LFCLKSRC_SRC_LFXO) && \
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(CLOCK_LFCLK != CLOCK_LFCLKSRC_SRC_LFSYNT))
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#error "LFCLK init: CLOCK_LFCLK has invalid value"
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#endif
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/**
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* @brief Initialize the CPU, set IRQ priorities
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*/
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@ -52,6 +52,21 @@ extern "C" {
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#endif /* def CPU_MODEL_NRF5340_APP */
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/** @} */
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/**
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* @brief Flash page configuration
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* @{
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*/
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#define FLASHPAGE_SIZE (4096U) /**< Size of a page in bytes */
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#define FLASHPAGE_NUMOF (256U) /**< Total number of flash pages */
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/* The minimum block size which can be written is 4B. However, the erase
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* block is always FLASHPAGE_SIZE.
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*/
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#define FLASHPAGE_WRITE_BLOCK_SIZE (4U) /**< Minimum block size */
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/* Writing should be always 4 bytes aligned */
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#define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (4U) /**< Mandatory alignment */
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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@ -1,13 +1,14 @@
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# Put defined MCU peripherals here (in alphabetical order)
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FEATURES_PROVIDED += periph_cpuid
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FEATURES_PROVIDED += periph_gpio periph_gpio_irq
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FEATURES_PROVIDED += periph_timer_periodic
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FEATURES_PROVIDED += periph_uart_modecfg
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ifeq (,$(filter nrf5340_app,$(CPU_MODEL)))
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FEATURES_PROVIDED += periph_flashpage
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FEATURES_PROVIDED += periph_flashpage_in_address_space
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FEATURES_PROVIDED += periph_flashpage_pagewise
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FEATURES_PROVIDED += periph_gpio periph_gpio_irq
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FEATURES_PROVIDED += periph_timer_periodic
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FEATURES_PROVIDED += periph_uart_modecfg
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FEATURES_PROVIDED += periph_wdt periph_wdt_cb
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ifeq (,$(filter nrf5340_app,$(CPU_MODEL)))
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FEATURES_PROVIDED += periph_gpio_ll periph_gpio_ll_irq periph_gpio_ll_irq_unmask
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endif
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@ -16,7 +17,6 @@ ifeq (,$(filter nrf9160 nrf5340_app,$(CPU_MODEL)))
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FEATURES_PROVIDED += periph_hwrng
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FEATURES_PROVIDED += periph_rtt_overflow
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FEATURES_PROVIDED += periph_temperature
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FEATURES_PROVIDED += periph_wdt periph_wdt_cb
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# Various other features (if any)
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FEATURES_PROVIDED += ble_nimble
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@ -23,23 +23,16 @@
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#include "nrf_clock.h"
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#include "periph_conf.h"
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/* make sure both clocks are configured */
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/* make HFCLK clock is configured */
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#ifndef CLOCK_HFCLK
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#error "Clock init: CLOCK_HFCLK is not defined by your board!"
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#endif
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#ifndef CLOCK_LFCLK
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#error "Clock init: CLOCK_LFCLK is not defined by your board!"
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#endif
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/* Add compatibility wrapper defines for nRF families with Cortex-M33 core */
|
||||
#ifdef NRF_CLOCK_S
|
||||
#define NRF_CLOCK NRF_CLOCK_S
|
||||
#endif
|
||||
|
||||
#ifdef CLOCK_LFCLKSRC_SRC_LFRC
|
||||
#define CLOCK_LFCLKSRC_SRC_RC CLOCK_LFCLKSRC_SRC_LFRC
|
||||
#endif
|
||||
|
||||
static unsigned _hfxo_requests = 0;
|
||||
|
||||
void clock_init_hf(void)
|
||||
@ -92,17 +85,9 @@ void clock_start_lf(void)
|
||||
return;
|
||||
}
|
||||
|
||||
#if (CLOCK_LFCLK == 0)
|
||||
NRF_CLOCK->LFCLKSRC = (CLOCK_LFCLKSRC_SRC_RC);
|
||||
#elif (CLOCK_LFCLK == 1)
|
||||
NRF_CLOCK->LFCLKSRC = (CLOCK_LFCLKSRC_SRC_Xtal);
|
||||
#elif (CLOCK_LFCLK == 2)
|
||||
NRF_CLOCK->LFCLKSRC = (CLOCK_LFCLKSRC_SRC_Synth);
|
||||
#elif (CLOCK_LFCLK == 3)
|
||||
NRF_CLOCK->LFCLKSRC = (CLOCK_LFCLKSRC_SRC_LFXO);
|
||||
#else
|
||||
#error "LFCLK init: CLOCK_LFCLK has invalid value"
|
||||
#endif
|
||||
/* Select LFCLK source */
|
||||
NRF_CLOCK->LFCLKSRC = CLOCK_LFCLK;
|
||||
|
||||
/* enable LF clock */
|
||||
NRF_CLOCK->EVENTS_LFCLKSTARTED = 0;
|
||||
NRF_CLOCK->TASKS_LFCLKSTART = 1;
|
||||
|
||||
@ -42,6 +42,18 @@
|
||||
#define NRF_WDT_HALT_MODE (WDT_CONFIG_HALT_Run)
|
||||
#endif
|
||||
|
||||
/* Compatibility wrapper for nRF53/nRF9160 */
|
||||
#ifdef NRF_WDT0_S
|
||||
#define NRF_WDT NRF_WDT0_S
|
||||
#elif defined(NRF_WDT_S)
|
||||
#define NRF_WDT NRF_WDT_S
|
||||
#endif
|
||||
|
||||
/* Wrapper around vendor files inconsistency */
|
||||
#ifdef WDT_RUNSTATUS_RUNSTATUSWDT_Running
|
||||
#define WDT_RUNSTATUS_RUNSTATUS_Running WDT_RUNSTATUS_RUNSTATUSWDT_Running
|
||||
#endif
|
||||
|
||||
#ifdef MODULE_PERIPH_WDT_CB
|
||||
static wdt_cb_t wdt_cb;
|
||||
static void *wdt_arg;
|
||||
|
||||
@ -19,6 +19,8 @@ config CPU_FAM_NRF9160
|
||||
select HAS_PERIPH_TIMER_PERIODIC
|
||||
select HAS_PERIPH_UART_MODECFG
|
||||
select HAS_PERIPH_SPI_GPIO_MODE
|
||||
select HAS_PERIPH_WDT
|
||||
select HAS_PERIPH_WDT_CB
|
||||
|
||||
## CPU Models
|
||||
config CPU_MODEL_NRF9160
|
||||
|
||||
@ -25,6 +25,14 @@
|
||||
#include "periph/init.h"
|
||||
#include "stdio_base.h"
|
||||
|
||||
/**
|
||||
* @brief LFCLK Clock selection configuration guard
|
||||
*/
|
||||
#if ((CLOCK_LFCLK != CLOCK_LFCLKSRC_SRC_LFRC) && \
|
||||
(CLOCK_LFCLK != CLOCK_LFCLKSRC_SRC_LFXO))
|
||||
#error "LFCLK init: CLOCK_LFCLK has invalid value"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Initialize the CPU, set IRQ priorities
|
||||
*/
|
||||
|
||||
@ -76,6 +76,8 @@ $(call target-export-variables,$(VECTORS_O),CPU_LINE)
|
||||
# Add this define to skip the inclusion of the system_stm32xxxx.h header files
|
||||
# which are only used for STM32 system includes and not of interest for RIOT.
|
||||
CFLAGS += -D__SYSTEM_STM32$(call uppercase,$(CPU_FAM))XX_H
|
||||
# C0, G0, H7, L5 and U5 use SYSTEM_STM32..XX_H instead
|
||||
CFLAGS += -DSYSTEM_STM32$(call uppercase,$(CPU_FAM))XX_H
|
||||
|
||||
ifneq (,$(filter STM32F030x4 STM32MP157Cxx,$(CPU_LINE)))
|
||||
STM32CMSIS_INCLUDE_DIR = $(RIOTCPU)/stm32/include/vendor/cmsis/$(CPU_FAM)/Include
|
||||
|
||||
@ -101,26 +101,6 @@
|
||||
#error "Invalid MSI clock"
|
||||
#endif
|
||||
|
||||
/* Configure 48MHz clock source */
|
||||
#define CLOCK_PLLQ ((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_Q
|
||||
|
||||
#if CLOCK_PLLQ == MHZ(48)
|
||||
#define CLOCK48MHZ_USE_PLLQ 1
|
||||
#elif CONFIG_CLOCK_MSI == MHZ(48)
|
||||
#define CLOCK48MHZ_USE_MSI 1
|
||||
#else
|
||||
#define CLOCK48MHZ_USE_PLLQ 0
|
||||
#define CLOCK48MHZ_USE_MSI 0
|
||||
#endif
|
||||
|
||||
#if IS_ACTIVE(CLOCK48MHZ_USE_PLLQ)
|
||||
#define CLOCK48MHZ_SELECT (RCC_CCIPR1_CLK48MSEL_1)
|
||||
#elif IS_ACTIVE(CLOCK48MHZ_USE_MSI)
|
||||
#define CLOCK48MHZ_SELECT (RCC_CCIPR1_CLK48MSEL_1 | RCC_CCIPR1_CLK48MSEL_0)
|
||||
#else
|
||||
#define CLOCK48MHZ_SELECT (0)
|
||||
#endif
|
||||
|
||||
/* Configure the AHB and APB buses prescalers */
|
||||
#define CLOCK_AHB_DIV (0)
|
||||
|
||||
@ -148,22 +128,17 @@
|
||||
#define CLOCK_APB2_DIV (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_1 | RCC_CFGR2_PPRE2_0)
|
||||
#endif
|
||||
|
||||
/* Only periph_hwrng requires 48MHz for the moment */
|
||||
#if IS_USED(MODULE_PERIPH_HWRNG)
|
||||
#if !IS_ACTIVE(CLOCK48MHZ_USE_PLLQ) && !IS_ACTIVE(CLOCK48MHZ_USE_MSI)
|
||||
#error "No 48MHz clock source available, HWRNG cannot work"
|
||||
#endif
|
||||
#define CLOCK_ENABLE_48MHZ 1
|
||||
/* Only periph_hwrng and periph_usbdev require HSI RC with 48MHz for the moment */
|
||||
#if IS_USED(MODULE_PERIPH_HWRNG) || IS_USED(MODULE_PERIPH_USBDEV_CLK)
|
||||
#define CLOCK_ENABLE_HSI48 1
|
||||
#else
|
||||
#define CLOCK_ENABLE_48MHZ 0
|
||||
#define CLOCK_ENABLE_HSI48 0
|
||||
#endif
|
||||
|
||||
/* Check if PLL is required
|
||||
- When used as system clock
|
||||
- When PLLQ is used as 48MHz clock source
|
||||
*/
|
||||
#if IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || \
|
||||
(IS_ACTIVE(CLOCK_ENABLE_48MHZ) && IS_ACTIVE(CLOCK48MHZ_USE_PLLQ))
|
||||
#if IS_ACTIVE(CONFIG_USE_CLOCK_PLL)
|
||||
#define CLOCK_ENABLE_PLL 1
|
||||
#else
|
||||
#define CLOCK_ENABLE_PLL 0
|
||||
@ -185,7 +160,7 @@
|
||||
#error "HSE is required by the clock configuration but is not provided by the board."
|
||||
#endif
|
||||
|
||||
/* Check if HSI is required:
|
||||
/* Check if HSI RC with 16 MHz is required:
|
||||
- When used as system clock
|
||||
- When used as PLL input clock
|
||||
*/
|
||||
@ -267,7 +242,7 @@ void stmclk_init_sysclk(void)
|
||||
while (!(RCC->CR & RCC_CR_HSERDY)) {}
|
||||
}
|
||||
|
||||
/* Enable the MSI clock only when it's used */
|
||||
/* Enable the MSIS clock only when it's used */
|
||||
if (IS_ACTIVE(CLOCK_ENABLE_MSI)) {
|
||||
RCC->ICSCR1 = RCC_ICSCR1_MSIRGSEL;
|
||||
RCC->ICSCR1 |= CLOCK_MSIRANGE;
|
||||
@ -330,9 +305,14 @@ void stmclk_init_sysclk(void)
|
||||
stmclk_disable_hsi();
|
||||
}
|
||||
|
||||
if (IS_ACTIVE(CLOCK_ENABLE_48MHZ)) {
|
||||
/* configure the clock used for the 48MHz clock tree (USB, RNG) */
|
||||
RCC->CCIPR1 = CLOCK48MHZ_SELECT;
|
||||
if (IS_ACTIVE(CLOCK_ENABLE_HSI48)) {
|
||||
/* enable HSI48 clock for certain peripherals (RNG, OTG_FS, USB and SDMMC) */
|
||||
RCC->CR |= RCC_CR_HSI48ON;
|
||||
while (!(RCC->CR & RCC_CR_HSI48RDY)) {}
|
||||
/* select HSI48 as clock for RNG (reset value) */
|
||||
/* RCC->CCIPR2 &= ~(RCC_CCIPR2_RNGSEL_1 | RCC_CCIPR2_RNGSEL_0); */
|
||||
/* select HSI48 as clock for OTG_FS, USB and SDMMC (reset value) */
|
||||
/* RCC->CCIPR1 &= ~(RCC_CCIPR1_CLK48MSEL_1 | RCC_CCIPR1_CLK48MSEL_0); */
|
||||
}
|
||||
|
||||
irq_restore(is);
|
||||
|
||||
@ -745,11 +745,16 @@ static void _usbdev_init(usbdev_t *dev)
|
||||
pm_block(STM32_PM_STOP);
|
||||
pm_block(STM32_PM_STANDBY);
|
||||
|
||||
#if defined(PWR_CR2_USV) /* on L4 */
|
||||
/* Validate USB Supply */
|
||||
#if defined(PWR_CR2_USV)
|
||||
/* on L4: Validate USB Supply */
|
||||
PWR->CR2 |= PWR_CR2_USV;
|
||||
#endif /* PWR_CR2_USV */
|
||||
|
||||
#if defined(PWR_SVMCR_USV)
|
||||
/* on U5: Validate USB Supply */
|
||||
PWR->SVMCR |= PWR_SVMCR_USV;
|
||||
#endif /* PWR_SVMCR_USV */
|
||||
|
||||
/* Enable the clock to the peripheral */
|
||||
periph_clk_en(conf->ahb, conf->rcc_mask);
|
||||
|
||||
@ -1004,11 +1009,11 @@ static void _usbdev_init(usbdev_t *dev)
|
||||
|
||||
/* Disable Vbus detection and force the pull-up on, GCCFG is STM32 specific */
|
||||
#if defined(STM32_USB_OTG_CID_1x)
|
||||
/* Enable no Vbus sensing */
|
||||
/* set No Vbus Sensing */
|
||||
_global_regs(usbdev->config)->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
|
||||
#elif defined(STM32_USB_OTG_CID_2x)
|
||||
/* Enable no Vbus Detect enable and enable 'Power Down Disable */
|
||||
_global_regs(usbdev->config)->GCCFG |= USB_OTG_GCCFG_VBDEN;
|
||||
/* clear Vbus Detect Enable */
|
||||
_global_regs(usbdev->config)->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
|
||||
/* Force Vbus Detect values and ID detect values to device mode */
|
||||
_global_regs(usbdev->config)->GOTGCTL |= USB_OTG_GOTGCTL_VBVALOVAL |
|
||||
USB_OTG_GOTGCTL_VBVALOEN |
|
||||
|
||||
@ -32,11 +32,16 @@ static int tinyusb_hw_init_dev(const dwc2_usb_otg_fshs_config_t *conf)
|
||||
pm_block(STM32_PM_STOP);
|
||||
pm_block(STM32_PM_STANDBY);
|
||||
|
||||
#if defined(PWR_CR2_USV) /* on L4 */
|
||||
/* Validate USB Supply */
|
||||
#if defined(PWR_CR2_USV)
|
||||
/* on L4: Validate USB Supply */
|
||||
PWR->CR2 |= PWR_CR2_USV;
|
||||
#endif /* PWR_CR2_USV */
|
||||
|
||||
#if defined(PWR_SVMCR_USV)
|
||||
/* on U5: Validate USB Supply */
|
||||
PWR->SVMCR |= PWR_SVMCR_USV;
|
||||
#endif /* PWR_SVMCR_USV */
|
||||
|
||||
/* Enable the clock to the peripheral */
|
||||
periph_clk_en(conf->ahb, conf->rcc_mask);
|
||||
|
||||
@ -53,8 +58,11 @@ static int tinyusb_hw_init_dev(const dwc2_usb_otg_fshs_config_t *conf)
|
||||
(USB_OTG_GlobalTypeDef *)(conf->periph + USB_OTG_GLOBAL_BASE);
|
||||
|
||||
#ifdef USB_OTG_GCCFG_NOVBUSSENS
|
||||
/* Enable no Vbus Detect enable and enable `Power Down Disable` */
|
||||
/* set No Vbus Sensing */
|
||||
global_regs->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
|
||||
#elif USB_OTG_GCCFG_VBDEN
|
||||
/* clear Vbus Detect Enable */
|
||||
global_regs->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
|
||||
#endif
|
||||
|
||||
#ifdef DWC2_USB_OTG_HS_ENABLED
|
||||
|
||||
Loading…
Reference in New Issue
Block a user