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boards/atmega2560: adapted UART configuration
This commit is contained in:
Hauke Petersen
kYc0o
parent
ccf7cde82d
commit
a2ddb1dd7f
@ -1,5 +1,6 @@
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/*
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* Copyright (C) 2014 Freie Universität Berlin, Hinnerk van Bruinehsen
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* Copyright (C) 2014-2016 Freie Universität Berlin
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* 2014 Hinnerk van Bruinehsen
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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@ -14,6 +15,7 @@
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* @brief Peripheral MCU configuration for the Arduino Mega 2560 board
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*
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* @author Hinnerk van Bruinehsen <h.v.bruinehsen@fu-berlin.de>
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*/
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#ifndef PERIPH_CONF_H_
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@ -57,109 +59,26 @@ extern "C" {
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/**
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* @brief UART configuration
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*
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* The UART devices have fixed pin mappings, so all we need to do, is to specify
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* which devices we would like to use and their corresponding RX interrupts. See
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* the reference manual for the fixed pin mapping.
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*
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* @{
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*/
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#define UART_NUMOF (4U)
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#define UART_0_EN 1
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#define UART_1_EN 1
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#define UART_2_EN 1
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#define UART_3_EN 1
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/* UART 0 registers */
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#define UART0_CTRL_STAT_A UCSR0A
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#define UART0_CTRL_STAT_B UCSR0B
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#define UART0_CTRL_STAT_C UCSR0C
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#define UART0_BAUD_RATE_L UBRR0L
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#define UART0_BAUD_RATE_H UBRR0H
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#define UART0_DATA_REGISTER UDR0
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#define UART_0 MEGA_UART0
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#define UART_0_ISR USART0_RX_vect
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/* Flags */
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#define UART0_RX_COMPLETE RXC0
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#define UART0_DATA_EMPTY UDRE0
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#define UART0_RX_EN RXEN0
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#define UART0_TX_EN TXEN0
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#define UART0_RXC_IRQ_EN RXCIE0
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#define UART0_TXC_IRQ_EN TXCIE0
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#define UART0_8BIT_SIZE (1 << UCSZ00) | (1 << UCSZ01)
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#define UART_1 MEGA_UART1
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#define UART_1_ISR USART1_RX_vect
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/* UART0 helper macros */
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#define UART0_RX_TX_EN UART0_CTRL_STAT_B |= (1 << UART0_RX_EN) | (1 << UART0_TX_EN)
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#define UART0_RX_IRQ_EN UART0_CTRL_STAT_B |= (1 << UART0_RXC_IRQ_EN)
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#define UART0_SET_8BIT_SIZE UART0_CTRL_STAT_C |= UART0_8BIT_SIZE
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#define UART0_RECEIVED_DATA (UART0_CTRL_STAT_A & (1 << UART0_RX_COMPLETE))
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#define UART0_DTREG_EMPTY (UART0_CTRL_STAT_A & (1 << UART0_DATA_EMPTY))
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#define UART_2 MEGA_UART2
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#define UART_2_ISR USART2_RX_vect
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/* UART 1 registers */
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#define UART1_CTRL_STAT_A UCSR1A
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#define UART1_CTRL_STAT_B UCSR1B
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#define UART1_CTRL_STAT_C UCSR1C
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#define UART1_BAUD_RATE_L UBRR1L
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#define UART1_BAUD_RATE_H UBRR1H
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#define UART1_DATA_REGISTER UDR1
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/* Flags */
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#define UART1_RX_COMPLETE RXC1
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#define UART1_DATA_EMPTY UDRE1
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#define UART1_RX_EN RXEN1
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#define UART1_TX_EN TXEN1
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#define UART1_RXC_IRQ_EN RXCIE1
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#define UART1_TXC_IRQ_EN TXCIE1
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#define UART1_8BIT_SIZE (1 << UCSZ10) | (1 << UCSZ11)
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/* UART1 helper macros */
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#define UART1_RX_TX_EN UART1_CTRL_STAT_B |= (1 << UART1_RX_EN) | (1 << UART1_TX_EN)
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#define UART1_RX_IRQ_EN UART1_CTRL_STAT_B |= (1 << UART1_RXC_IRQ_EN)
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#define UART1_SET_8BIT_SIZE UART1_CTRL_STAT_C |= UART1_8BIT_SIZE
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#define UART1_RECEIVED_DATA (UART1_CTRL_STAT_A & (1 << UART1_RX_COMPLETE))
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#define UART1_DTREG_EMPTY (UART1_CTRL_STAT_A & (1 << UART1_DATA_EMPTY))
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/* UART 2 registers */
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#define UART2_CTRL_STAT_A UCSR2A
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#define UART2_CTRL_STAT_B UCSR2B
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#define UART2_CTRL_STAT_C UCSR2C
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#define UART2_BAUD_RATE_L UBRR2L
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#define UART2_BAUD_RATE_H UBRR2H
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#define UART2_DATA_REGISTER UDR2
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/* Flags */
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#define UART2_RX_COMPLETE RXC2
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#define UART2_DATA_EMPTY UDRE2
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#define UART2_RX_EN RXEN2
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#define UART2_TX_EN TXEN2
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#define UART2_RXC_IRQ_EN RXCIE2
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#define UART2_TXC_IRQ_EN TXCIE2
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#define UART2_8BIT_SIZE (1 << UCSZ20) | (1 << UCSZ21)
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/* UART2 helper macros */
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#define UART2_RX_TX_EN UART2_CTRL_STAT_B |= (1 << UART2_RX_EN) | (1 << UART2_TX_EN)
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#define UART2_RX_IRQ_EN UART2_CTRL_STAT_B |= (1 << UART2_RXC_IRQ_EN)
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#define UART2_SET_8BIT_SIZE UART2_CTRL_STAT_C |= UART2_8BIT_SIZE
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#define UART2_RECEIVED_DATA (UART2_CTRL_STAT_A & (1 << UART2_RX_COMPLETE))
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#define UART2_DTREG_EMPTY (UART2_CTRL_STAT_A & (1 << UART2_DATA_EMPTY))
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/* UART 2 registers */
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#define UART3_CTRL_STAT_A UCSR3A
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#define UART3_CTRL_STAT_B UCSR3B
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#define UART3_CTRL_STAT_C UCSR3C
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#define UART3_BAUD_RATE_L UBRR3L
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#define UART3_BAUD_RATE_H UBRR3H
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#define UART3_DATA_REGISTER UDR3
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/* Flags */
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#define UART3_RX_COMPLETE RXC3
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#define UART3_DATA_EMPTY UDRE3
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#define UART3_RX_EN RXEN3
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#define UART3_TX_EN TXEN3
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#define UART3_RXC_IRQ_EN RXCIE3
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#define UART3_TXC_IRQ_EN TXCIE3
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#define UART3_8BIT_SIZE (1 << UCSZ30) | (1 << UCSZ31)
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/* UART3 helper macros */
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#define UART3_RX_TX_EN UART3_CTRL_STAT_B |= (1 << UART3_RX_EN) | (1 << UART3_TX_EN)
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#define UART3_RX_IRQ_EN UART3_CTRL_STAT_B |= (1 << UART3_RXC_IRQ_EN)
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#define UART3_SET_8BIT_SIZE UART3_CTRL_STAT_C |= UART3_8BIT_SIZE
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#define UART3_RECEIVED_DATA (UART3_CTRL_STAT_A & (1 << UART3_RX_COMPLETE))
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#define UART3_DTREG_EMPTY (UART3_CTRL_STAT_A & (1 << UART3_DATA_EMPTY))
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#define UART_3 MEGA_UART3
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#define UART_3_ISR USART3_RX_vect
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/** @} */
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/**
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