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[SQUASH] Make PLL_DIV and PLL_MUL behave the same as for the F3 and F4

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This commit is contained in:
DipSwitch 2016-04-05 23:51:55 +02:00
parent edae42281b
commit a259cc42b0
5 changed files with 29 additions and 8 deletions
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4
boards/fox/include/periph_conf.h
View File

@ -33,8 +33,8 @@ extern "C" {
#define CLOCK_CORECLOCK (72000000U) /* targeted core clock frequency */
/* configuration of PLL prescaler and multiply values */
/* CORECLOCK := CLOCK_SOURCE / PLL_DIV * PLL_MUL */
#define CLOCK_PLL_DIV RCC_CFGR_PLLXTPRE_HSE_DIV2
#define CLOCK_PLL_MUL RCC_CFGR_PLLMULL9
#define CLOCK_PLL_DIV (2)
#define CLOCK_PLL_MUL (9)
/* configuration of peripheral bus clock prescalers */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 72MHz */
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 72MHz */

4
boards/iotlab-m3/include/periph_conf.h
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@ -34,8 +34,8 @@ extern "C" {
#define CLOCK_CORECLOCK (72000000U) /* targeted core clock frequency */
/* configuration of PLL prescaler and multiply values */
/* CORECLOCK := CLOCK_SOURCE / PLL_DIV * PLL_MUL */
#define CLOCK_PLL_DIV RCC_CFGR_PLLXTPRE_HSE_DIV2
#define CLOCK_PLL_MUL RCC_CFGR_PLLMULL9
#define CLOCK_PLL_DIV (2)
#define CLOCK_PLL_MUL (9)
/* configuration of peripheral bus clock prescalers */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 72MHz */
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 72MHz */

2
boards/nucleo-f103/include/periph_conf.h
View File

@ -33,7 +33,7 @@ extern "C" {
#define CLOCK_CORECLOCK (72000000U) /* desired core clock frequency */
/* the actual PLL values are automatically generated */
#define CLOCK_PLL_DIV (0)
#define CLOCK_PLL_DIV (1)
#define CLOCK_PLL_MUL (9)
/* AHB, APB1, APB2 dividers */

4
boards/spark-core/include/periph_conf.h
View File

@ -33,8 +33,8 @@
#define CLOCK_CORECLOCK (72000000U) /* targeted core clock frequency */
/* configuration of PLL prescaler and multiply values */
/* CORECLOCK := HSE / PLL_HSE_DIV * PLL_HSE_MUL */
#define CLOCK_PLL_DIV RCC_CFGR_PLLXTPRE_HSE /* not divided */
#define CLOCK_PLL_MUL RCC_CFGR_PLLMULL9
#define CLOCK_PLL_DIV (1)
#define CLOCK_PLL_MUL (9)
/* configuration of peripheral bus clock prescalers */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 72MHz */
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 72MHz */

23
cpu/stm32f1/cpu.c
View File

@ -32,17 +32,38 @@
#elif CLOCK_HSI
#define CLOCK_CR_SOURCE RCC_CR_HSION
#define CLOCK_CR_SOURCE_RDY RCC_CR_HSIRDY
#define CLOCK_PLL_DIVMSK 0
#define CLOCK_PLL_SOURCE 0
#define CLOCK_DISABLE_HSI 0
#if (CLOCK_PLL_DIV != 1)
#error "HSI clock cannot be divided"
#endif
#elif CLOCK_HSE
#define CLOCK_CR_SOURCE RCC_CR_HSEON
#define CLOCK_CR_SOURCE_RDY RCC_CR_HSERDY
#define CLOCK_PLL_SOURCE RCC_CFGR_PLLSRC
#define CLOCK_DISABLE_HSI 1
#if (CLOCK_PLL_DIV == 2)
#define CLOCK_PLL_DIVMSK RCC_CFGR_PLLXTPRE
#elif (CLOCK_PLL_DIV == 1)
#define CLOCK_PLL_DIVMSK 0
#else
#error "HSE divider must be 1 or 2"
#endif
#else
#error "Please provide CLOCK_HSI or CLOCK_HSE in boards/NAME/includes/perhip_cpu.h"
#endif
#if CLOCK_PLL_MUL > 16
#error "PLL multiplier cannot exceed 16 times"
#elif CLOCK_PLL_MUL < 2
#error "PLL multiplier cannot be set to 1 or lower"
#endif
static void clk_init(void);
void cpu_init(void)
@ -91,7 +112,7 @@ static void clk_init(void)
RCC->CFGR |= (uint32_t)CLOCK_APB1_DIV;
/* PLL configuration: PLLCLK = CLOCK_SOURCE / PLL_DIV * PLL_MUL */
RCC->CFGR &= ~((uint32_t)(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
RCC->CFGR |= (uint32_t)(CLOCK_PLL_SOURCE | CLOCK_PLL_DIV | ((CLOCK_PLL_MUL - 2) << 18));
RCC->CFGR |= (uint32_t)(CLOCK_PLL_SOURCE | CLOCK_PLL_DIVMSK | ((CLOCK_PLL_MUL - 2) << 18));
/* Enable PLL */
RCC->CR |= RCC_CR_PLLON;
/* Wait till PLL is ready */