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cpu/sam0_common: flashpage: disable interrupts while writing
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1ee9985577
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a21acf0858
@ -64,7 +64,7 @@ static inline void wait_nvm_is_ready(void)
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#endif
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}
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static void _unlock(void)
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static unsigned _unlock(void)
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{
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/* remove peripheral access lock for the NVMCTRL peripheral */
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#ifdef REG_PAC_WRCTRL
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@ -72,9 +72,11 @@ static void _unlock(void)
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#else
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PAC1->WPCLR.reg = PAC1_WPROT_DEFAULT_VAL;
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#endif
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return irq_disable();
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}
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static void _lock(void)
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static void _lock(unsigned state)
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{
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wait_nvm_is_ready();
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@ -89,6 +91,8 @@ static void _lock(void)
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#ifdef CMCC
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CMCC->MAINT0.bit.INVALL = 1;
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#endif
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irq_restore(state);
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}
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static void _cmd_clear_page_buffer(void)
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@ -225,7 +229,7 @@ static void _write_page(void* dst, const void *data, size_t len, void (*cmd_writ
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/* word align destination address */
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uint32_t *dst32 = (void*)((uintptr_t)dst & ~0x3);
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_unlock();
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unsigned state = _unlock();
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_cmd_clear_page_buffer();
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/* write the first, unaligned bytes */
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@ -252,7 +256,7 @@ static void _write_page(void* dst, const void *data, size_t len, void (*cmd_writ
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}
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cmd_write();
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_lock();
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_lock(state);
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}
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static void _erase_page(void* page, void (*cmd_erase)(void))
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@ -260,7 +264,7 @@ static void _erase_page(void* page, void (*cmd_erase)(void))
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uintptr_t page_addr = (uintptr_t)page;
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/* erase given page (the ADDR register uses 16-bit addresses) */
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_unlock();
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unsigned state = _unlock();
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/* ADDR drives the hardware (16-bit) address to the NVM when a command is executed using CMDEX.
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* 8-bit addresses must be shifted one bit to the right before writing to this register.
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@ -273,7 +277,7 @@ static void _erase_page(void* page, void (*cmd_erase)(void))
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_NVMCTRL->ADDR.reg = page_addr;
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cmd_erase();
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_lock();
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_lock(state);
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}
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static void _write_row(uint8_t *dst, const void *_data, size_t len, size_t chunk_size,
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