mirror of
https://github.com/RIOT-OS/RIOT.git
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boards/sodaq-one: add support for SODAQ ONE
The following features were tested (briefly): * UART (the first) * xtimer is working (it's the same code as in samr21)
This commit is contained in:
Kees Bakker
parent
6a07301862
commit
a10bec6874
3
boards/sodaq-one/Makefile
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3
boards/sodaq-one/Makefile
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@ -0,0 +1,3 @@
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MODULE = board
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include $(RIOTBASE)/Makefile.base
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3
boards/sodaq-one/Makefile.dep
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3
boards/sodaq-one/Makefile.dep
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@ -0,0 +1,3 @@
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ifneq (,$(filter saul_default,$(USEMODULE)))
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USEMODULE += saul_gpio
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endif
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14
boards/sodaq-one/Makefile.features
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14
boards/sodaq-one/Makefile.features
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@ -0,0 +1,14 @@
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# Put defined MCU peripherals here (in alphabetical order)
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FEATURES_PROVIDED += periph_adc
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FEATURES_PROVIDED += periph_gpio
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FEATURES_PROVIDED += periph_i2c
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FEATURES_PROVIDED += periph_rtc
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FEATURES_PROVIDED += periph_rtt
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FEATURES_PROVIDED += periph_spi
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FEATURES_PROVIDED += periph_timer
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FEATURES_PROVIDED += periph_uart
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# The board MPU family (used for grouping by the CI system)
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FEATURES_MCU_GROUP = cortex_m0_2
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-include $(RIOTCPU)/samd21/Makefile.features
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19
boards/sodaq-one/Makefile.include
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19
boards/sodaq-one/Makefile.include
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@ -0,0 +1,19 @@
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# define the cpu used by the SODAQ ONE board
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export CPU = samd21
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export CPU_MODEL = samd21g18a
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#export needed for flash rule
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export PORT_LINUX ?= /dev/ttyACM0
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export PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.usbmodem*)))
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# setup serial terminal
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include $(RIOTMAKE)/tools/serial.inc.mk
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# setup the flash tool used
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# we use BOSSA to flash this board since there's an Arduino bootloader
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# preflashed on it. ROM_OFFSET skips the space taken by such bootloader.
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ROM_OFFSET ?= 0x2000
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include $(RIOTMAKE)/tools/bossa.inc.mk
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# setup the boards dependencies
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include $(RIOTBOARD)/$(BOARD)/Makefile.dep
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43
boards/sodaq-one/board.c
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43
boards/sodaq-one/board.c
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@ -0,0 +1,43 @@
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/*
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* Copyright (C) 2017 Kees Bakker, SODAQ
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_sodaq-one
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* @{
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*
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* @file
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* @brief Board common implementations for the SODAQ ONE board
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*
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* @author Kees Bakker <kees@sodaq.com>
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* @}
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*/
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#include "cpu.h"
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#include "board.h"
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#include "periph/gpio.h"
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void board_init(void)
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{
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/* initialize the on-board LEDs, switch them off to start with */
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LED0_OFF;
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gpio_init(LED0_PIN, GPIO_OUT);
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LED1_OFF;
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gpio_init(LED1_PIN, GPIO_OUT);
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LED2_OFF;
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gpio_init(LED2_PIN, GPIO_OUT);
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/* reset RN2483 (LoRa) */
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LORA_RESET_OFF;
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gpio_init(LORA_RESET_PIN, GPIO_OUT);
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GPS_ENABLE_OFF;
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gpio_init(GPS_ENABLE_PIN, GPIO_OUT);
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/* initialize the CPU */
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cpu_init();
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}
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29
boards/sodaq-one/doc.txt
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29
boards/sodaq-one/doc.txt
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@ -0,0 +1,29 @@
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/**
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* @defgroup boards_sodaq-one SODAQ ONE
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* @ingroup boards
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* @brief Support for the SODAQ ONE board
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*
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* ### General information
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*
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* General information about this board can be found on the
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* [SODAQ support](http://support.sodaq.com/sodaq-one/sodaq-one/) website.
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*
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* ### Flash the board
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*
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* 1. Put the board in bootloader mode by double tapping the reset button.<br/>
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* When the board is in bootloader mode, the user led (blue) oscillates
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* smoothly.
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*
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*
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* 2. Use `BOARD=sodaq-one` with the `make` command.<br/>
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* Example with `hello-world` application:
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* ```
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* make BOARD=sodaq-one -C examples/hello-world flash
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* ```
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*
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* ### Accessing STDIO via UART
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*
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* To access the STDIO of RIOT, a FTDI to USB converter needs to be plugged to
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* the RX/TX pins on the board.
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*
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*/
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119
boards/sodaq-one/include/board.h
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119
boards/sodaq-one/include/board.h
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@ -0,0 +1,119 @@
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/*
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* Copyright (C) 2017 Kees Bakker, SODAQ
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_sodaq-one
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* @{
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*
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* @file
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* @brief Board specific definitions for the SODAQ ONE board
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*
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* @author Kees Bakker <kees@sodaq.com>
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*/
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#ifndef BOARD_H
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#define BOARD_H
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#include "cpu.h"
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#include "periph_conf.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name xtimer configuration
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* @{
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*/
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#define XTIMER_WIDTH (16)
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/** @} */
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/**
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* @name LED pin definitions and handlers
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* @{
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*/
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#define LED0_PIN GPIO_PIN(PA, 15)
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#define LED0_PORT PORT->Group[PA]
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#define LED0_MASK (1 << 15)
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#define LED0_OFF (LED0_PORT.OUTSET.reg = LED0_MASK)
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#define LED0_ON (LED0_PORT.OUTCLR.reg = LED0_MASK)
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#define LED0_TOGGLE (LED0_PORT.OUTTGL.reg = LED0_MASK)
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#define LED1_PIN GPIO_PIN(PB, 10)
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#define LED1_PORT PORT->Group[PB]
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#define LED1_MASK (1 << 10)
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#define LED1_OFF (LED1_PORT.OUTSET.reg = LED1_MASK)
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#define LED1_ON (LED1_PORT.OUTCLR.reg = LED1_MASK)
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#define LED1_TOGGLE (LED1_PORT.OUTTGL.reg = LED1_MASK)
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#define LED2_PIN GPIO_PIN(PB, 11)
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#define LED2_PORT PORT->Group[PB]
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#define LED2_MASK (1 << 11)
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#define LED2_OFF (LED2_PORT.OUTSET.reg = LED2_MASK)
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#define LED2_ON (LED2_PORT.OUTCLR.reg = LED2_MASK)
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#define LED2_TOGGLE (LED2_PORT.OUTTGL.reg = LED2_MASK)
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/** @} */
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/**
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* @name User button
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*/
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#define BTN0_PIN GPIO_PIN(PA, 16)
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#define BTN0_MODE GPIO_IN
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/** @} */
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/**
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* @name GPS Time Pulse
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*/
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#define GPS_TIMEPULSE_PIN GPIO_PIN(PA, 14)
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#define GPS_TIMEPULSE_MODE GPIO_IN
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/** @} */
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/**
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* @name GPS Enable
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* @{
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*/
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#define GPS_ENABLE_PIN GPIO_PIN(PA, 18)
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#define GPS_ENABLE_PORT PORT->Group[PA]
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#define GPS_ENABLE_MASK (1 << 18)
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#define GPS_ENABLE_ON (GPS_ENABLE_PORT.OUTSET.reg = GPS_ENABLE_MASK)
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#define GPS_ENABLE_OFF (GPS_ENABLE_PORT.OUTCLR.reg = GPS_ENABLE_MASK)
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/** @} */
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/**
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* @name LORA Reset
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* @{
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*/
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#define LORA_RESET_PIN GPIO_PIN(PA, 4)
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#define LORA_RESET_PORT PORT->Group[PA]
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#define LORA_RESET_MASK (1 << 4)
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#define LORA_RESET_OFF (LORA_RESET_PORT.OUTSET.reg = LORA_RESET_MASK)
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#define LORA_RESET_ON (LORA_RESET_PORT.OUTCLR.reg = LORA_RESET_MASK)
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#define LORA_RESET_TOGGLE (LORA_RESET_PORT.OUTTGL.reg = LORA_RESET_MASK)
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/** @} */
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/**
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* @brief Initialize board specific hardware, including clock, LEDs and std-IO
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*/
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void board_init(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* BOARD_H */
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/** @} */
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62
boards/sodaq-one/include/gpio_params.h
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62
boards/sodaq-one/include/gpio_params.h
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/*
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* Copyright (C) 2017 Kees Bakker, SODAQ
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_sodaq-one
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* @{
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*
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* @file
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* @brief Board specific configuration of direct mapped GPIOs
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*
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* @author Kees Bakker <kees@sodaq.com>
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*/
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#ifndef GPIO_PARAMS_H
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#define GPIO_PARAMS_H
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#include "board.h"
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#include "saul/periph.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief GPIO pin configuration
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*/
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static const saul_gpio_params_t saul_gpio_params[] =
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{
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{
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.name = "LED Red",
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.pin = LED0_PIN,
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.mode = GPIO_OUT
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},
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{
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.name = "LED Green",
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.pin = LED1_PIN,
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.mode = GPIO_OUT
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},
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{
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.name = "LED Blue",
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.pin = LED2_PIN,
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.mode = GPIO_OUT
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},
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{
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.name = "Button",
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.pin = BTN0_PIN,
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.mode = BTN0_MODE,
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.flags = SAUL_GPIO_INVERTED
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},
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /* GPIO_PARAMS_H */
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/** @} */
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243
boards/sodaq-one/include/periph_conf.h
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243
boards/sodaq-one/include/periph_conf.h
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/*
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* Copyright (C) 2017 Kees Bakker, SODAQ
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_sodaq-one
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* @{
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*
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* @file
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* @brief Configuration of CPU peripherals for the SODAQ ONE board
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*
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* @author Kees Bakker <kees@sodaq.com>
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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#include <stdint.h>
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#include "cpu.h"
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name External oscillator and clock configuration
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*
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* For selection of the used CORECLOCK, we have implemented two choices:
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*
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* - usage of the PLL fed by the internal 8MHz oscillator divided by 8
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* - usage of the internal 8MHz oscillator directly, divided by N if needed
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*
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*
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* The PLL option allows for the usage of a wider frequency range and a more
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* stable clock with less jitter. This is why we use this option as default.
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*
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* The target frequency is computed from the PLL multiplier and the PLL divisor.
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* Use the following formula to compute your values:
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*
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* CORECLOCK = ((PLL_MUL + 1) * 1MHz) / PLL_DIV
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*
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* NOTE: The PLL circuit does not run with less than 32MHz while the maximum PLL
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* frequency is 96MHz. So PLL_MULL must be between 31 and 95!
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*
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*
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* The internal Oscillator used directly can lead to a slightly better power
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* efficiency to the cost of a less stable clock. Use this option when you know
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* what you are doing! The actual core frequency is adjusted as follows:
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*
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* CORECLOCK = 8MHz / DIV
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*
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* NOTE: A core clock frequency below 1MHz is not recommended
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*
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* @{
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*/
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#define CLOCK_USE_PLL (1)
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#if CLOCK_USE_PLL
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/* edit these values to adjust the PLL output frequency */
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#define CLOCK_PLL_MUL (47U) /* must be >= 31 & <= 95 */
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#define CLOCK_PLL_DIV (1U) /* adjust to your needs */
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/* generate the actual used core clock frequency */
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#define CLOCK_CORECLOCK (((CLOCK_PLL_MUL + 1) * 1000000U) / CLOCK_PLL_DIV)
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#else
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/* edit this value to your needs */
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#define CLOCK_DIV (1U)
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/* generate the actual core clock frequency */
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#define CLOCK_CORECLOCK (8000000 / CLOCK_DIV)
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#endif
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/** @} */
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/**
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* @name Timer peripheral configuration
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* @{
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*/
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#define TIMER_NUMOF (2U)
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#define TIMER_0_EN 1
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#define TIMER_1_EN 1
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/* Timer 0 configuration */
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#define TIMER_0_DEV TC3->COUNT16
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#define TIMER_0_CHANNELS 2
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#define TIMER_0_MAX_VALUE (0xffff)
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#define TIMER_0_ISR isr_tc3
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/* Timer 1 configuration */
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#define TIMER_1_DEV TC4->COUNT32
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#define TIMER_1_CHANNELS 2
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#define TIMER_1_MAX_VALUE (0xffffffff)
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#define TIMER_1_ISR isr_tc4
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/** @} */
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/**
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* @name UART configuration
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* @{
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* See Table 6.1 of the SAM D21 Datasheet
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*/
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static const uart_conf_t uart_config[] = {
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{
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.dev = &SERCOM5->USART,
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.rx_pin = GPIO_PIN(PB,3), /* D0, RX Pin */
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.tx_pin = GPIO_PIN(PB,2), /* D1, TX Pin */
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.mux = GPIO_MUX_D,
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.rx_pad = UART_PAD_RX_1,
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.tx_pad = UART_PAD_TX_0,
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.flags = UART_FLAG_NONE,
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.gclk_src = GCLK_CLKCTRL_GEN_GCLK0
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},
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{
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.dev = &SERCOM2->USART,
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.rx_pin = GPIO_PIN(PA,13),
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.tx_pin = GPIO_PIN(PA,12),
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.mux = GPIO_MUX_C,
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.rx_pad = UART_PAD_RX_1,
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.tx_pad = UART_PAD_TX_0,
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.flags = UART_FLAG_NONE,
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.gclk_src = GCLK_CLKCTRL_GEN_GCLK0
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},
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};
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/* interrupt function name mapping */
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#define UART_0_ISR isr_sercom5
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#define UART_1_ISR isr_sercom2
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#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
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/** @} */
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/**
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* @name ADC configuration
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* @{
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*/
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#define ADC_0_EN 1
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#define ADC_MAX_CHANNELS 17
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/* ADC 0 device configuration */
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#define ADC_0_DEV ADC
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#define ADC_0_IRQ ADC_IRQn
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/* ADC 0 Default values */
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#define ADC_0_CLK_SOURCE 0 /* GCLK_GENERATOR_0 */
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#define ADC_0_PRESCALER ADC_CTRLB_PRESCALER_DIV512
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#define ADC_0_NEG_INPUT ADC_INPUTCTRL_MUXNEG_GND
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#define ADC_0_GAIN_FACTOR_DEFAULT ADC_INPUTCTRL_GAIN_1X
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#define ADC_0_REF_DEFAULT ADC_REFCTRL_REFSEL_INT1V
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static const adc_conf_chan_t adc_channels[] = {
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/* port, pin, muxpos */
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{GPIO_PIN(PA, 2), ADC_INPUTCTRL_MUXPOS_PIN0}, /* A0 */
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{GPIO_PIN(PA, 3), ADC_INPUTCTRL_MUXPOS_PIN1}, /* A1 */
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{GPIO_PIN(PB, 8), ADC_INPUTCTRL_MUXPOS_PIN2}, /* A2 */
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{GPIO_PIN(PB, 9), ADC_INPUTCTRL_MUXPOS_PIN3}, /* A3 */
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{GPIO_PIN(PA, 6), ADC_INPUTCTRL_MUXPOS_PIN6}, /* A4 */
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{GPIO_PIN(PA, 7), ADC_INPUTCTRL_MUXPOS_PIN7}, /* A5 */
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{GPIO_PIN(PA, 8), ADC_INPUTCTRL_MUXPOS_PIN16}, /* A6 */
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{GPIO_PIN(PA, 9), ADC_INPUTCTRL_MUXPOS_PIN17}, /* A7 */
|
||||
{GPIO_PIN(PA,10), ADC_INPUTCTRL_MUXPOS_PIN18}, /* A8 */
|
||||
{GPIO_PIN(PA,11), ADC_INPUTCTRL_MUXPOS_PIN19}, /* A9 */
|
||||
{GPIO_PIN(PB, 2), ADC_INPUTCTRL_MUXPOS_PIN10}, /* A10 */
|
||||
{GPIO_PIN(PB, 3), ADC_INPUTCTRL_MUXPOS_PIN11}, /* A11 */
|
||||
|
||||
{GPIO_PIN(PA, 2), ADC_INPUTCTRL_MUXPOS_PIN0}, /* DAC/VOUT */
|
||||
{GPIO_PIN(PA, 3), ADC_INPUTCTRL_MUXPOS_PIN1}, /* AREF */
|
||||
{GPIO_PIN(PA, 5), ADC_INPUTCTRL_MUXPOS_PIN5}, /* BAT_VOLT */
|
||||
};
|
||||
|
||||
#define ADC_0_CHANNELS (12)
|
||||
#define ADC_NUMOF ADC_0_CHANNELS
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name SPI configuration
|
||||
* @{
|
||||
*/
|
||||
static const spi_conf_t spi_config[] = {
|
||||
{
|
||||
.dev = &SERCOM0->SPI,
|
||||
.miso_pin = GPIO_PIN(PA, 8),
|
||||
.mosi_pin = GPIO_PIN(PA, 10),
|
||||
.clk_pin = GPIO_PIN(PA, 11),
|
||||
.miso_mux = GPIO_MUX_C,
|
||||
.mosi_mux = GPIO_MUX_C,
|
||||
.clk_mux = GPIO_MUX_C,
|
||||
.miso_pad = SPI_PAD_MISO_0,
|
||||
.mosi_pad = SPI_PAD_MOSI_2_SCK_3
|
||||
}
|
||||
};
|
||||
|
||||
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name I2C configuration
|
||||
* @{
|
||||
*/
|
||||
static const i2c_conf_t i2c_config[] = {
|
||||
{
|
||||
.dev = &(SERCOM3->I2CM),
|
||||
.speed = I2C_SPEED_NORMAL,
|
||||
.scl_pin = GPIO_PIN(PA, 23),
|
||||
.sda_pin = GPIO_PIN(PA, 22),
|
||||
.mux = GPIO_MUX_C,
|
||||
.gclk_src = GCLK_CLKCTRL_GEN_GCLK0,
|
||||
.flags = I2C_FLAG_NONE
|
||||
}
|
||||
};
|
||||
#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0]))
|
||||
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name RTC configuration
|
||||
* @{
|
||||
*/
|
||||
#define RTC_NUMOF (1U)
|
||||
#define RTC_DEV RTC->MODE2
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name RTT configuration
|
||||
* @{
|
||||
*/
|
||||
#define RTT_NUMOF (1U)
|
||||
#define RTT_DEV RTC->MODE0
|
||||
#define RTT_IRQ RTC_IRQn
|
||||
#define RTT_IRQ_PRIO 10
|
||||
#define RTT_ISR isr_rtc
|
||||
#define RTT_MAX_VALUE (0xffffffff)
|
||||
#define RTT_FREQUENCY (32768U) /* in Hz. For changes see `rtt.c` */
|
||||
#define RTT_RUNSTDBY (1) /* Keep RTT running in sleep states */
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PERIPH_CONF_H */
|
||||
/** @} */
|
||||
Loading…
Reference in New Issue
Block a user