diff --git a/cpu/lpc2387/include/vendor/lpc23xx.h b/cpu/lpc2387/include/vendor/lpc23xx.h index 63f2e8c7d9..60dc70e1f6 100644 --- a/cpu/lpc2387/include/vendor/lpc23xx.h +++ b/cpu/lpc2387/include/vendor/lpc23xx.h @@ -809,8 +809,25 @@ typedef struct { #define S0SPCCR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x0C)) #define S0SPINT (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x1C)) +/** + * @brief Generic SPI register map + */ +typedef struct { + REG32 CR0; /**< Control Register 0 */ + REG32 CR1; /**< Control Register 1 */ + REG32 DR; /**< Data Register */ + REG32 SR; /**< Status Register */ + REG32 CPSR; /**< Clock Prescale Register */ + REG32 IMSC; /**< Interrupt Mask Set/Clear Register */ + REG32 RIS; /**< Raw Interrupt Status Register */ + REG32 MIS; /**< Masked Interrupt Status Register */ + REG32 ICR; /**< Interrupt Clear Register */ + REG32 DMACR; /**< DMA Control Register */ +} lpc23xx_spi_t; + /* SSP0 Controller */ #define SSP0_BASE_ADDR 0xE0068000 +#define SPI0 ((lpc23xx_spi_t *)SSP0_BASE_ADDR) #define SSP0CR0 (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x00)) #define SSP0CR1 (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x04)) #define SSP0DR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x08)) @@ -824,6 +841,7 @@ typedef struct { /* SSP1 Controller */ #define SSP1_BASE_ADDR 0xE0030000 +#define SPI1 ((lpc23xx_spi_t *)SSP1_BASE_ADDR) #define SSP1CR0 (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x00)) #define SSP1CR1 (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x04)) #define SSP1DR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x08)) diff --git a/cpu/lpc2387/periph/spi.c b/cpu/lpc2387/periph/spi.c index 3fe63bd95d..20c9722839 100644 --- a/cpu/lpc2387/periph/spi.c +++ b/cpu/lpc2387/periph/spi.c @@ -34,9 +34,9 @@ #define ENABLE_DEBUG (0) #include "debug.h" -#define SPI_TX_EMPTY (SSP0SR & SSPSR_TFE) -#define SPI_BUSY (SSP0SR & SSPSR_BSY) -#define SPI_RX_AVAIL (SSP0SR & SSPSR_RNE) +#define SPI_TX_EMPTY (SPI0->SR & SSPSR_TFE) +#define SPI_BUSY (SPI0->SR & SSPSR_BSY) +#define SPI_RX_AVAIL (SPI0->SR & SSPSR_RNE) /** * @brief Array holding one pre-initialized mutex for each SPI device @@ -80,21 +80,21 @@ int spi_acquire(spi_t bus, spi_cs_t cs, spi_mode_t mode, spi_clk_t clk) /* power on */ PCONP |= (PCSSP0); /* interface setup */ - SSP0CR0 = 7; + SPI0->CR0 = 7; /* configure bus clock */ lpc2387_pclk_scale(CLOCK_CORECLOCK / 1000, (uint32_t)clk, &pclksel, &cpsr); PCLKSEL1 &= ~(BIT10 | BIT11); /* CCLK to PCLK divider*/ PCLKSEL1 |= pclksel << 10; - SSP0CPSR = cpsr; + SPI0->CPSR = cpsr; /* enable the bus */ - SSP0CR1 |= BIT1; + SPI0->CR1 |= BIT1; /* clear RxFIFO */ int dummy; while (SPI_RX_AVAIL) { /* while RNE (Receive FIFO Not Empty)...*/ - dummy = SSP0DR; /* read data*/ + dummy = SPI0->DR; /* read data*/ } (void) dummy; /* to suppress unused-but-set-variable */ @@ -105,7 +105,7 @@ void spi_release(spi_t bus) { (void) bus; /* disable, power off, and release the bus */ - SSP0CR1 &= ~(BIT1); + SPI0->CR1 &= ~(BIT1); PCONP &= ~(PCSSP0); mutex_unlock(&lock); } @@ -127,10 +127,10 @@ void spi_transfer_bytes(spi_t bus, spi_cs_t cs, bool cont, for (size_t i = 0; i < len; i++) { uint8_t tmp = (out_buf) ? out_buf[i] : 0; while (!SPI_TX_EMPTY) {} - SSP0DR = tmp; + SPI0->DR = tmp; while (SPI_BUSY) {} while (!SPI_RX_AVAIL) {} - tmp = (uint8_t)SSP0DR; + tmp = (uint8_t)SPI0->DR; if (in_buf) { in_buf[i] = tmp; }