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cpu/kinetis: Refactor LPTMR driver implementation
Uses timer freerunning counter mode (TFC) and updating an internal reference point instead of relying on RTT for reference time. The target accuracy has been greatly improved for all test cases in bench_periph_timer
This commit is contained in:
Joakim Nohlgård
parent
3d2d3be267
commit
9e10cd4401
@ -1,8 +1,3 @@
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ifneq (,$(filter periph_rtc,$(USEMODULE)))
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USEMODULE += periph_rtt
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endif
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ifneq (,$(filter periph_timer,$(USEMODULE)))
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# RTT is used as the time base for the LPTMR driver.
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# TODO: Remove when LPTMR is refactored.
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FEATURES_OPTIONAL += periph_rtt
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endif
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@ -293,6 +293,10 @@ typedef struct {
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typedef struct {
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/** LPTMR device base pointer */
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LPTMR_Type *dev;
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/** Input clock frequency */
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uint32_t base_freq;
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/** Clock source setting */
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uint8_t src;
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/** IRQn interrupt number */
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uint8_t irqn;
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} lptmr_conf_t;
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@ -52,28 +52,12 @@
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#error TIMER_NUMOF should be the total of PIT and LPTMR timers in the system
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#endif
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/*
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* The RTC prescaler will normally count to 32767 every second unless configured
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* otherwise through the time compensation register.
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*/
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#define TIMER_RTC_SUBTICK_MAX (0x7fff)
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/*
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* Number of bits in the ideal RTC prescaler counter
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*/
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#define TIMER_RTC_SUBTICK_BITS (15)
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/**
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* @brief The number of ticks that will be lost when setting a new target in the LPTMR
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*
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* The counter will otherwise drop ticks when setting new timeouts.
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*/
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#define LPTMR_RELOAD_OVERHEAD 2
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/**
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* @brief Base clock frequency of the LPTMR module
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*/
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/* The LPTMR implementation is hard-coded to use ER32KCLK */
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#define LPTMR_BASE_FREQ (32768ul)
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#define LPTMR_RELOAD_OVERHEAD 1
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/* PIT channel state */
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typedef struct {
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@ -86,11 +70,9 @@ typedef struct {
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/* LPTMR state */
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typedef struct {
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timer_isr_ctx_t isr_ctx;
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uint32_t csr;
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uint32_t cnr;
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uint32_t cmr;
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uint32_t running;
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uint16_t reference;
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uint16_t rtt_offset;
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} lptmr_t;
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static const pit_conf_t pit_config[PIT_NUMOF] = PIT_CONFIG;
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@ -350,35 +332,6 @@ static inline void lptmr_start(uint8_t dev);
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static inline void lptmr_stop(uint8_t dev);
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static inline void lptmr_irq_handler(tim_t tim);
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/**
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* @brief Read the prescaler register from the RTC as a reliable 47 bit time counter
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*/
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static inline uint32_t _rtt_get_subtick(void)
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{
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uint32_t tpr;
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uint32_t tsr;
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for (int i = 0; i < 5; i++) {
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/* Read twice to make sure we get a stable reading */
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tpr = RTC->TPR & RTC_TPR_TPR_MASK;
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tsr = RTC->TSR & RTC_TSR_TSR_MASK;
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if ((tsr == (RTC->TSR & RTC_TSR_TSR_MASK)) &&
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(tpr == (RTC->TPR & RTC_TPR_TPR_MASK))) {
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break;
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}
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}
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if (tpr > TIMER_RTC_SUBTICK_MAX) {
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/* This only happens if the RTC time compensation value has been
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* modified to compensate for RTC drift. See Kinetis ref.manual,
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* RTC Time Compensation Register (RTC_TCR).
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*/
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tpr = TIMER_RTC_SUBTICK_MAX;
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}
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return (tsr << TIMER_RTC_SUBTICK_BITS) | tpr;
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}
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static inline void _lptmr_set_cb_config(uint8_t dev, timer_cb_t cb, void *arg)
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{
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/* set callback function */
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@ -389,60 +342,32 @@ static inline void _lptmr_set_cb_config(uint8_t dev, timer_cb_t cb, void *arg)
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/**
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* @brief Compute the LPTMR prescaler setting, see reference manual for details
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*/
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static inline int32_t _lptmr_compute_prescaler(uint32_t freq) {
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static inline int32_t _lptmr_compute_prescaler(uint8_t dev, uint32_t freq) {
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uint32_t prescale = 0;
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if ((freq > LPTMR_BASE_FREQ) || (freq == 0)) {
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if ((freq > lptmr_config[dev].base_freq) || (freq == 0)) {
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/* Frequency out of range */
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return -1;
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}
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while (freq < LPTMR_BASE_FREQ){
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while (freq < lptmr_config[dev].base_freq){
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++prescale;
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freq <<= 1;
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}
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if (freq != LPTMR_BASE_FREQ) {
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/* freq was not a power of two division of LPTMR_BASE_FREQ */
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if (freq != lptmr_config[dev].base_freq) {
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/* freq was not a power of two division of base_freq */
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return -2;
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}
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if (prescale > 0) {
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/* LPTMR_PSR_PRESCALE == 0 yields LPTMR_BASE_FREQ/2,
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* LPTMR_PSR_PRESCALE == 1 yields LPTMR_BASE_FREQ/4 etc.. */
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return LPTMR_PSR_PRESCALE(prescale - 1);
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}
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else {
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if (prescale == 0) {
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/* Prescaler bypass enabled */
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return LPTMR_PSR_PBYP_MASK;
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}
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}
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/**
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* @brief Update the offset between RTT and LPTMR
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*/
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static inline void _lptmr_update_rtt_offset(uint8_t dev)
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{
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lptmr[dev].rtt_offset = _rtt_get_subtick();
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}
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/**
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* @brief Update the reference time point (CNR=0)
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*/
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static inline void _lptmr_update_reference(uint8_t dev)
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{
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lptmr[dev].reference = _rtt_get_subtick() + LPTMR_RELOAD_OVERHEAD - lptmr[dev].rtt_offset;
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}
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static inline void _lptmr_set_counter(uint8_t dev)
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{
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_lptmr_update_reference(dev);
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LPTMR_Type *hw = lptmr_config[dev].dev;
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hw->CSR = 0;
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hw->CMR = lptmr[dev].cmr;
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/* restore saved state */
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hw->CSR = lptmr[dev].csr;
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/* LPTMR_PSR_PRESCALE == 0 yields base_freq / 2,
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* LPTMR_PSR_PRESCALE == 1 yields base_freq / 4 etc.. */
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return LPTMR_PSR_PRESCALE(prescale - 1);
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}
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static inline int lptmr_init(uint8_t dev, uint32_t freq, timer_cb_t cb, void *arg)
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{
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int32_t prescale = _lptmr_compute_prescaler(freq);
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int32_t prescale = _lptmr_compute_prescaler(dev, freq);
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if (prescale < 0) {
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return -1;
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}
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@ -452,13 +377,13 @@ static inline int lptmr_init(uint8_t dev, uint32_t freq, timer_cb_t cb, void *ar
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/* Turn on module clock */
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LPTMR_CLKEN();
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/* Completely disable the module before messing with the settings */
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hw->CSR = 0;
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/* select ERCLK32K as clock source for LPTMR */
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hw->PSR = LPTMR_PSR_PCS(2) | ((uint32_t)prescale);
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/* Clear IRQ flag in case it was already set */
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hw->CSR = LPTMR_CSR_TCF_MASK;
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/* select clock source and configure prescaler */
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hw->PSR = LPTMR_PSR_PCS(lptmr_config[dev].src) | ((uint32_t)prescale);
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/* Enable IRQs on the counting channel */
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NVIC_ClearPendingIRQ(lptmr_config[dev].irqn);
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NVIC_EnableIRQ(lptmr_config[dev].irqn);
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@ -466,9 +391,11 @@ static inline int lptmr_init(uint8_t dev, uint32_t freq, timer_cb_t cb, void *ar
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_lptmr_set_cb_config(dev, cb, arg);
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/* Reset state */
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_lptmr_update_rtt_offset(dev);
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lptmr[dev].running = 1;
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lptmr_clear(dev);
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lptmr[dev].cnr = 0;
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lptmr[dev].cmr = 0;
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hw->CMR = 0;
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hw->CSR = LPTMR_CSR_TEN_MASK | LPTMR_CSR_TFC_MASK;
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irq_restore(mask);
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@ -480,86 +407,188 @@ static inline uint16_t lptmr_read(uint8_t dev)
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LPTMR_Type *hw = lptmr_config[dev].dev;
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/* latch the current timer value into CNR */
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hw->CNR = 0;
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return lptmr[dev].reference + hw->CNR;
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return lptmr[dev].cnr + hw->CNR;
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}
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/**
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* @brief Reload the timer with the given timeout, or spin if timeout is too small
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*
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* @pre IRQs masked, timer running
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*/
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static inline void lptmr_reload_or_spin(uint8_t dev, uint16_t timeout)
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{
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LPTMR_Type *hw = lptmr_config[dev].dev;
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/* Disable timer and set target, 1 to 2 ticks will be dropped by the
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* hardware during the disable-enable cycle */
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/* Disable the timer interrupt first */
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hw->CSR = LPTMR_CSR_TEN_MASK | LPTMR_CSR_TFC_MASK;
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if (timeout <= LPTMR_RELOAD_OVERHEAD) {
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/* we spin if the timeout is too short to reload the timer */
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hw->CNR = 0;
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uint16_t cnr_begin = hw->CNR;
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while ((hw->CNR - cnr_begin) <= timeout) {
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hw->CNR = 0;
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}
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/* Emulate IRQ handler behaviour */
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lptmr[dev].running = 0;
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if (lptmr[dev].isr_ctx.cb != NULL) {
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lptmr[dev].isr_ctx.cb(lptmr[dev].isr_ctx.arg, 0);
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}
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thread_yield_higher();
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return;
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}
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/* Update reference */
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hw->CNR = 0;
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lptmr[dev].cnr += hw->CNR + LPTMR_RELOAD_OVERHEAD;
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/* Disable timer */
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hw->CSR = 0;
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hw->CMR = timeout - LPTMR_RELOAD_OVERHEAD;
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/* Enable timer and IRQ */
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hw->CSR = LPTMR_CSR_TEN_MASK | LPTMR_CSR_TFC_MASK | LPTMR_CSR_TIE_MASK;
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}
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static inline int lptmr_set(uint8_t dev, uint16_t timeout)
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{
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LPTMR_Type *hw = lptmr_config[dev].dev;
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/* Disable IRQs to minimize jitter */
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unsigned int mask = irq_disable();
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lptmr[dev].cmr = timeout;
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/* Enable interrupt, enable timer */
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lptmr[dev].csr = LPTMR_CSR_TEN_MASK | LPTMR_CSR_TIE_MASK;
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if (lptmr[dev].running != 0) {
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/* Timer is currently running */
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/* Set new target */
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_lptmr_set_counter(dev);
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lptmr[dev].running = 1;
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if (!(hw->CSR & LPTMR_CSR_TEN_MASK)) {
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/* Timer is stopped, only update target */
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if (timeout > LPTMR_RELOAD_OVERHEAD) {
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/* Compensate for the reload delay */
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lptmr[dev].cmr = timeout - LPTMR_RELOAD_OVERHEAD;
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}
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else {
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lptmr[dev].cmr = 0;
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}
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}
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else if (hw->CSR & LPTMR_CSR_TCF_MASK) {
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/* TCF is set, safe to update CMR live */
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hw->CNR = 0;
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hw->CMR = timeout + hw->CNR;
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/* cppcheck-suppress selfAssignment
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* Clear IRQ flags */
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hw->CSR = hw->CSR;
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/* Enable timer and IRQ */
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hw->CSR = LPTMR_CSR_TEN_MASK | LPTMR_CSR_TFC_MASK | LPTMR_CSR_TIE_MASK;
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}
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else {
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lptmr_reload_or_spin(dev, timeout);
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}
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irq_restore(mask);
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return 0;
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return 1;
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}
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static inline int lptmr_set_absolute(uint8_t dev, uint16_t target)
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{
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LPTMR_Type *hw = lptmr_config[dev].dev;
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/* Disable IRQs to minimize jitter */
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unsigned int mask = irq_disable();
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uint16_t offset = target - lptmr[dev].reference;
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lptmr[dev].cmr = offset;
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/* Enable interrupt, enable timer */
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lptmr[dev].csr = LPTMR_CSR_TEN_MASK | LPTMR_CSR_TIE_MASK;
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if (lptmr[dev].running != 0) {
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/* Timer is currently running */
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/* Set new target */
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_lptmr_set_counter(dev);
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lptmr[dev].running = 1;
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if (!(hw->CSR & LPTMR_CSR_TEN_MASK)) {
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/* Timer is stopped, only update target */
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uint16_t timeout = target - lptmr[dev].cnr;
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if (timeout > LPTMR_RELOAD_OVERHEAD) {
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/* Compensate for the reload delay */
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lptmr[dev].cmr = timeout - LPTMR_RELOAD_OVERHEAD;
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}
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else {
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lptmr[dev].cmr = 0;
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}
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}
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else if (hw->CSR & LPTMR_CSR_TCF_MASK) {
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/* TCF is set, safe to update CMR live */
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hw->CMR = target - lptmr[dev].cnr;
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/* cppcheck-suppress selfAssignment
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* Clear IRQ flags */
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hw->CSR = hw->CSR;
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/* Enable timer and IRQ */
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hw->CSR = LPTMR_CSR_TEN_MASK | LPTMR_CSR_TFC_MASK | LPTMR_CSR_TIE_MASK;
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}
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else {
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uint16_t timeout = target - lptmr_read(dev);
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lptmr_reload_or_spin(dev, timeout);
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}
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irq_restore(mask);
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return 0;
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return 1;
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}
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static inline int lptmr_clear(uint8_t dev)
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{
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/* Disable IRQs to minimize jitter */
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LPTMR_Type *hw = lptmr_config[dev].dev;
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unsigned int mask = irq_disable();
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lptmr[dev].cmr = LPTMR_MAX_VALUE;
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/* Disable interrupt, enable timer */
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lptmr[dev].csr = LPTMR_CSR_TEN_MASK;
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if (lptmr[dev].running != 0) {
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/* Timer is currently running */
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/* Set new target */
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_lptmr_set_counter(dev);
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if (!lptmr[dev].running) {
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/* Already clear */
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irq_restore(mask);
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return 1;
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}
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lptmr[dev].running = 0;
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if (!(hw->CSR & LPTMR_CSR_TEN_MASK)) {
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/* Timer is stopped */
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irq_restore(mask);
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return 1;
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}
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/* Disable interrupt, enable timer */
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hw->CSR = LPTMR_CSR_TEN_MASK | LPTMR_CSR_TFC_MASK;
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/* Clear IRQ if it occurred during this function */
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NVIC_ClearPendingIRQ(lptmr_config[dev].irqn);
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irq_restore(mask);
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return 0;
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return 1;
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}
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static inline void lptmr_start(uint8_t dev)
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{
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if (lptmr[dev].running != 0) {
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/* Timer already running */
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return;
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}
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lptmr[dev].running = 1;
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_lptmr_set_counter(dev);
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}
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static inline void lptmr_stop(uint8_t dev)
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{
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if (lptmr[dev].running == 0) {
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/* Timer already stopped */
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LPTMR_Type *hw = lptmr_config[dev].dev;
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if (hw->CSR & LPTMR_CSR_TEN_MASK) {
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/* Timer is running */
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return;
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}
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/* Disable IRQs to avoid race with ISR */
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unsigned int mask = irq_disable();
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lptmr[dev].running = 0;
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/* ensure hardware is reset */
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hw->CSR = 0;
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if (lptmr[dev].running) {
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/* set target */
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hw->CMR = lptmr[dev].cmr;
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/* enable interrupt and start timer */
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hw->CSR = LPTMR_CSR_TEN_MASK | LPTMR_CSR_TFC_MASK | LPTMR_CSR_TIE_MASK;
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}
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else {
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/* no target */
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hw->CMR = 0;
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/* Disable interrupt, enable timer */
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hw->CSR = LPTMR_CSR_TEN_MASK | LPTMR_CSR_TFC_MASK;
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}
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/* compensate for the reload delay when starting the timer */
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lptmr[dev].cnr += LPTMR_RELOAD_OVERHEAD;
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irq_restore(mask);
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}
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static inline void lptmr_stop(uint8_t dev)
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{
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/* Disable IRQs to avoid race with ISR */
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unsigned int mask = irq_disable();
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LPTMR_Type *hw = lptmr_config[dev].dev;
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/* latch the current timer value into CNR */
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hw->CNR = 12345;
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uint16_t cnr = hw->CNR;
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lptmr[dev].cmr = hw->CMR - cnr;
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lptmr[dev].csr = hw->CSR;
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_lptmr_update_reference(dev);
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/* Disable counter and clear interrupt flag */
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hw->CSR = LPTMR_CSR_TCF_MASK;
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if (!(hw->CSR & LPTMR_CSR_TEN_MASK)) {
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/* Timer is already stopped */
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return;
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}
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/* Update state */
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/* Latch counter value */
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hw->CNR = 0;
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lptmr[dev].cnr += hw->CNR;
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uint16_t timeout = hw->CMR - hw->CNR;
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/* Disable timer */
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hw->CSR = 0;
|
||||
if (timeout > LPTMR_RELOAD_OVERHEAD) {
|
||||
/* Compensate for the delay in reloading */
|
||||
lptmr[dev].cmr = timeout - LPTMR_RELOAD_OVERHEAD;
|
||||
}
|
||||
else {
|
||||
lptmr[dev].cmr = timeout;
|
||||
}
|
||||
/* Clear any pending IRQ */
|
||||
NVIC_ClearPendingIRQ(lptmr_config[dev].irqn);
|
||||
irq_restore(mask);
|
||||
@ -569,17 +598,17 @@ static inline void lptmr_irq_handler(tim_t tim)
|
||||
{
|
||||
uint8_t dev = _lptmr_index(tim);
|
||||
LPTMR_Type *hw = lptmr_config[dev].dev;
|
||||
lptmr_t *lptmr_ctx = &lptmr[dev];
|
||||
lptmr_ctx->cmr = LPTMR_MAX_VALUE;
|
||||
_lptmr_set_counter(dev);
|
||||
|
||||
if (lptmr_ctx->isr_ctx.cb != NULL) {
|
||||
lptmr_ctx->isr_ctx.cb(lptmr_ctx->isr_ctx.arg, 0);
|
||||
lptmr[dev].running = 0;
|
||||
/* Disable interrupt generation, keep timer running */
|
||||
/* Do not clear TCF flag here, it is required for writing CMR without
|
||||
* disabling timer first */
|
||||
hw->CSR = LPTMR_CSR_TEN_MASK | LPTMR_CSR_TFC_MASK;
|
||||
|
||||
if (lptmr[dev].isr_ctx.cb != NULL) {
|
||||
lptmr[dev].isr_ctx.cb(lptmr[dev].isr_ctx.arg, 0);
|
||||
}
|
||||
|
||||
/* Clear interrupt flag */
|
||||
bit_set32(&hw->CSR, LPTMR_CSR_TCF_SHIFT);
|
||||
|
||||
cortexm_isr_end();
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user