RIOT-OS/RIOT
RIOT-OS/RIOT
1
0
Fork 0
mirror of https://github.com/RIOT-OS/RIOT.git synced 2024-12-29 04:50:03 +01:00
Code Releases Activity

cpu/sam0/periph: remove bitfield usage in DMAC driver

Browse Source 
Signed-off-by: Dylan Laduranty <dylan.laduranty@mesotic.com>
This commit is contained in:
Dylan Laduranty 2024-06-06 22:39:01 +02:00
parent 292111a244
commit 9d298137d6
1 changed files with 7 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
cpu/sam0_common/periph/dma.c
View File

@ -90,7 +90,7 @@ void dma_init(void)
NVIC_EnableIRQ(DMAC_IRQn);
#endif
DMAC->CTRL.bit.DMAENABLE = 1;
DMAC->CTRL.reg |= DMAC_CTRL_DMAENABLE;
}
dma_t dma_acquire_channel(void)
@ -255,11 +255,11 @@ void dma_start(dma_t dma)
#ifdef REG_DMAC_CHID
unsigned state = irq_disable();
DMAC->CHID.bit.ID = dma;
DMAC->CHID.reg = DMAC_CHID_ID(dma);
DMAC->CHCTRLA.reg = DMAC_CHCTRLA_ENABLE;
irq_restore(state);
#else
DMAC->Channel[dma].CHCTRLA.bit.ENABLE = 1;
DMAC->Channel[dma].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
#endif
}
@ -274,15 +274,15 @@ void dma_cancel(dma_t dma)
DEBUG("[DMA]: Cancelling active transfer: %u\n", dma);
#ifdef REG_DMAC_CHID
unsigned state = irq_disable();
DMAC->CHID.bit.ID = dma;
DMAC->CHID.reg = DMAC_CHID_ID(dma);
/* Write zero to the enable bit */
DMAC->CHCTRLA.reg = 0;
/* Wait until the active beat is finished */
while (DMAC->CHCTRLA.bit.ENABLE) {}
while (DMAC->CHCTRLA.reg & DMAC_CHCTRLA_ENABLE) {}
irq_restore(state);
#else
DMAC->Channel[dma].CHCTRLA.bit.ENABLE = 0;
while (DMAC->Channel[dma].CHCTRLA.bit.ENABLE) {}
DMAC->Channel[dma].CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE;
while (DMAC->Channel[dma].CHCTRLA.reg & DMAC_CHCTRLA_ENABLE) {}
#endif
}