From 9cc338d29ed8c783008ba6c8f1a49d810968d90a Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Fri, 28 Jun 2019 14:34:57 +0200 Subject: [PATCH] boards/nucleo-l4*: use shared clock configuration --- boards/b-l475e-iot01a/include/periph_conf.h | 45 +------------- boards/nucleo-l412kb/include/periph_conf.h | 45 +------------- boards/nucleo-l432kc/include/periph_conf.h | 45 +------------- boards/nucleo-l433rc/include/periph_conf.h | 56 +----------------- boards/nucleo-l476rg/include/periph_conf.h | 58 +------------------ boards/nucleo-l496zg/include/periph_conf.h | 56 +----------------- boards/p-l496g-cell02/include/periph_conf.h | 45 +------------- boards/stm32l476g-disco/include/periph_conf.h | 45 +------------- 8 files changed, 8 insertions(+), 387 deletions(-) diff --git a/boards/b-l475e-iot01a/include/periph_conf.h b/boards/b-l475e-iot01a/include/periph_conf.h index 2d05cd4556..98841c2584 100644 --- a/boards/b-l475e-iot01a/include/periph_conf.h +++ b/boards/b-l475e-iot01a/include/periph_conf.h @@ -20,56 +20,13 @@ #define PERIPH_CONF_H #include "periph_cpu.h" +#include "l4/cfg_clock_80_1.h" #include "cfg_rtt_default.h" #ifdef __cplusplus extern "C" { #endif -/** - * @name Clock system configuration - * @{ - */ -/* 0: no external high speed crystal available - * else: actual crystal frequency [in Hz] */ -#define CLOCK_HSE (0) -/* 0: no external low speed crystal available, - * 1: external crystal available (always 32.768kHz) */ -#define CLOCK_LSE (1) -/* 0: enable MSI only if HSE isn't available - * 1: always enable MSI (e.g. if USB or RNG is used)*/ -#define CLOCK_MSI_ENABLE (1) -/* 0: disable Hardware auto calibration with LSE - * 1: enable Hardware auto calibration with LSE (PLL-mode)*/ -#define CLOCK_MSI_LSE_PLL (1) -/* give the target core clock (HCLK) frequency [in Hz], maximum: 80MHz */ -#define CLOCK_CORECLOCK (80000000U) -/* PLL configuration: make sure your values are legit! - * - * compute by: CORECLOCK = (((PLL_IN / M) * N) / R) - * with: - * PLL_IN: input clock, HSE or MSI @ 48MHz - * M: pre-divider, allowed range: [1:8] - * N: multiplier, allowed range: [8:86] - * R: post-divider, allowed range: [2,4,6,8] - * - * Also the following constraints need to be met: - * (PLL_IN / M) -> [4MHz:16MHz] - * (PLL_IN / M) * N -> [64MHz:344MHz] - * CORECLOCK -> 80MHz MAX! - */ -#define CLOCK_PLL_M (6) -#define CLOCK_PLL_N (20) -#define CLOCK_PLL_R (2) -/* peripheral clock setup */ -#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 -#define CLOCK_AHB (CLOCK_CORECLOCK / 1) -#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 -#define CLOCK_APB1 (CLOCK_CORECLOCK / 4) -#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 -#define CLOCK_APB2 (CLOCK_CORECLOCK / 2) -/** @} */ - /** * @name DMA streams configuration * @{ diff --git a/boards/nucleo-l412kb/include/periph_conf.h b/boards/nucleo-l412kb/include/periph_conf.h index a8d3759112..8eb99a9918 100644 --- a/boards/nucleo-l412kb/include/periph_conf.h +++ b/boards/nucleo-l412kb/include/periph_conf.h @@ -24,6 +24,7 @@ #define PERIPH_CONF_H #include "periph_cpu.h" +#include "l4/cfg_clock_80_1.h" #include "cfg_i2c1_pb6_pb7.h" #include "cfg_timer_tim2.h" #include "cfg_rtt_default.h" @@ -33,50 +34,6 @@ extern "C" { #endif -/** - * @name Clock system configuration - * @{ - */ -/* 0: no external high speed crystal available - * else: actual crystal frequency [in Hz] */ -#define CLOCK_HSE (0) -/* 0: no external low speed crystal available, - * 1: external crystal available (always 32.768kHz) */ -#define CLOCK_LSE (1) -/* 0: enable MSI only if HSE isn't available - * 1: always enable MSI (e.g. if USB or RNG is used)*/ -#define CLOCK_MSI_ENABLE (1) -/* 0: disable Hardware auto calibration with LSE - * 1: enable Hardware auto calibration with LSE (PLL-mode)*/ -#define CLOCK_MSI_LSE_PLL (1) -/* give the target core clock (HCLK) frequency [in Hz], maximum: 80MHz */ -#define CLOCK_CORECLOCK (80000000U) -/* PLL configuration: make sure your values are legit! - * - * compute by: CORECLOCK = (((PLL_IN / M) * N) / R) - * with: - * PLL_IN: input clock, HSE or MSI @ 48MHz - * M: pre-divider, allowed range: [1:8] - * N: multiplier, allowed range: [8:86] - * R: post-divider, allowed range: [2,4,6,8] - * - * Also the following constraints need to be met: - * (PLL_IN / M) -> [4MHz:16MHz] - * (PLL_IN / M) * N -> [64MHz:344MHz] - * CORECLOCK -> 80MHz MAX! - */ -#define CLOCK_PLL_M (6) -#define CLOCK_PLL_N (20) -#define CLOCK_PLL_R (2) -/* peripheral clock setup */ -#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 -#define CLOCK_AHB (CLOCK_CORECLOCK / 1) -#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 -#define CLOCK_APB1 (CLOCK_CORECLOCK / 4) -#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 -#define CLOCK_APB2 (CLOCK_CORECLOCK / 2) -/** @} */ - /** * @name UART configuration * @{ diff --git a/boards/nucleo-l432kc/include/periph_conf.h b/boards/nucleo-l432kc/include/periph_conf.h index de24a43f8d..7b1acc3095 100644 --- a/boards/nucleo-l432kc/include/periph_conf.h +++ b/boards/nucleo-l432kc/include/periph_conf.h @@ -22,6 +22,7 @@ #define PERIPH_CONF_H #include "periph_cpu.h" +#include "l4/cfg_clock_80_1.h" #include "cfg_i2c1_pb6_pb7.h" #include "cfg_rtt_default.h" #include "cfg_timer_tim2.h" @@ -30,50 +31,6 @@ extern "C" { #endif -/** - * @name Clock system configuration - * @{ - */ -/* 0: no external high speed crystal available - * else: actual crystal frequency [in Hz] */ -#define CLOCK_HSE (0) -/* 0: no external low speed crystal available, - * 1: external crystal available (always 32.768kHz) */ -#define CLOCK_LSE (1) -/* 0: enable MSI only if HSE isn't available - * 1: always enable MSI (e.g. if USB or RNG is used)*/ -#define CLOCK_MSI_ENABLE (1) -/* 0: disable Hardware auto calibration with LSE - * 1: enable Hardware auto calibration with LSE (PLL-mode)*/ -#define CLOCK_MSI_LSE_PLL (1) -/* give the target core clock (HCLK) frequency [in Hz], maximum: 80MHz */ -#define CLOCK_CORECLOCK (80000000U) -/* PLL configuration: make sure your values are legit! - * - * compute by: CORECLOCK = (((PLL_IN / M) * N) / R) - * with: - * PLL_IN: input clock, HSE or MSI @ 48MHz - * M: pre-divider, allowed range: [1:8] - * N: multiplier, allowed range: [8:86] - * R: post-divider, allowed range: [2,4,6,8] - * - * Also the following constraints need to be met: - * (PLL_IN / M) -> [4MHz:16MHz] - * (PLL_IN / M) * N -> [64MHz:344MHz] - * CORECLOCK -> 80MHz MAX! - */ -#define CLOCK_PLL_M (6) -#define CLOCK_PLL_N (20) -#define CLOCK_PLL_R (2) -/* peripheral clock setup */ -#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 -#define CLOCK_AHB (CLOCK_CORECLOCK / 1) -#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 -#define CLOCK_APB1 (CLOCK_CORECLOCK / 4) -#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 -#define CLOCK_APB2 (CLOCK_CORECLOCK / 2) -/** @} */ - /** * @name UART configuration * @{ diff --git a/boards/nucleo-l433rc/include/periph_conf.h b/boards/nucleo-l433rc/include/periph_conf.h index 5b858a5639..dc180f5c91 100644 --- a/boards/nucleo-l433rc/include/periph_conf.h +++ b/boards/nucleo-l433rc/include/periph_conf.h @@ -20,6 +20,7 @@ #define PERIPH_CONF_H #include "periph_cpu.h" +#include "l4/cfg_clock_80_1.h" #include "cfg_rtt_default.h" #include "cfg_timer_tim2.h" @@ -27,61 +28,6 @@ extern "C" { #endif -/** - * @name Clock system configuration - * @{ - */ -/* 0: no external high speed crystal available - * else: actual crystal frequency [in Hz] */ -#define CLOCK_HSE (0) - -#ifndef CLOCK_LSE -/* 0: no external low speed crystal available, - * 1: external crystal available (always 32.768kHz) - */ -#define CLOCK_LSE (1) -#endif - -/* 0: enable MSI only if HSE isn't available - * 1: always enable MSI (e.g. if USB or RNG is used)*/ -#define CLOCK_MSI_ENABLE (1) - -#ifndef CLOCK_MSI_LSE_PLL -/* 0: disable Hardware auto calibration with LSE - * 1: enable Hardware auto calibration with LSE (PLL-mode) - * Same as with CLOCK_LSE above this defaults to 0 because LSE is - * mandatory for MSI/LSE-trimming to work */ -#define CLOCK_MSI_LSE_PLL (0) -#endif - -/* give the target core clock (HCLK) frequency [in Hz], maximum: 80MHz */ -#define CLOCK_CORECLOCK (80000000U) -/* PLL configuration: make sure your values are legit! - * - * compute by: CORECLOCK = (((PLL_IN / M) * N) / R) - * with: - * PLL_IN: input clock, HSE or MSI @ 48MHz - * M: pre-divider, allowed range: [1:8] - * N: multiplier, allowed range: [8:86] - * R: post-divider, allowed range: [2,4,6,8] - * - * Also the following constraints need to be met: - * (PLL_IN / M) -> [4MHz:16MHz] - * (PLL_IN / M) * N -> [64MHz:344MHz] - * CORECLOCK -> 80MHz MAX! - */ -#define CLOCK_PLL_M (6) -#define CLOCK_PLL_N (20) -#define CLOCK_PLL_R (2) -/* peripheral clock setup */ -#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 -#define CLOCK_AHB (CLOCK_CORECLOCK / 1) -#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 -#define CLOCK_APB1 (CLOCK_CORECLOCK / 4) -#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 -#define CLOCK_APB2 (CLOCK_CORECLOCK / 2) -/** @} */ - /** * @name UART configuration * @{ diff --git a/boards/nucleo-l476rg/include/periph_conf.h b/boards/nucleo-l476rg/include/periph_conf.h index 9dce138e6c..e5670b4f44 100644 --- a/boards/nucleo-l476rg/include/periph_conf.h +++ b/boards/nucleo-l476rg/include/periph_conf.h @@ -24,6 +24,7 @@ #define PERIPH_CONF_H #include "periph_cpu.h" +#include "l4/cfg_clock_80_1.h" #include "cfg_i2c1_pb8_pb9.h" #include "cfg_rtt_default.h" @@ -31,63 +32,6 @@ extern "C" { #endif -/** - * @name Clock system configuration - * @{ - */ -/* 0: no external high speed crystal available - * else: actual crystal frequency [in Hz] */ -#define CLOCK_HSE (0) - -#ifndef CLOCK_LSE -/* 0: no external low speed crystal available, - * 1: external crystal available (always 32.768kHz) - * This defaults to 0 because hardware revision 'MB1136 C-01' of the nucleo-64 - * board disconnects LSE by default. You may safely set this to 1 on revisions - * newer than 'MB1136 C-01' */ -#define CLOCK_LSE (1) -#endif - -/* 0: enable MSI only if HSE isn't available - * 1: always enable MSI (e.g. if USB or RNG is used)*/ -#define CLOCK_MSI_ENABLE (1) - -#ifndef CLOCK_MSI_LSE_PLL -/* 0: disable Hardware auto calibration with LSE - * 1: enable Hardware auto calibration with LSE (PLL-mode) - * Same as with CLOCK_LSE above this defaults to 0 because LSE is - * mandatory for MSI/LSE-trimming to work */ -#define CLOCK_MSI_LSE_PLL (0) -#endif - -/* give the target core clock (HCLK) frequency [in Hz], maximum: 80MHz */ -#define CLOCK_CORECLOCK (80000000U) -/* PLL configuration: make sure your values are legit! - * - * compute by: CORECLOCK = (((PLL_IN / M) * N) / R) - * with: - * PLL_IN: input clock, HSE or MSI @ 48MHz - * M: pre-divider, allowed range: [1:8] - * N: multiplier, allowed range: [8:86] - * R: post-divider, allowed range: [2,4,6,8] - * - * Also the following constraints need to be met: - * (PLL_IN / M) -> [4MHz:16MHz] - * (PLL_IN / M) * N -> [64MHz:344MHz] - * CORECLOCK -> 80MHz MAX! - */ -#define CLOCK_PLL_M (6) -#define CLOCK_PLL_N (20) -#define CLOCK_PLL_R (2) -/* peripheral clock setup */ -#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 -#define CLOCK_AHB (CLOCK_CORECLOCK / 1) -#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 -#define CLOCK_APB1 (CLOCK_CORECLOCK / 4) -#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 -#define CLOCK_APB2 (CLOCK_CORECLOCK / 2) -/** @} */ - /** * @name DMA streams configuration * @{ diff --git a/boards/nucleo-l496zg/include/periph_conf.h b/boards/nucleo-l496zg/include/periph_conf.h index 72d0870d4c..9ae0c7357f 100644 --- a/boards/nucleo-l496zg/include/periph_conf.h +++ b/boards/nucleo-l496zg/include/periph_conf.h @@ -20,6 +20,7 @@ #define PERIPH_CONF_H #include "periph_cpu.h" +#include "l4/cfg_clock_80_1.h" #include "cfg_i2c1_pb8_pb9.h" #include "cfg_rtt_default.h" @@ -27,61 +28,6 @@ extern "C" { #endif -/** - * @name Clock system configuration - * @{ - */ -/* 0: no external high speed crystal available - * else: actual crystal frequency [in Hz] */ -#define CLOCK_HSE (0) - -#ifndef CLOCK_LSE -/* 0: no external low speed crystal available, - * 1: external crystal available (always 32.768kHz) */ -#define CLOCK_LSE (1) -#endif - -/* 0: enable MSI only if HSE isn't available - * 1: always enable MSI (e.g. if USB or RNG is used)*/ -#define CLOCK_MSI_ENABLE (1) - -#ifndef CLOCK_MSI_LSE_PLL -/* 0: disable Hardware auto calibration with LSE - * 1: enable Hardware auto calibration with LSE (PLL-mode) - * Same as with CLOCK_LSE above this defaults to 0 because LSE is - * mandatory for MSI/LSE-trimming to work */ -#define CLOCK_MSI_LSE_PLL (0) -#endif - -/* give the target core clock (HCLK) frequency [in Hz], maximum: 80MHz */ -#define CLOCK_CORECLOCK (80000000U) -/* PLL configuration: make sure your values are legit! - * - * compute by: CORECLOCK = (((PLL_IN / M) * N) / R) - * with: - * PLL_IN: input clock, HSE or MSI @ 48MHz - * M: pre-divider, allowed range: [1:8] - * N: multiplier, allowed range: [8:86] - * R: post-divider, allowed range: [2,4,6,8] - * - * Also the following constraints need to be met: - * (PLL_IN / M) -> [4MHz:16MHz] - * (PLL_IN / M) * N -> [64MHz:344MHz] - * CORECLOCK -> 80MHz MAX! - */ -#define CLOCK_PLL_M (6) -#define CLOCK_PLL_N (20) -#define CLOCK_PLL_R (2) -/* peripheral clock setup */ -#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 -#define CLOCK_AHB (CLOCK_CORECLOCK / 1) -#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 -#define CLOCK_APB1 (CLOCK_CORECLOCK / 4) -#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 -#define CLOCK_APB2 (CLOCK_CORECLOCK / 2) -/** @} */ - - /** * @name Timer configuration * @{ diff --git a/boards/p-l496g-cell02/include/periph_conf.h b/boards/p-l496g-cell02/include/periph_conf.h index d0f531ab52..26afbd2830 100644 --- a/boards/p-l496g-cell02/include/periph_conf.h +++ b/boards/p-l496g-cell02/include/periph_conf.h @@ -20,6 +20,7 @@ #define PERIPH_CONF_H #include "periph_cpu.h" +#include "l4/cfg_clock_80_1.h" #include "cfg_rtt_default.h" #include "cfg_timer_tim2.h" @@ -27,50 +28,6 @@ extern "C" { #endif -/** - * @name Clock system configuration - * @{ - */ -/* 0: no external high speed crystal available - * else: actual crystal frequency [in Hz] */ -#define CLOCK_HSE (0) -/* 0: no external low speed crystal available, - * 1: external crystal available (always 32.768kHz) */ -#define CLOCK_LSE (1) -/* 0: enable MSI only if HSE isn't available - * 1: always enable MSI (e.g. if USB or RNG is used)*/ -#define CLOCK_MSI_ENABLE (1) -/* 0: disable Hardware auto calibration with LSE - * 1: enable Hardware auto calibration with LSE (PLL-mode)*/ -#define CLOCK_MSI_LSE_PLL (1) -/* give the target core clock (HCLK) frequency [in Hz], maximum: 80MHz */ -#define CLOCK_CORECLOCK (80000000U) -/* PLL configuration: make sure your values are legit! - * - * compute by: CORECLOCK = (((PLL_IN / M) * N) / R) - * with: - * PLL_IN: input clock, HSE or MSI @ 48MHz - * M: pre-divider, allowed range: [1:8] - * N: multiplier, allowed range: [8:86] - * R: post-divider, allowed range: [2,4,6,8] - * - * Also the following constraints need to be met: - * (PLL_IN / M) -> [4MHz:16MHz] - * (PLL_IN / M) * N -> [64MHz:344MHz] - * CORECLOCK -> 80MHz MAX! - */ -#define CLOCK_PLL_M (6) -#define CLOCK_PLL_N (20) -#define CLOCK_PLL_R (2) -/* peripheral clock setup */ -#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 -#define CLOCK_AHB (CLOCK_CORECLOCK / 1) -#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 -#define CLOCK_APB1 (CLOCK_CORECLOCK / 4) -#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 -#define CLOCK_APB2 (CLOCK_CORECLOCK / 2) -/** @} */ - /** * @name UART configuration * @{ diff --git a/boards/stm32l476g-disco/include/periph_conf.h b/boards/stm32l476g-disco/include/periph_conf.h index 1eb5ed1f5d..a0b1a36b64 100644 --- a/boards/stm32l476g-disco/include/periph_conf.h +++ b/boards/stm32l476g-disco/include/periph_conf.h @@ -20,56 +20,13 @@ #define PERIPH_CONF_H #include "periph_cpu.h" +#include "l4/cfg_clock_80_1.h" #include "cfg_rtt_default.h" #ifdef __cplusplus extern "C" { #endif -/** - * @name Clock system configuration - * @{ - */ -/* 0: no external high speed crystal available - * else: actual crystal frequency [in Hz] */ -#define CLOCK_HSE (0) -/* 0: no external low speed crystal available, - * 1: external crystal available (always 32.768kHz) */ -#define CLOCK_LSE (1) -/* 0: enable MSI only if HSE isn't available - * 1: always enable MSI (e.g. if USB or RNG is used)*/ -#define CLOCK_MSI_ENABLE (1) -/* 0: disable Hardware auto calibration with LSE - * 1: enable Hardware auto calibration with LSE (PLL-mode)*/ -#define CLOCK_MSI_LSE_PLL (1) -/* give the target core clock (HCLK) frequency [in Hz], maximum: 80MHz */ -#define CLOCK_CORECLOCK (80000000U) -/* PLL configuration: make sure your values are legit! - * - * compute by: CORECLOCK = (((PLL_IN / M) * N) / R) - * with: - * PLL_IN: input clock, HSE or MSI @ 48MHz - * M: pre-divider, allowed range: [1:8] - * N: multiplier, allowed range: [8:86] - * R: post-divider, allowed range: [2,4,6,8] - * - * Also the following constraints need to be met: - * (PLL_IN / M) -> [4MHz:16MHz] - * (PLL_IN / M) * N -> [64MHz:344MHz] - * CORECLOCK -> 80MHz MAX! - */ -#define CLOCK_PLL_M (6) -#define CLOCK_PLL_N (20) -#define CLOCK_PLL_R (2) -/* peripheral clock setup */ -#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 -#define CLOCK_AHB (CLOCK_CORECLOCK / 1) -#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 -#define CLOCK_APB1 (CLOCK_CORECLOCK / 4) -#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 -#define CLOCK_APB2 (CLOCK_CORECLOCK / 2) -/** @} */ - /** * @name Timer configuration * @{