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boards/cc2538: fix SPI clock initialisation

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This commit is contained in:
PeterKietzmann 2017-01-18 17:52:31 +01:00 committed by Hauke Petersen
parent 55391bc8eb
commit 9b772a45de
5 changed files with 30 additions and 25 deletions
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11
boards/cc2538dk/include/periph_conf.h
View File

@ -115,14 +115,15 @@ static const i2c_conf_t i2c_config[I2C_NUMOF] = {
* @brief Pre-calculated clock divider values based on a CLOCK_CORECLOCK (32MHz)
*
* Calculated with (CPSR * (SCR + 1)) = (CLOCK_CORECLOCK / bus_freq), where
* CPSR and SCR cannot be larger than 255.
* 1 < CPSR < 255 and
* 0 < SCR < 256
*/
static const spi_clk_conf_t spi_clk_config[] = {
{ .cpsr = 10, .scr = 31 }, /* 100khz */
{ .cpsr = 1, .scr = 79 }, /* 400khz */
{ .cpsr = 1, .scr = 31 }, /* 1MHz */
{ .cpsr = 1, .scr = 6 }, /* ~4.5MHz */
{ .cpsr = 1, .scr = 2 } /* ~10.7MHz */
{ .cpsr = 2, .scr = 39 }, /* 400khz */
{ .cpsr = 2, .scr = 15 }, /* 1MHz */
{ .cpsr = 2, .scr = 2 }, /* ~4.5MHz */
{ .cpsr = 2, .scr = 1 } /* ~10.7MHz */
};
/**

11
boards/openmote-cc2538/include/periph_conf.h
View File

@ -108,14 +108,15 @@ static const i2c_conf_t i2c_config[I2C_NUMOF] = {
* @brief Pre-calculated clock divider values based on a CLOCK_CORECLOCK (32MHz)
*
* Calculated with (CPSR * (SCR + 1)) = (CLOCK_CORECLOCK / bus_freq), where
* CPSR and SCR cannot be larger than 255.
* 1 < CPSR < 255 and
* 0 < SCR < 256
*/
static const spi_clk_conf_t spi_clk_config[] = {
{ .cpsr = 10, .scr = 31 }, /* 100khz */
{ .cpsr = 1, .scr = 79 }, /* 400khz */
{ .cpsr = 1, .scr = 31 }, /* 1MHz */
{ .cpsr = 1, .scr = 6 }, /* ~4.5MHz */
{ .cpsr = 1, .scr = 2 } /* ~10.7MHz */
{ .cpsr = 2, .scr = 39 }, /* 400khz */
{ .cpsr = 2, .scr = 15 }, /* 1MHz */
{ .cpsr = 2, .scr = 2 }, /* ~4.5MHz */
{ .cpsr = 2, .scr = 1 } /* ~10.7MHz */
};
/**

11
boards/remote-pa/include/periph_conf.h
View File

@ -74,14 +74,15 @@ static const i2c_conf_t i2c_config[I2C_NUMOF] = {
* @brief Pre-calculated clock divider values based on a CLOCK_CORECLOCK (32MHz)
*
* Calculated with (CPSR * (SCR + 1)) = (CLOCK_CORECLOCK / bus_freq), where
* CPSR and SCR cannot be larger than 255.
* 1 < CPSR < 255 and
* 0 < SCR < 256
*/
static const spi_clk_conf_t spi_clk_config[] = {
{ .cpsr = 10, .scr = 31 }, /* 100khz */
{ .cpsr = 1, .scr = 79 }, /* 400khz */
{ .cpsr = 1, .scr = 31 }, /* 1MHz */
{ .cpsr = 1, .scr = 6 }, /* ~4.5MHz */
{ .cpsr = 1, .scr = 2 } /* ~10.7MHz */
{ .cpsr = 2, .scr = 39 }, /* 400khz */
{ .cpsr = 2, .scr = 15 }, /* 1MHz */
{ .cpsr = 2, .scr = 2 }, /* ~4.5MHz */
{ .cpsr = 2, .scr = 1 } /* ~10.7MHz */
};
/**

11
boards/remote-reva/include/periph_conf.h
View File

@ -74,14 +74,15 @@ static const i2c_conf_t i2c_config[I2C_NUMOF] = {
* @brief Pre-calculated clock divider values based on a CLOCK_CORECLOCK (32MHz)
*
* Calculated with (CPSR * (SCR + 1)) = (CLOCK_CORECLOCK / bus_freq), where
* CPSR and SCR cannot be larger than 255.
* 1 < CPSR < 255 and
* 0 < SCR < 256
*/
static const spi_clk_conf_t spi_clk_config[] = {
{ .cpsr = 10, .scr = 31 }, /* 100khz */
{ .cpsr = 1, .scr = 79 }, /* 400khz */
{ .cpsr = 1, .scr = 31 }, /* 1MHz */
{ .cpsr = 1, .scr = 6 }, /* ~4.5MHz */
{ .cpsr = 1, .scr = 2 } /* ~10.7MHz */
{ .cpsr = 2, .scr = 39 }, /* 400khz */
{ .cpsr = 2, .scr = 15 }, /* 1MHz */
{ .cpsr = 2, .scr = 2 }, /* ~4.5MHz */
{ .cpsr = 2, .scr = 1 } /* ~10.7MHz */
};
/**

11
boards/remote-revb/include/periph_conf.h
View File

@ -74,14 +74,15 @@ static const i2c_conf_t i2c_config[I2C_NUMOF] = {
* @brief Pre-calculated clock divider values based on a CLOCK_CORECLOCK (32MHz)
*
* Calculated with (CPSR * (SCR + 1)) = (CLOCK_CORECLOCK / bus_freq), where
* CPSR and SCR cannot be larger than 255.
* 1 < CPSR < 255 and
* 0 < SCR < 256
*/
static const spi_clk_conf_t spi_clk_config[] = {
{ .cpsr = 10, .scr = 31 }, /* 100khz */
{ .cpsr = 1, .scr = 79 }, /* 400khz */
{ .cpsr = 1, .scr = 31 }, /* 1MHz */
{ .cpsr = 1, .scr = 6 }, /* ~4.5MHz */
{ .cpsr = 1, .scr = 2 } /* ~10.7MHz */
{ .cpsr = 2, .scr = 39 }, /* 400khz */
{ .cpsr = 2, .scr = 15 }, /* 1MHz */
{ .cpsr = 2, .scr = 2 }, /* ~4.5MHz */
{ .cpsr = 2, .scr = 1 } /* ~10.7MHz */
};
/**