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Merge pull request #8930 from gebart/pr/kinetis-rtt-refactor

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kinetis: Refactor RTT driver
This commit is contained in:
Francisco Acosta 2018-05-30 14:54:15 +02:00 committed by GitHub
commit 9a0f3469b7
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8 changed files with 68 additions and 150 deletions
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15
boards/frdm-k22f/include/periph_conf.h
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@ -267,21 +267,6 @@ static const spi_conf_t spi_config[] = {
#define I2C_0_PORT_CFG (PORT_PCR_MUX(I2C_0_PIN_AF) | PORT_PCR_ODE_MASK)
/** @} */
/**
* @name RTT and RTC configuration
* @{
*/
#define RTT_NUMOF (1U)
#define RTC_NUMOF (1U)
#define RTT_DEV RTC
#define RTT_IRQ RTC_IRQn
#define RTT_IRQ_PRIO 10
#define RTT_UNLOCK() (SIM->SCGC6 |= (SIM_SCGC6_RTC_MASK))
#define RTT_ISR isr_rtc
#define RTT_FREQUENCY (1)
#define RTT_MAX_VALUE (0xffffffff)
/** @} */
#ifdef __cplusplus
}
#endif

15
boards/frdm-k64f/include/periph_conf.h
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@ -259,21 +259,6 @@ static const spi_conf_t spi_config[] = {
#define I2C_0_PORT_CFG (PORT_PCR_MUX(I2C_0_PIN_AF) | PORT_PCR_ODE_MASK)
/** @} */
/**
* @name RTT and RTC configuration
* @{
*/
#define RTT_NUMOF (1U)
#define RTC_NUMOF (1U)
#define RTT_DEV RTC
#define RTT_IRQ RTC_IRQn
#define RTT_IRQ_PRIO 10
#define RTT_UNLOCK() (SIM->SCGC6 |= (SIM_SCGC6_RTC_MASK))
#define RTT_ISR isr_rtc
#define RTT_FREQUENCY (1)
#define RTT_MAX_VALUE (0xffffffff)
/** @} */
#ifdef __cplusplus
}
#endif

15
boards/frdm-kw41z/include/periph_conf.h
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@ -288,21 +288,6 @@ static const spi_conf_t spi_config[] = {
#define I2C_1_PORT_CFG (PORT_PCR_MUX(I2C_0_PIN_AF))
/** @} */
/**
* @name RTT and RTC configuration
* @{
*/
#define RTT_NUMOF (1U)
#define RTC_NUMOF (1U)
#define RTT_DEV RTC
#define RTT_IRQ RTC_IRQn
#define RTT_IRQ_PRIO 10
#define RTT_UNLOCK() (bit_set32(&SIM->SCGC6, SIM_SCGC6_RTC_SHIFT))
#define RTT_ISR isr_rtc
#define RTT_FREQUENCY (1)
#define RTT_MAX_VALUE (0xffffffff)
/** @} */
/**
* @name Random Number Generator configuration
* @{

23
boards/mulle/include/periph_conf.h
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@ -117,6 +117,7 @@ static const clock_config_t clock_config = {
#define PIT_ISR_0 isr_pit1
#define PIT_ISR_1 isr_pit3
#define LPTMR_ISR_0 isr_lptmr0
/** @} */
/**
@ -376,28 +377,6 @@ static const spi_conf_t spi_config[] = {
#define KINETIS_I2C_F_MULT_FAST_PLUS (0)
/** @} */
/**
* @name RTC configuration
* @{
*/
/* RIOT RTC implementation uses RTT for underlying timekeeper */
#define RTC_NUMOF (1U)
/** @} */
/**
* @name RTT configuration
* @{
*/
#define RTT_NUMOF (1U)
#define RTT_IRQ RTC_IRQn
#define RTT_IRQ_PRIO 10
#define RTT_ISR isr_rtc
#define RTT_DEV RTC
#define RTT_UNLOCK() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_RTC_SHIFT) = 1)
#define RTT_MAX_VALUE (0xffffffff)
#define RTT_FREQUENCY (1) /* in Hz */
/** @} */
#ifdef __cplusplus
}
#endif

15
boards/pba-d-01-kw2x/include/periph_conf.h
View File

@ -289,21 +289,6 @@ static const spi_conf_t spi_config[] = {
/** @} */
/**
* @name RTT and RTC configuration
* @{
*/
#define RTT_NUMOF (1U)
#define RTC_NUMOF (1U)
#define RTT_DEV RTC
#define RTT_IRQ RTC_IRQn
#define RTT_IRQ_PRIO 10
#define RTT_UNLOCK() (SIM->SCGC6 |= (SIM_SCGC6_RTC_MASK))
#define RTT_ISR isr_rtc
#define RTT_FREQUENCY (1)
#define RTT_MAX_VALUE (0xffffffff)
/** @} */
#ifdef __cplusplus
}
#endif

8
boards/teensy31/Makefile.features
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@ -1,11 +1,13 @@
# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_pwm
FEATURES_PROVIDED += periph_rtc
FEATURES_PROVIDED += periph_rtt
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart
# The board MPU family (used for grouping by the CI system)
FEATURES_MCU_GROUP = cortex_m4_2
include $(RIOTCPU)/cortexm_common/Makefile.features
include $(RIOTCPU)/kinetis/Makefile.features
# No HWRNG in MK20D7 devices
FEATURES_PROVIDED := $(filter-out periph_hwrng,$(FEATURES_PROVIDED))

14
cpu/kinetis/include/periph_cpu.h
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@ -114,6 +114,20 @@ typedef uint16_t gpio_t;
*/
#define PM_NUM_MODES (1U)
#ifdef RTC
/* All Kinetis CPUs have exactly one RTC hardware module, except for the KL02
* family which don't have an RTC at all */
/**
* @name RTT and RTC configuration
* @{
*/
#define RTT_NUMOF (1U)
#define RTC_NUMOF (1U)
#define RTT_FREQUENCY (1)
#define RTT_MAX_VALUE (0xffffffff)
/** @} */
#endif
#ifndef DOXYGEN
/**
* @name GPIO pin modes

113
cpu/kinetis/periph/rtt.c
View File

@ -15,7 +15,7 @@
*
* @file
* @brief Low-level RTT interface implementation for Freescale Kinetis
* MCUs. Freescale's RTC module is what RIOT calls a Real-Time
* MCUs. NXP's RTC module is what RIOT calls a Real-Time
* Timer (RTT), a simple counter which counts seconds; RIOT Real-
* Time Clocks (RTC) counts seconds, minutes, hours etc. We provide
* an RTT->RTC wrapper layer in a separate file to allow using the
@ -29,16 +29,13 @@
#include <time.h>
#include "cpu.h"
#include "bit.h"
#include "periph/rtt.h"
#include "periph_conf.h"
#define ENABLE_DEBUG (0)
#include "debug.h"
#ifndef RTC_LOAD_CAP_BITS
#define RTC_LOAD_CAP_BITS 0
#endif
typedef struct {
rtt_cb_t alarm_cb; /**< callback called from RTC alarm */
void *alarm_arg; /**< argument passed to the callback */
@ -50,58 +47,58 @@ static rtt_state_t rtt_callback;
void rtt_init(void)
{
RTC_Type *rtt = RTT_DEV;
/* Enable module clock gate */
RTC_CLKEN();
RTT_UNLOCK();
/* Reset RTC */
rtt->CR = RTC_CR_SWR_MASK;
/* cppcheck-suppress redundantAssignment
* reset routine */
rtt->CR = 0;
/* At this point, the CPU core may be clocked by a clock derived from the
* RTC oscillator, avoid touching the oscillator enable bit (OSCE) in RTC_CR */
if (rtt->SR & RTC_SR_TIF_MASK) {
/* Clear TIF by writing TSR. */
rtt->TSR = 0;
}
/* Enable RTC oscillator and non-supervisor mode accesses. */
/* Enable load capacitance as configured by periph_conf.h */
rtt->CR = RTC_CR_OSCE_MASK | RTC_CR_SUP_MASK | RTC_LOAD_CAP_BITS;
/* Clear TAF by writing TAR. */
rtt->TAR = 0xffffff42;
/* Enable user mode access */
bit_set32(&RTC->CR, RTC_CR_SUP_SHIFT);
/* Disable all RTC interrupts. */
rtt->IER = 0;
RTC->IER = 0;
/* The RTC module is only reset on VBAT power on reset, we try to preserve
* the seconds counter between reboots */
if (RTC->SR & RTC_SR_TIF_MASK) {
/* Time Invalid Flag is set, clear TIF by writing TSR */
/* Stop counter to make TSR writable */
bit_clear32(&RTC->SR, RTC_SR_TCE_SHIFT);
RTC->TSR = 0;
}
/* Clear the alarm flag TAF by writing a new alarm target to TAR */
RTC->TAR = 0xffffffff;
/* Enable RTC interrupts */
NVIC_EnableIRQ(RTC_IRQn);
rtt_poweron();
}
void rtt_set_overflow_cb(rtt_cb_t cb, void *arg)
{
RTC_Type *rtt = RTT_DEV;
rtt_callback.overflow_cb = cb;
rtt_callback.overflow_arg = arg;
rtt->IER |= RTC_IER_TOIE_MASK;
bit_set32(&RTC->IER, RTC_IER_TOIE_SHIFT);
}
void rtt_clear_overflow_cb(void)
{
RTC_Type *rtt = RTT_DEV;
rtt_callback.overflow_cb = NULL;
rtt_callback.overflow_arg = NULL;
rtt->IER &= ~(RTC_IER_TOIE_MASK);
bit_clear32(&RTC->IER, RTC_IER_TOIE_SHIFT);
}
uint32_t rtt_get_counter(void)
{
RTC_Type *rtt = RTT_DEV;
uint32_t t;
for (int i = 0; i < 3; i++) {
/* Read twice to make sure we get a stable reading */
t = rtt->TSR;
t = RTC->TSR;
if (t == rtt->TSR) {
if (t == RTC->TSR) {
return t;
}
}
@ -111,13 +108,11 @@ uint32_t rtt_get_counter(void)
void rtt_set_counter(uint32_t counter)
{
RTC_Type *rtt = RTT_DEV;
/* Disable time counter before writing to the timestamp register */
rtt->SR &= ~RTC_SR_TCE_MASK;
rtt->TSR = counter;
bit_clear32(&RTC->SR, RTC_SR_TCE_SHIFT);
RTC->TSR = counter;
/* Enable when done */
rtt->SR |= RTC_SR_TCE_MASK;
bit_set32(&RTC->SR, RTC_SR_TCE_SHIFT);
}
@ -125,71 +120,59 @@ void rtt_set_alarm(uint32_t alarm, rtt_cb_t cb, void *arg)
{
/* The alarm is triggered when TSR matches TAR, and TSR increments. This
* seem counterintuitive as most users expect the alarm to trigger
* immediately when the counter becomes equal to the alarm time. */
RTC_Type *rtt = RTT_DEV;
* immediately when the counter becomes equal to the alarm time.
*
* Workaround: Set TAF to alarm - 1
*/
/* Disable Timer Alarm Interrupt */
rtt->IER &= ~(RTC_IER_TAIE_MASK);
bit_clear32(&RTC->IER, RTC_IER_TAIE_SHIFT);
rtt->TAR = alarm - 1;
RTC->TAR = alarm - 1;
rtt_callback.alarm_cb = cb;
rtt_callback.alarm_arg = arg;
/* Enable Timer Alarm Interrupt */
rtt->IER |= RTC_IER_TAIE_MASK;
/* Enable RTC interrupts */
NVIC_SetPriority(RTT_IRQ, RTT_IRQ_PRIO);
NVIC_EnableIRQ(RTT_IRQ);
bit_set32(&RTC->IER, RTC_IER_TAIE_SHIFT);
}
uint32_t rtt_get_alarm(void)
{
RTC_Type *rtt = RTT_DEV;
return rtt->TAR + 1;
return RTC->TAR + 1;
}
void rtt_clear_alarm(void)
{
RTC_Type *rtt = RTT_DEV;
/* Disable Timer Alarm Interrupt */
rtt->IER &= ~RTC_IER_TAIE_MASK;
rtt->TAR = 0;
rtt_callback.alarm_cb = NULL;
rtt_callback.alarm_arg = NULL;
bit_clear32(&RTC->IER, RTC_IER_TAIE_SHIFT);
}
/* RTC module has independent power suply. We can not really turn it on/off. */
void rtt_poweron(void)
{
RTC_Type *rtt = RTT_DEV;
/* Enable Time Counter */
rtt->SR |= RTC_SR_TCE_MASK;
bit_set32(&RTC->SR, RTC_SR_TCE_SHIFT);
}
void rtt_poweroff(void)
{
RTC_Type *rtt = RTT_DEV;
/* Disable Time Counter */
rtt->SR &= ~RTC_SR_TCE_MASK;
bit_clear32(&RTC->SR, RTC_SR_TCE_SHIFT);
}
void RTT_ISR(void)
void isr_rtc(void)
{
RTC_Type *rtt = RTT_DEV;
if (rtt->SR & RTC_SR_TAF_MASK) {
if (RTC->SR & RTC_SR_TAF_MASK) {
if (rtt_callback.alarm_cb != NULL) {
/* Disable Timer Alarm Interrupt */
rtt->IER &= ~RTC_IER_TAIE_MASK;
bit_clear32(&RTC->IER, RTC_IER_TAIE_SHIFT);
rtt_callback.alarm_cb(rtt_callback.alarm_arg);
}
}
if (rtt->SR & RTC_SR_TOF_MASK) {
if (RTC->SR & RTC_SR_TOF_MASK) {
if (rtt_callback.overflow_cb != NULL) {
rtt_callback.overflow_cb(rtt_callback.overflow_arg);
}