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cpu/stm32: GPIO: use bitarithm_test_and_clear()

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This commit is contained in:
Benjamin Valentin 2020-07-21 00:56:29 +02:00
parent 403b6b15c6
commit 9970c57cdf
1 changed files with 17 additions and 16 deletions
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33
cpu/stm32/periph/gpio_all.c
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@ -28,6 +28,7 @@
#include "cpu.h" #include "cpu.h"
#include "bitarithm.h"
#include "periph/gpio.h" #include "periph/gpio.h"
#include "periph_conf.h" #include "periph_conf.h"
@ -289,26 +290,26 @@ void isr_exti(void)
/* only generate interrupts against lines which have their IMR set */ /* only generate interrupts against lines which have their IMR set */
uint32_t pending_rising_isr = (EXTI->RPR1 & EXTI_REG_IMR); uint32_t pending_rising_isr = (EXTI->RPR1 & EXTI_REG_IMR);
uint32_t pending_falling_isr = (EXTI->FPR1 & EXTI_REG_IMR); uint32_t pending_falling_isr = (EXTI->FPR1 & EXTI_REG_IMR);
for (size_t i = 0; i < EXTI_NUMOF; i++) {
if (pending_rising_isr & (1 << i)) { /* clear by writing a 1 */
EXTI->RPR1 = (1 << i); /* clear by writing a 1 */ EXTI->RPR1 = pending_rising_isr;
isr_ctx[i].cb(isr_ctx[i].arg); EXTI->FPR1 = pending_falling_isr;
}
if (pending_falling_isr & (1 << i)) { uint32_t pending_isr = pending_rising_isr | pending_falling_isr;
EXTI->FPR1 = (1 << i); /* clear by writing a 1 */
isr_ctx[i].cb(isr_ctx[i].arg);
}
}
#else #else
/* only generate interrupts against lines which have their IMR set */ /* only generate interrupts against lines which have their IMR set */
uint32_t pending_isr = (EXTI_REG_PR & EXTI_REG_IMR); uint32_t pending_isr = (EXTI_REG_PR & EXTI_REG_IMR);
for (size_t i = 0; i < EXTI_NUMOF; i++) {
if (pending_isr & (1 << i)) { /* clear by writing a 1 */
EXTI_REG_PR = (1 << i); /* clear by writing a 1 */ EXTI_REG_PR = pending_isr;
isr_ctx[i].cb(isr_ctx[i].arg);
}
}
#endif #endif
/* iterate over all set bits */
uint8_t pin = 0;
while (pending_isr) {
pending_isr = bitarithm_test_and_clear(pending_isr, &pin);
isr_ctx[pin].cb(isr_ctx[pin].arg);
}
cortexm_isr_end(); cortexm_isr_end();
} }
#endif /* MODULE_PERIPH_GPIO_IRQ */ #endif /* MODULE_PERIPH_GPIO_IRQ */