RIOT-OS/RIOT
RIOT-OS/RIOT
1
0
Fork 0
mirror of https://github.com/RIOT-OS/RIOT.git synced 2024-12-29 04:50:03 +01:00
Code Releases Activity

cpu/sam3: udpate gpio driver

Browse Source
This commit is contained in:
TobiasFredersdorf 2016-01-20 17:10:40 +01:00
parent d60bfc0ae2
commit 9864c84c92
3 changed files with 273 additions and 2264 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

202
boards/arduino-due/include/periph_conf.h
View File

@ -113,208 +113,6 @@ static const uart_conf_t uart_config[] = {
#define SPI_0_SCK_PORT_CLKEN() (PMC->PMC_PCER0 |= (1 << ID_PIOA));
/** @} */
/**
* @name GPIO configuration
* @{
*/
#define GPIO_0_EN 1
#define GPIO_1_EN 1
#define GPIO_2_EN 1
#define GPIO_3_EN 1
#define GPIO_4_EN 1
#define GPIO_5_EN 1
#define GPIO_6_EN 1
#define GPIO_7_EN 1
#define GPIO_8_EN 1
#define GPIO_9_EN 1
#define GPIO_10_EN 1
#define GPIO_11_EN 1
#define GPIO_12_EN 1
#define GPIO_13_EN 1
#define GPIO_14_EN 1
#define GPIO_15_EN 1
#define GPIO_16_EN 1
#define GPIO_17_EN 1
#define GPIO_18_EN 1
#define GPIO_19_EN 1
#define GPIO_20_EN 1
#define GPIO_21_EN 1
#define GPIO_22_EN 1
#define GPIO_23_EN 1
#define GPIO_24_EN 1
#define GPIO_25_EN 1
#define GPIO_26_EN 1
#define GPIO_27_EN 1
#define GPIO_28_EN 1
#define GPIO_29_EN 1
#define GPIO_30_EN 1
#define GPIO_31_EN 1
/* interrupt priority */
#define GPIO_IRQ_PRIO 1
/* GPIO channel 0 config */
#define GPIO_0_DEV PIOA
#define GPIO_0_PIN PIO_PA14
#define GPIO_0_IRQ PIOA_IRQn
#define GPIO_A14_MAP 0
/* GPIO channel 1 config */
#define GPIO_1_DEV PIOD
#define GPIO_1_PIN PIO_PD0
#define GPIO_1_IRQ PIOD_IRQn
#define GPIO_D0_MAP 1
/* GPIO channel 2 config */
#define GPIO_2_DEV PIOD
#define GPIO_2_PIN PIO_PD2
#define GPIO_2_IRQ PIOD_IRQn
#define GPIO_D2_MAP 2
/* GPIO channel 3 config */
#define GPIO_3_DEV PIOD
#define GPIO_3_PIN PIO_PD6
#define GPIO_3_IRQ PIOD_IRQn
#define GPIO_D6_MAP 3
/* GPIO channel 4 config */
#define GPIO_4_DEV PIOA
#define GPIO_4_PIN PIO_PA7
#define GPIO_4_IRQ PIOA_IRQn
#define GPIO_A7_MAP 4
/* GPIO channel 5 config */
#define GPIO_5_DEV PIOC
#define GPIO_5_PIN PIO_PC1
#define GPIO_5_IRQ PIOC_IRQn
#define GPIO_C1_MAP 5
/* GPIO channel 6 config */
#define GPIO_6_DEV PIOC
#define GPIO_6_PIN PIO_PC3
#define GPIO_6_IRQ PIOC_IRQn
#define GPIO_C3_MAP 6
/* GPIO channel 7 config */
#define GPIO_7_DEV PIOC
#define GPIO_7_PIN PIO_PC5
#define GPIO_7_IRQ PIOC_IRQn
#define GPIO_C5_MAP 7
/* GPIO channel 8 config */
#define GPIO_8_DEV PIOC
#define GPIO_8_PIN PIO_PC7
#define GPIO_8_IRQ PIOC_IRQn
#define GPIO_C7_MAP 8
/* GPIO channel 9 config */
#define GPIO_9_DEV PIOC
#define GPIO_9_PIN PIO_PC9
#define GPIO_9_IRQ PIOC_IRQn
#define GPIO_C9_MAP 9
/* GPIO channel 10 config */
#define GPIO_10_DEV PIOA
#define GPIO_10_PIN PIO_PA20
#define GPIO_10_IRQ PIOA_IRQn
#define GPIO_A20_MAP 10
/* GPIO channel 11 config */
#define GPIO_11_DEV PIOC
#define GPIO_11_PIN PIO_PC18
#define GPIO_11_IRQ PIOC_IRQn
#define GPIO_C18_MAP 11
/* GPIO channel 12 config */
#define GPIO_12_DEV PIOC
#define GPIO_12_PIN PIO_PC16
#define GPIO_12_IRQ PIOC_IRQn
#define GPIO_C16_MAP 12
/* GPIO channel 13 config */
#define GPIO_13_DEV PIOC
#define GPIO_13_PIN PIO_PC14
#define GPIO_13_IRQ PIOC_IRQn
#define GPIO_C14_MAP 13
/* GPIO channel 14 config */
#define GPIO_14_DEV PIOC
#define GPIO_14_PIN PIO_PC12
#define GPIO_14_IRQ PIOC_IRQn
#define GPIO_C12_MAP 14
/* GPIO channel 15 config */
#define GPIO_15_DEV PIOB
#define GPIO_15_PIN PIO_PB14
#define GPIO_15_IRQ PIOB_IRQn
#define GPIO_B14_MAP 15
/* GPIO channel 16 config */
#define GPIO_16_DEV PIOB
#define GPIO_16_PIN PIO_PB26
#define GPIO_16_IRQ PIOB_IRQn
#define GPIO_B26_MAP 16
/* GPIO channel 17 config */
#define GPIO_17_DEV PIOA
#define GPIO_17_PIN PIO_PA15
#define GPIO_17_IRQ PIOA_IRQn
#define GPIO_A15_MAP 17
/* GPIO channel 18 config */
#define GPIO_18_DEV PIOD
#define GPIO_18_PIN PIO_PD1
#define GPIO_18_IRQ PIOD_IRQn
#define GPIO_D1_MAP 18
/* GPIO channel 19 config */
#define GPIO_19_DEV PIOD
#define GPIO_19_PIN PIO_PD3
#define GPIO_19_IRQ PIOD_IRQn
#define GPIO_D3_MAP 19
/* GPIO channel 20 config */
#define GPIO_20_DEV PIOD
#define GPIO_20_PIN PIO_PD9
#define GPIO_20_IRQ PIOD_IRQn
#define GPIO_D9_MAP 20
/* GPIO channel 21 config */
#define GPIO_21_DEV PIOD
#define GPIO_21_PIN PIO_PD10
#define GPIO_21_IRQ PIOD_IRQn
#define GPIO_D10_MAP 21
/* GPIO channel 22 config */
#define GPIO_22_DEV PIOC
#define GPIO_22_PIN PIO_PC2
#define GPIO_22_IRQ PIOC_IRQn
#define GPIO_C2_MAP 22
/* GPIO channel 23 config */
#define GPIO_23_DEV PIOC
#define GPIO_23_PIN PIO_PC4
#define GPIO_23_IRQ PIOC_IRQn
#define GPIO_C4_MAP 23
/* GPIO channel 24 config */
#define GPIO_24_DEV PIOC
#define GPIO_24_PIN PIO_PC6
#define GPIO_24_IRQ PIOC_IRQn
#define GPIO_C6_MAP 24
/* GPIO channel 25 config */
#define GPIO_25_DEV PIOC
#define GPIO_25_PIN PIO_PC8
#define GPIO_25_IRQ PIOC_IRQn
#define GPIO_C8_MAP 25
/* GPIO channel 26 config */
#define GPIO_26_DEV PIOA
#define GPIO_26_PIN PIO_PA19
#define GPIO_26_IRQ PIOA_IRQn
#define GPIO_A19_MAP 26
/* GPIO channel 27 config */
#define GPIO_27_DEV PIOC
#define GPIO_27_PIN PIO_PC19
#define GPIO_27_IRQ PIOC_IRQn
#define GPIO_C19_MAP 27
/* GPIO channel 28 config */
#define GPIO_28_DEV PIOC
#define GPIO_28_PIN PIO_PC17
#define GPIO_28_IRQ PIOC_IRQn
#define GPIO_C17_MAP 28
/* GPIO channel 29 config */
#define GPIO_29_DEV PIOC
#define GPIO_29_PIN PIO_PC15
#define GPIO_29_IRQ PIOC_IRQn
#define GPIO_C15_MAP 29
/* GPIO channel 30 config */
#define GPIO_30_DEV PIOC
#define GPIO_30_PIN PIO_PC13
#define GPIO_30_IRQ PIOC_IRQn
#define GPIO_C13_MAP 30
/* GPIO channel 31 config */
#define GPIO_31_DEV PIOB
#define GPIO_31_PIN PIO_PB21
#define GPIO_31_IRQ PIOB_IRQn
#define GPIO_B21_MAP 31
/** @} */
/**
* @name PWM configuration
* @{

69
cpu/sam3/include/periph_cpu.h
View File

@ -1,5 +1,6 @@
/*
* Copyright (C) 2015 Freie Universität Berlin
* 2015 Hamburg University of Applied Sciences
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
@ -7,26 +8,46 @@
*/
/**
* @ingroup cpu_sam3x8e
* @ingroup cpu_sam3x8e
* @{
*
* @file
* @brief CPU specific definitions for internal peripheral handling
* @brief CPU specific definitions for internal peripheral handling
*
* @author Hauke Petersen <hauke.peterse@fu-berlin.de>
* @author Tobias Fredersdorf <tobias.fredersdorf@haw-hamburg.de>
*
* @author Hauke Petersen <hauke.peterse@fu-berlin.de>
*/
#ifndef PERIPH_CPU_H_
#define PERIPH_CPU_H_
#ifndef PERIPH_CPU_H
#define PERIPH_CPU_H
#include "cpu.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief declare needed generic SPI functions
* @brief Overwrite the default gpio_t type definition
*/
#define HAVE_GPIO_T
typedef uint32_t gpio_t;
/** @} */
/**
* @brief Definition of a fitting UNDEF value
*/
#define GPIO_UNDEF (0xffffffff)
/**
* @brief Define a CPU specific GPIO pin generator macro
*/
#define GPIO_PIN(x, y) (((uint32_t)PIOA + (x << 9)) | y)
/**
* @brief Declare needed generic SPI functions
* @{
*/
#define PERIPH_SPI_NEEDS_TRANSFER_BYTES
@ -34,6 +55,40 @@ extern "C" {
#define PERIPH_SPI_NEEDS_TRANSFER_REGS
/** @} */
/**
* @brief Override values for pull register configuration
* @{
*/
#define HAVE_GPIO_PP_T
typedef enum {
GPIO_NOPULL = 4, /**< do not use internal pull resistors */
GPIO_PULLUP = 9, /**< enable internal pull-up resistor */
GPIO_PULLDOWN = 8 /**< enable internal pull-down resistor */
} gpio_pp_t;
/** @} */
/**
* @brief Override flank configuration values
* @{
*/
#define HAVE_GPIO_FLANK_T
typedef enum {
GPIO_RISING = 1, /**< emit interrupt on rising flank */
GPIO_FALLING = 2, /**< emit interrupt on falling flank */
GPIO_BOTH = 3 /**< emit interrupt on both flanks */
} gpio_flank_t;
/** @} */
/**
* @brief Available ports on the SAM3X8E
*/
enum {
PA = 0, /**< port A */
PB = 1, /**< port B */
PC = 2, /**< port C */
PD = 3, /**< port D */
};
/**
* @brief GPIO mux configuration
*/
@ -60,5 +115,5 @@ typedef struct {
}
#endif
#endif /* PERIPH_CPU_H_ */
#endif /* PERIPH_CPU_H */
/** @} */

2266
cpu/sam3/periph/gpio.c
View File

File diff suppressed because it is too large Load Diff