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boards/z1: fix broken clock configuration

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df5c319978 from
https://github.com/RIOT-OS/RIOT/pull/19558 broke the clock
configuration of the Z1 by relying on the incorrect documentation of
what clock is actually used. Closely reading the convoluted clock
initialization code revealed that no XT2 crystal is present (as also
indicated by some comments in `board.c`), contradicting the
`#define MSP430_HAS_EXTERNAL_CRYSTAL 1` in the `board.h`.

This now should restore behavior (but with calibrated DCO than
hard coded magic numbers).
This commit is contained in:
Marian Buschsieweke 2023-06-03 23:05:08 +02:00
parent f2250015c2
commit 971dc880f6
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1 changed files with 4 additions and 4 deletions
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8
boards/z1/include/periph_conf.h
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@ -28,16 +28,16 @@
extern "C" {
#endif
#define CLOCK_CORECLOCK MHZ(8)
#define CLOCK_CORECLOCK msp430_fxyz_dco_freq
/**
* @brief Clock configuration
*/
static const msp430_fxyz_clock_params_t clock_params = {
.xt2_frequency = CLOCK_CORECLOCK,
.target_dco_frequency = MHZ(8),
.lfxt1_frequency = 32768,
.main_clock_source = MAIN_CLOCK_SOURCE_XT2CLK,
.submain_clock_source = SUBMAIN_CLOCK_SOURCE_XT2CLK,
.main_clock_source = MAIN_CLOCK_SOURCE_DCOCLK,
.submain_clock_source = SUBMAIN_CLOCK_SOURCE_DCOCLK,
.main_clock_divier = MAIN_CLOCK_DIVIDE_BY_1,
.submain_clock_divier = SUBMAIN_CLOCK_DIVIDE_BY_1,
.auxiliary_clock_divier = AUXILIARY_CLOCK_DIVIDE_BY_1,