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boards/stm32f4*: add Kconfig clock configuration
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@ -17,3 +17,9 @@ config BOARD_COMMON_WEACT_F41XCX
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select HAS_PERIPH_UART
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select HAS_PERIPH_USBDEV
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select HAS_HIGHLEVEL_STDIO
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# Clock configuration
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select BOARD_HAS_HSE
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select BOARD_HAS_LSE
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source "$(RIOTBOARD)/common/stm32/Kconfig"
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@ -12,3 +12,6 @@ FEATURES_PROVIDED += periph_usbdev
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# Various other features (if any)
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FEATURES_PROVIDED += highlevel_stdio
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# weact-f4x1cx boards provide a custom default Kconfig clock configuration
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KCONFIG_ADD_CONFIG += $(RIOTBOARD)/common/weact-f4x1cx/clock.config
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4
boards/common/weact-f4x1cx/clock.config
Normal file
4
boards/common/weact-f4x1cx/clock.config
Normal file
@ -0,0 +1,4 @@
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# weact-f4x1cx based boards provide a 25MHz HSE so they need a custom PLL config
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# to output a 48MHz clock for USB.
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CONFIG_CUSTOM_PLL_PARAMS=y
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CONFIG_CLOCK_PLL_M=25
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@ -16,3 +16,9 @@ config BOARD_F4VI1
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# Put defined MCU peripherals here (in alphabetical order)
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select HAS_PERIPH_TIMER
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select HAS_PERIPH_UART
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# Clock configuration
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select BOARD_HAS_HSE
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select BOARD_HAS_LSE
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source "$(RIOTBOARD)/common/stm32/Kconfig"
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@ -5,3 +5,6 @@ CPU_MODEL = stm32f415rg
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# Put defined MCU peripherals here (in alphabetical order)
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FEATURES_PROVIDED += periph_timer
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FEATURES_PROVIDED += periph_uart
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# f4vi1 provides a custom default Kconfig clock configuration
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KCONFIG_ADD_CONFIG += $(RIOTBOARD)/f4vi1/clock.config
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4
boards/f4vi1/clock.config
Normal file
4
boards/f4vi1/clock.config
Normal file
@ -0,0 +1,4 @@
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# f4vi1 provides a 16MHz HSE so they need a custom PLL config
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# to remain in 180MHz max clock.
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CONFIG_CUSTOM_PLL_PARAMS=y
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CONFIG_CLOCK_PLL_N=90
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@ -22,3 +22,9 @@ config BOARD_MSBIOT
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select HAS_PERIPH_SPI
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select HAS_PERIPH_TIMER
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select HAS_PERIPH_UART
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# Clock configuration
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select BOARD_HAS_HSE
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select BOARD_HAS_LSE
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source "$(RIOTBOARD)/common/stm32/Kconfig"
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@ -10,3 +10,6 @@ FEATURES_PROVIDED += periph_pwm
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FEATURES_PROVIDED += periph_spi
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FEATURES_PROVIDED += periph_timer
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FEATURES_PROVIDED += periph_uart
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# msbiot provides a custom default Kconfig clock configuration
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KCONFIG_ADD_CONFIG += $(RIOTBOARD)/msbiot/clock.config
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5
boards/msbiot/clock.config
Normal file
5
boards/msbiot/clock.config
Normal file
@ -0,0 +1,5 @@
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# msbiot provides a 16MHz HSE so its needs a custom PLL config to output a
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# 180MHz clock.
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CONFIG_CUSTOM_PLL_PARAMS=y
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CONFIG_CLOCK_PLL_M=16
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CONFIG_CLOCK_PLL_N=360
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@ -25,4 +25,8 @@ config BOARD_NUCLEO_F401RE
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select HAS_PERIPH_UART
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select HAS_PERIPH_QDEC
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# Clock configuration
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select BOARD_HAS_HSE
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select BOARD_HAS_LSE
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source "$(RIOTBOARD)/common/nucleo64/Kconfig"
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@ -23,4 +23,8 @@ config BOARD_NUCLEO_F410RB
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select HAS_PERIPH_TIMER
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select HAS_PERIPH_UART
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# Clock configuration
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select BOARD_HAS_HSE
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select BOARD_HAS_LSE
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source "$(RIOTBOARD)/common/nucleo64/Kconfig"
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@ -24,4 +24,8 @@ config BOARD_NUCLEO_F411RE
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select HAS_PERIPH_TIMER
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select HAS_PERIPH_UART
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# Clock configuration
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select BOARD_HAS_HSE
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select BOARD_HAS_LSE
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source "$(RIOTBOARD)/common/nucleo64/Kconfig"
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@ -25,4 +25,8 @@ config BOARD_NUCLEO_F412ZG
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select HAS_PERIPH_UART
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select HAS_PERIPH_USBDEV
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# Clock configuration
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select BOARD_HAS_HSE
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select BOARD_HAS_LSE
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source "$(RIOTBOARD)/common/nucleo144/Kconfig"
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@ -28,4 +28,8 @@ config BOARD_NUCLEO_F413ZH
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select HAS_PERIPH_UART
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select HAS_PERIPH_USBDEV
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# Clock configuration
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select BOARD_HAS_HSE
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select BOARD_HAS_LSE
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source "$(RIOTBOARD)/common/nucleo144/Kconfig"
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@ -25,4 +25,8 @@ config BOARD_NUCLEO_F429ZI
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select HAS_PERIPH_UART
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select HAS_PERIPH_USBDEV
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# Clock configuration
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select BOARD_HAS_HSE
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select BOARD_HAS_LSE
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source "$(RIOTBOARD)/common/nucleo144/Kconfig"
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@ -30,4 +30,8 @@ config BOARD_NUCLEO_F446RE
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select HAS_MOTOR_DRIVER
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select HAS_RIOTBOOT
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# Clock configuration
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select BOARD_HAS_HSE
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select BOARD_HAS_LSE
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source "$(RIOTBOARD)/common/nucleo64/Kconfig"
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@ -25,4 +25,8 @@ config BOARD_NUCLEO_F446ZE
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select HAS_PERIPH_UART
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select HAS_PERIPH_USBDEV
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# Clock configuration
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select BOARD_HAS_HSE
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select BOARD_HAS_LSE
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source "$(RIOTBOARD)/common/nucleo144/Kconfig"
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@ -21,3 +21,9 @@ config BOARD_PYBOARD
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select HAS_PERIPH_TIMER
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select HAS_PERIPH_UART
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select HAS_PERIPH_USBDEV
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# Clock configuration
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select BOARD_HAS_HSE
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select BOARD_HAS_LSE
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source "$(RIOTBOARD)/common/stm32/Kconfig"
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@ -9,3 +9,6 @@ FEATURES_PROVIDED += periph_spi
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FEATURES_PROVIDED += periph_timer
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FEATURES_PROVIDED += periph_uart
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FEATURES_PROVIDED += periph_usbdev
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# pyboard provides a custom default Kconfig clock configuration
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KCONFIG_ADD_CONFIG += $(RIOTBOARD)/pyboard/clock.config
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5
boards/pyboard/clock.config
Normal file
5
boards/pyboard/clock.config
Normal file
@ -0,0 +1,5 @@
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# pyboard provides a 12MHz HSE so its needs a custom PLL config to output a
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# 48MHz clock for USB.
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CONFIG_CUSTOM_PLL_PARAMS=y
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CONFIG_CLOCK_PLL_M=12
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CONFIG_CLOCK_PLL_N=336
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@ -23,3 +23,9 @@ config BOARD_STM32F429I_DISC1
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# Put other features for this board (in alphabetical order)
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select HAS_RIOTBOOT
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# Clock configuration
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select BOARD_HAS_HSE
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select BOARD_HAS_LSE
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source "$(RIOTBOARD)/common/stm32/Kconfig"
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@ -24,3 +24,9 @@ config BOARD_STM32F429I_DISCO
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# Put other features for this board (in alphabetical order)
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select HAS_HIGHLEVEL_STDIO
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select HAS_RIOTBOOT
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# Clock configuration
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select BOARD_HAS_HSE
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select BOARD_HAS_LSE
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source "$(RIOTBOARD)/common/stm32/Kconfig"
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@ -28,6 +28,11 @@ config BOARD_STM32F4DISCOVERY
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# Various other features (if any)
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select HAS_ARDUINO
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# Clock configuration
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select BOARD_HAS_HSE
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source "$(RIOTBOARD)/common/stm32/Kconfig"
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config ERROR_MODULES_CONFLICT
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default "On stm32f4discovery boards there are the same pins for the DAC and/or SPI_0." if MODULE_PERIPH_SPI && MODULE_PERIPH_DAC
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depends on BOARD_STM32F4DISCOVERY
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@ -21,3 +21,9 @@ config BOARD_UBLOX_C030_U201
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select HAS_PERIPH_SPI
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select HAS_PERIPH_TIMER
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select HAS_PERIPH_UART
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# Clock configuration
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select BOARD_HAS_HSE
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select BOARD_HAS_LSE
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source "$(RIOTBOARD)/common/stm32/Kconfig"
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@ -9,3 +9,6 @@ FEATURES_PROVIDED += periph_rtc
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FEATURES_PROVIDED += periph_spi
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FEATURES_PROVIDED += periph_timer
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FEATURES_PROVIDED += periph_uart
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# ublox-c030-u201 provides a custom default Kconfig clock configuration
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KCONFIG_ADD_CONFIG += $(RIOTBOARD)/ublox-c030-u201/clock.config
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5
boards/ublox-c030-u201/clock.config
Normal file
5
boards/ublox-c030-u201/clock.config
Normal file
@ -0,0 +1,5 @@
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# ublox-c030-u201 provides a 12MHz HSE so its needs a custom PLL config to
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# output a 180MHz clock.
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CONFIG_CUSTOM_PLL_PARAMS=y
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CONFIG_CLOCK_PLL_M=12
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CONFIG_CLOCK_PLL_N=360
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@ -1,3 +1,6 @@
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CPU_MODEL = stm32f401cc
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include $(RIOTBOARD)/common/weact-f4x1cx/Makefile.features
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# weact-f401cc provides a custom default Kconfig clock configuration
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KCONFIG_ADD_CONFIG += $(RIOTBOARD)/weact-f401cc/clock.config
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1
boards/weact-f401cc/clock.config
Normal file
1
boards/weact-f401cc/clock.config
Normal file
@ -0,0 +1 @@
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CONFIG_CLOCK_PLL_N=336
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@ -1,3 +1,6 @@
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CPU_MODEL = stm32f401ce
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include $(RIOTBOARD)/common/weact-f4x1cx/Makefile.features
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# weact-f401ce provides a custom default Kconfig clock configuration
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KCONFIG_ADD_CONFIG += $(RIOTBOARD)/weact-f401ce/clock.config
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1
boards/weact-f401ce/clock.config
Normal file
1
boards/weact-f401ce/clock.config
Normal file
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CONFIG_CLOCK_PLL_N=336
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@ -1,3 +1,6 @@
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CPU_MODEL = stm32f411ce
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include $(RIOTBOARD)/common/weact-f4x1cx/Makefile.features
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# weact-f411ce provides a custom default Kconfig clock configuration
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KCONFIG_ADD_CONFIG += $(RIOTBOARD)/weact-f411ce/clock.config
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1
boards/weact-f411ce/clock.config
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1
boards/weact-f411ce/clock.config
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CONFIG_CLOCK_PLL_N=192
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