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cpu/stm32f1: Use {} notation for empty while loops

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This commit is contained in:
Joakim Nohlgård 2016-02-11 14:20:26 +01:00
parent aba4e719eb
commit 96a7583c2a
4 changed files with 14 additions and 14 deletions
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6
cpu/stm32f1/cpu.c
View File

@ -60,7 +60,7 @@ static void clk_init(void)
RCC->CR |= ((uint32_t)RCC_CR_HSEON); RCC->CR |= ((uint32_t)RCC_CR_HSEON);
/* Wait till HSE is ready, /* Wait till HSE is ready,
* NOTE: the MCU will stay here forever if no HSE clock is connected */ * NOTE: the MCU will stay here forever if no HSE clock is connected */
while ((RCC->CR & RCC_CR_HSERDY) == 0); while ((RCC->CR & RCC_CR_HSERDY) == 0) {}
/* Enable Prefetch Buffer */ /* Enable Prefetch Buffer */
FLASH->ACR |= FLASH_ACR_PRFTBE; FLASH->ACR |= FLASH_ACR_PRFTBE;
/* Flash 2 wait state */ /* Flash 2 wait state */
@ -78,10 +78,10 @@ static void clk_init(void)
/* Enable PLL */ /* Enable PLL */
RCC->CR |= RCC_CR_PLLON; RCC->CR |= RCC_CR_PLLON;
/* Wait till PLL is ready */ /* Wait till PLL is ready */
while ((RCC->CR & RCC_CR_PLLRDY) == 0); while ((RCC->CR & RCC_CR_PLLRDY) == 0) {}
/* Select PLL as system clock source */ /* Select PLL as system clock source */
RCC->CFGR &= ~((uint32_t)(RCC_CFGR_SW)); RCC->CFGR &= ~((uint32_t)(RCC_CFGR_SW));
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
/* Wait till PLL is used as system clock source */ /* Wait till PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL); while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {}
} }

14
cpu/stm32f1/periph/rtt.c
View File

@ -96,7 +96,7 @@ void rtt_clear_overflow_cb(void)
uint32_t rtt_get_counter(void) uint32_t rtt_get_counter(void)
{ {
/* wait for syncronization */ /* wait for syncronization */
while (!(RTT_DEV->CRL & RTT_FLAG_RSF)); while (!(RTT_DEV->CRL & RTT_FLAG_RSF)) {}
return (((uint32_t)RTT_DEV->CNTH << 16 ) | (uint32_t)(RTT_DEV->CNTL)); return (((uint32_t)RTT_DEV->CNTH << 16 ) | (uint32_t)(RTT_DEV->CNTL));
} }
@ -116,7 +116,7 @@ void rtt_set_counter(uint32_t counter)
uint32_t rtt_get_alarm(void) uint32_t rtt_get_alarm(void)
{ {
/* wait for syncronization */ /* wait for syncronization */
while (!(RTT_DEV->CRL & RTT_FLAG_RSF)); while (!(RTT_DEV->CRL & RTT_FLAG_RSF)) {}
return (((uint32_t)RTT_DEV->ALRH << 16 ) | (uint32_t)(RTT_DEV->ALRL)); return (((uint32_t)RTT_DEV->ALRH << 16 ) | (uint32_t)(RTT_DEV->ALRL));
} }
@ -157,9 +157,9 @@ void rtt_poweron(void)
{ {
RCC->APB1ENR |= (RCC_APB1ENR_BKPEN|RCC_APB1ENR_PWREN); /* enable BKP and PWR, Clock */ RCC->APB1ENR |= (RCC_APB1ENR_BKPEN|RCC_APB1ENR_PWREN); /* enable BKP and PWR, Clock */
/* RTC clock source configuration */ /* RTC clock source configuration */
PWR->CR |= PWR_CR_DBP; /* Allow access to BKP Domain */ PWR->CR |= PWR_CR_DBP; /* Allow access to BKP Domain */
RCC->BDCR |= RCC_BDCR_LSEON; /* Enable LSE OSC */ RCC->BDCR |= RCC_BDCR_LSEON; /* Enable LSE OSC */
while(!(RCC->BDCR & RCC_BDCR_LSERDY)); /* Wait till LSE is ready */ while(!(RCC->BDCR & RCC_BDCR_LSERDY)) {} /* Wait till LSE is ready */
RCC->BDCR |= RCC_BDCR_RTCSEL_LSE; /* Select the RTC Clock Source */ RCC->BDCR |= RCC_BDCR_RTCSEL_LSE; /* Select the RTC Clock Source */
RCC->BDCR |= RCC_BDCR_RTCEN; /* enable RTC */ RCC->BDCR |= RCC_BDCR_RTCEN; /* enable RTC */
} }
@ -174,7 +174,7 @@ void rtt_poweroff(void)
inline void _rtt_enter_config_mode(void) inline void _rtt_enter_config_mode(void)
{ {
/* Loop until RTOFF flag is set */ /* Loop until RTOFF flag is set */
while (!(RTT_DEV->CRL & RTT_FLAG_RTOFF)); while (!(RTT_DEV->CRL & RTT_FLAG_RTOFF)) {}
/* enter configuration mode */ /* enter configuration mode */
RTT_DEV->CRL |= RTC_CRL_CNF; RTT_DEV->CRL |= RTC_CRL_CNF;
} }
@ -184,7 +184,7 @@ inline void _rtt_leave_config_mode(void)
/* leave configuration mode */ /* leave configuration mode */
RTT_DEV->CRL &= ~RTC_CRL_CNF; RTT_DEV->CRL &= ~RTC_CRL_CNF;
/* Loop until RTOFF flag is set */ /* Loop until RTOFF flag is set */
while (!(RTT_DEV->CRL & RTT_FLAG_RTOFF)); while (!(RTT_DEV->CRL & RTT_FLAG_RTOFF)) {}
} }
void RTT_ISR(void) void RTT_ISR(void)

6
cpu/stm32f1/periph/spi.c
View File

@ -210,11 +210,11 @@ int spi_transfer_byte(spi_t dev, char out, char *in)
return -1; return -1;
} }
while (!(spi->SR & SPI_SR_TXE)) ; while (!(spi->SR & SPI_SR_TXE)) {}
spi->DR = out; spi->DR = out;
transferred++; transferred++;
while (!(spi->SR & SPI_SR_RXNE)) ; while (!(spi->SR & SPI_SR_RXNE)) {}
if (in != NULL) { if (in != NULL) {
*in = spi->DR; *in = spi->DR;
transferred++; transferred++;
@ -224,7 +224,7 @@ int spi_transfer_byte(spi_t dev, char out, char *in)
} }
/* SPI busy */ /* SPI busy */
while ((spi->SR & 0x80)) ; while ((spi->SR & 0x80)) {}
#if ENABLE_DEBUG #if ENABLE_DEBUG
if (in != NULL) { if (in != NULL) {
DEBUG("\nout: %x in: %x transferred: %x\n", out, *in, transferred); DEBUG("\nout: %x in: %x transferred: %x\n", out, *in, transferred);

2
cpu/stm32f1/periph/uart.c
View File

@ -139,7 +139,7 @@ void uart_write(uart_t uart, const uint8_t *data, size_t len)
} }
for (size_t i = 0; i < len; i++) { for (size_t i = 0; i < len; i++) {
while (!(dev->SR & USART_SR_TXE)); while (!(dev->SR & USART_SR_TXE)) {}
dev->DR = data[i]; dev->DR = data[i];
} }
} }