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cpu/esp32: add ESP32-S3 support in peripheral drivers
This commit is contained in:
Gunar Schorcht
parent
55e1f88a60
commit
945a960fa7
@ -215,6 +215,8 @@ int adc_line_vref_to_gpio(adc_t line, gpio_t gpio)
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/* the GPIO for the output must be a channel of ADC2 */
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assert(_adc_hw[rtcio_out].adc_ctrl == ADC_UNIT_2);
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/* given ADC line has to be a channel of ADC2 */
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assert(_adc_hw[rtcio_vref].adc_ctrl == ADC_UNIT_2);
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esp_err_t res = ESP_OK;
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126
cpu/esp32/periph/adc_arch_esp32s3.c
Normal file
126
cpu/esp32/periph/adc_arch_esp32s3.c
Normal file
@ -0,0 +1,126 @@
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/*
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* Copyright (C) 2022 Gunar Schorcht
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_esp32
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* @{
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*
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* @file
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* @brief Architecture-specific ADC/DAC definitions for ESP32-S3 variant (family)
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*
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* @author Gunar Schorcht <gunar@schorcht.net>
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*
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* @}
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*/
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#include "board.h"
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#include "adc_arch_private.h"
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#include "esp_common.h"
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#include "soc/adc_channel.h"
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#define ENABLE_DEBUG 0
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#include "debug.h"
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/**
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* @brief ADC hardware descriptor table (for internal use only)
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*
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* Reference: Technical Reference Manual, Section 5.13 Table 5-5
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* https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf
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*
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* @note The index of entries in the table MUST correspond to the
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* RTCIO GPIO number.
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*/
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const _adc_hw_desc_t _adc_hw[] = {
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/* rtcio, gpio, adc_ctrl, adc_channel, pad_name */
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{ RTCIO_GPIO(0), GPIO0, ADC_UNIT_MAX, ADC_CHANNEL_MAX, "GPIO0" },
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{ RTCIO_GPIO(1), ADC1_CHANNEL_0_GPIO_NUM, ADC_UNIT_1, ADC_CHANNEL_0, "TOUCH1" },
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{ RTCIO_GPIO(2), ADC1_CHANNEL_1_GPIO_NUM, ADC_UNIT_1, ADC_CHANNEL_1, "TOUCH2" },
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{ RTCIO_GPIO(3), ADC1_CHANNEL_2_GPIO_NUM, ADC_UNIT_1, ADC_CHANNEL_2, "TOUCH3" },
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{ RTCIO_GPIO(4), ADC1_CHANNEL_3_GPIO_NUM, ADC_UNIT_1, ADC_CHANNEL_3, "TOUCH4" },
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{ RTCIO_GPIO(5), ADC1_CHANNEL_4_GPIO_NUM, ADC_UNIT_1, ADC_CHANNEL_4, "TOUCH5" },
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{ RTCIO_GPIO(6), ADC1_CHANNEL_5_GPIO_NUM, ADC_UNIT_1, ADC_CHANNEL_5, "TOUCH6" },
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{ RTCIO_GPIO(7), ADC1_CHANNEL_6_GPIO_NUM, ADC_UNIT_1, ADC_CHANNEL_6, "TOUCH7" },
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{ RTCIO_GPIO(8), ADC1_CHANNEL_7_GPIO_NUM, ADC_UNIT_1, ADC_CHANNEL_7, "TOUCH8" },
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{ RTCIO_GPIO(9), ADC1_CHANNEL_8_GPIO_NUM, ADC_UNIT_1, ADC_CHANNEL_8, "TOUCH9" },
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{ RTCIO_GPIO(10), ADC1_CHANNEL_9_GPIO_NUM, ADC_UNIT_1, ADC_CHANNEL_9, "TOUCH10" },
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{ RTCIO_GPIO(11), ADC2_CHANNEL_0_GPIO_NUM, ADC_UNIT_2, ADC_CHANNEL_0, "TOUCH11" },
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{ RTCIO_GPIO(12), ADC2_CHANNEL_1_GPIO_NUM, ADC_UNIT_2, ADC_CHANNEL_1, "TOUCH12" },
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{ RTCIO_GPIO(13), ADC2_CHANNEL_2_GPIO_NUM, ADC_UNIT_2, ADC_CHANNEL_2, "TOUCH13" },
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{ RTCIO_GPIO(14), ADC2_CHANNEL_3_GPIO_NUM, ADC_UNIT_2, ADC_CHANNEL_3, "TOUCH14" },
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{ RTCIO_GPIO(15), ADC2_CHANNEL_4_GPIO_NUM, ADC_UNIT_2, ADC_CHANNEL_4, "XTAL_32K_P" },
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{ RTCIO_GPIO(16), ADC2_CHANNEL_5_GPIO_NUM, ADC_UNIT_2, ADC_CHANNEL_5, "XTAL_32K_N" },
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{ RTCIO_GPIO(17), ADC2_CHANNEL_6_GPIO_NUM, ADC_UNIT_2, ADC_CHANNEL_6, "GPIO17" },
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{ RTCIO_GPIO(18), ADC2_CHANNEL_7_GPIO_NUM, ADC_UNIT_2, ADC_CHANNEL_7, "GPIO18" },
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{ RTCIO_GPIO(19), ADC2_CHANNEL_8_GPIO_NUM, ADC_UNIT_2, ADC_CHANNEL_8, "USB_D-" },
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{ RTCIO_GPIO(20), ADC2_CHANNEL_9_GPIO_NUM, ADC_UNIT_2, ADC_CHANNEL_9, "USB_D+" },
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{ RTCIO_GPIO(21), GPIO21, ADC_UNIT_MAX, ADC_CHANNEL_MAX, "GPIO21" },
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};
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/**
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* @brief GPIO to RTC IO map (for internal use only)
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*
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* Reference: Technical Reference Manual, Section 5.13 Table 5-5
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* https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf
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*/
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const gpio_t _gpio_rtcio_map[] = {
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RTCIO_GPIO(0), /* GPIO0 */
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RTCIO_GPIO(1), /* GPIO1 TOUCH1 */
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RTCIO_GPIO(2), /* GPIO2 TOUCH2 */
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RTCIO_GPIO(3), /* GPIO3 TOUCH3 */
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RTCIO_GPIO(4), /* GPIO4 TOUCH4 */
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RTCIO_GPIO(5), /* GPIO5 TOUCH5 */
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RTCIO_GPIO(6), /* GPIO6 TOUCH6 */
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RTCIO_GPIO(7), /* GPIO7 TOUCH7 */
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RTCIO_GPIO(8), /* GPIO8 TOUCH8 */
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RTCIO_GPIO(9), /* GPIO9 TOUCH9 */
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RTCIO_GPIO(10), /* GPIO10 TOUCH10 */
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RTCIO_GPIO(11), /* GPIO11 TOUCH11 */
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RTCIO_GPIO(12), /* GPIO12 TOUCH12 */
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RTCIO_GPIO(13), /* GPIO13 TOUCH13 */
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RTCIO_GPIO(14), /* GPIO14 TOUCH14 */
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RTCIO_GPIO(15), /* GPIO15 XTAL_32K_P */
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RTCIO_GPIO(16), /* GPIO16 XTAL_32K_N */
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RTCIO_GPIO(17), /* GPIO17 */
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RTCIO_GPIO(18), /* GPIO18 */
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RTCIO_GPIO(19), /* GPIO19 USB_D- */
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RTCIO_GPIO(20), /* GPIO20 USB_D+ */
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RTCIO_GPIO(21), /* GPIO21 */
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RTCIO_NA, /* GPIO22 */
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RTCIO_NA, /* GPIO23 */
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RTCIO_NA, /* GPIO24 */
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RTCIO_NA, /* GPIO25 */
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RTCIO_NA, /* GPIO26 */
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RTCIO_NA, /* GPIO27 */
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RTCIO_NA, /* GPIO28 */
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RTCIO_NA, /* GPIO29 */
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RTCIO_NA, /* GPIO30 */
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RTCIO_NA, /* GPIO31 */
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RTCIO_NA, /* GPIO32 */
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RTCIO_NA, /* GPIO33 */
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RTCIO_NA, /* GPIO34 */
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RTCIO_NA, /* GPIO35 */
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RTCIO_NA, /* GPIO36 */
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RTCIO_NA, /* GPIO37 */
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RTCIO_NA, /* GPIO38 */
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RTCIO_NA, /* GPIO39 */
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RTCIO_NA, /* GPIO40 */
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RTCIO_NA, /* GPIO41 */
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RTCIO_NA, /* GPIO42 */
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RTCIO_NA, /* GPIO43 */
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RTCIO_NA, /* GPIO44 */
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RTCIO_NA, /* GPIO45 */
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RTCIO_NA, /* GPIO46 */
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RTCIO_NA, /* GPIO47 */
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RTCIO_NA, /* GPIO48 */
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};
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_Static_assert(ARRAY_SIZE(_adc_hw) == SOC_RTCIO_PIN_COUNT,
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"size of _adc_hw does not match SOC_RTCIO_PIN_COUNT");
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_Static_assert(ARRAY_SIZE(_gpio_rtcio_map) == SOC_GPIO_PIN_COUNT,
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"size of _gpio_rtcio_map does not match SOC_GPIO_PIN_COUNT");
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@ -101,7 +101,7 @@ static bool _gpio_pin_pu[GPIO_PIN_NUMOF] = { };
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static bool _gpio_pin_pd[GPIO_PIN_NUMOF] = { };
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#endif
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#if defined(CPU_FAM_ESP32)
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#if defined(CPU_FAM_ESP32) || defined(CPU_FAM_ESP32S3)
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#define GPIO_IN_GET(b) (b < 32) ? GPIO.in & BIT(b) : GPIO.in1.val & BIT(b-32)
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#define GPIO_OUT_SET(b) if (b < 32) { GPIO.out_w1ts = BIT(b); } else { GPIO.out1_w1ts.val = BIT(b-32); }
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145
cpu/esp32/periph/gpio_arch_esp32s3.c
Normal file
145
cpu/esp32/periph/gpio_arch_esp32s3.c
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@ -0,0 +1,145 @@
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/*
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* Copyright (C) 2022 Gunar Schorcht
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_esp32
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* @ingroup drivers_periph_gpio
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* @{
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*
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* @file
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* @brief Architecture-specific GPIO definitions for ESP32-S3 variant (family)
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*
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* @author Gunar Schorcht <gunar@schorcht.net>
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* @}
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*/
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#include "gpio_arch.h"
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#include "soc/io_mux_reg.h"
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#if !IS_USED(MODULE_ESP_IDF_GPIO_HAL)
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/* GPIO to IOMUX register mapping (see Technical Reference, Section 5.14.2 Register Summary)
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https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf */
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const uint32_t _gpio_to_iomux_reg[GPIO_PIN_NUMOF] =
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{
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PERIPHS_IO_MUX_GPIO0_U, /* GPIO0 */
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PERIPHS_IO_MUX_GPIO1_U, /* GPIO1 */
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PERIPHS_IO_MUX_GPIO2_U, /* GPIO2 */
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PERIPHS_IO_MUX_GPIO3_U, /* GPIO3 */
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PERIPHS_IO_MUX_GPIO4_U, /* GPIO4 */
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PERIPHS_IO_MUX_GPIO5_U, /* GPIO5 */
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PERIPHS_IO_MUX_GPIO6_U, /* GPIO6 */
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PERIPHS_IO_MUX_GPIO7_U, /* GPIO7 */
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PERIPHS_IO_MUX_GPIO8_U, /* GPIO8 */
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PERIPHS_IO_MUX_GPIO9_U, /* GPIO9 */
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PERIPHS_IO_MUX_GPIO10_U, /* GPIO10 */
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PERIPHS_IO_MUX_GPIO11_U, /* GPIO11 */
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PERIPHS_IO_MUX_GPIO12_U, /* GPIO12 */
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PERIPHS_IO_MUX_GPIO13_U, /* GPIO13 */
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PERIPHS_IO_MUX_GPIO14_U, /* GPIO14 */
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PERIPHS_IO_MUX_XTAL_32K_P_U, /* GPIO15 used for 32k XTAL */
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PERIPHS_IO_MUX_XTAL_32K_N_U, /* GPIO16 used for 32k XTAL */
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PERIPHS_IO_MUX_DAC_1_U, /* GPIO17 */
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PERIPHS_IO_MUX_DAC_2_U, /* GPIO18 */
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PERIPHS_IO_MUX_GPIO19_U, /* GPIO19 */
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PERIPHS_IO_MUX_GPIO20_U, /* GPIO20 */
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PERIPHS_IO_MUX_GPIO21_U, /* GPIO21 */
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0, /* GPIO22 is not available */
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0, /* GPIO23 is not available */
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0, /* GPIO24 is not available */
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0, /* GPIO25 is not available */
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PERIPHS_IO_MUX_SPICS1_U, /* GPIO26 used as SPI CS1 */
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PERIPHS_IO_MUX_SPIHD_U, /* GPIO27 used as SPI HS for Flash */
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PERIPHS_IO_MUX_SPIWP_U, /* GPIO28 used as SPI WP for Flash */
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PERIPHS_IO_MUX_SPICS0_U, /* GPIO29 used as SPI CS0 for Flash */
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PERIPHS_IO_MUX_SPICLK_U, /* GPIO30 used as SPI CLK for Flash */
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PERIPHS_IO_MUX_SPID_U, /* GPIO31 used as SPI D for Flash */
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PERIPHS_IO_MUX_SPIQ_U, /* GPIO32 used as SPI Q for Flash */
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PERIPHS_IO_MUX_GPIO33_U, /* GPIO33 */
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PERIPHS_IO_MUX_GPIO34_U, /* GPIO34 */
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PERIPHS_IO_MUX_GPIO35_U, /* GPIO35 */
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PERIPHS_IO_MUX_GPIO36_U, /* GPIO36 */
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PERIPHS_IO_MUX_GPIO37_U, /* GPIO37 */
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PERIPHS_IO_MUX_GPIO38_U, /* GPIO38 */
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PERIPHS_IO_MUX_MTCK_U, /* GPIO39 used as JTAG*/
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PERIPHS_IO_MUX_MTDO_U, /* GPIO40 used as JTAG*/
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PERIPHS_IO_MUX_MTDI_U, /* GPIO41 used as JTAG*/
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PERIPHS_IO_MUX_MTMS_U, /* GPIO42 used as JTAG*/
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PERIPHS_IO_MUX_U0TXD_U, /* GPIO43 used as UART0 TxD */
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PERIPHS_IO_MUX_U0RXD_U, /* GPIO44 used as UART0 RxD */
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PERIPHS_IO_MUX_GPIO45_U, /* GPIO45 */
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PERIPHS_IO_MUX_GPIO46_U, /* GPIO46 */
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PERIPHS_IO_MUX_SPICLK_P_U, /* GPIO47 */
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PERIPHS_IO_MUX_SPICLK_N_U, /* GPIO48 */
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};
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#endif /* !IS_USED(MODULE_ESP_IDF_GPIO_HAL) */
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/* Table of the usage type of each GPIO pin */
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gpio_pin_usage_t _gpio_pin_usage[GPIO_PIN_NUMOF] = {
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_GPIO, /* GPIO0 */
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_GPIO, /* GPIO1 */
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_GPIO, /* GPIO2 */
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_GPIO, /* GPIO3 */
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_GPIO, /* GPIO4 */
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_GPIO, /* GPIO5 */
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_GPIO, /* GPIO6 */
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_GPIO, /* GPIO7 */
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_GPIO, /* GPIO8 */
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_GPIO, /* GPIO9 */
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_GPIO, /* GPIO10 */
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_GPIO, /* GPIO11 */
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_GPIO, /* GPIO12 */
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_GPIO, /* GPIO13 */
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_GPIO, /* GPIO14 */
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#if MODULE_ESP_RTC_TIMER_32K
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_NOT_EXIST, /* GPIO15 is used for external 32K crystal */
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_NOT_EXIST, /* GPIO16 is used for external 32K crystal */
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#else
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_GPIO, /* GPIO15 */
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_GPIO, /* GPIO16 */
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#endif
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_GPIO, /* GPIO17 */
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_GPIO, /* GPIO18 */
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_GPIO, /* GPIO19 could be used for ESP USB/builtin USB2JTAG bridge */
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_GPIO, /* GPIO20 could be used for ESP USB/builtin USB2JTAG bridge */
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_GPIO, /* GPIO21 */
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_NOT_EXIST, /* GPIO22 does not exist */
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_NOT_EXIST, /* GPIO23 does not exist */
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_NOT_EXIST, /* GPIO24 does not exist */
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_NOT_EXIST, /* GPIO25 does not exist */
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_NOT_EXIST, /* GPIO26 is used as direct I/O SPI CS1 for Flash/PSRAM */
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#if defined(FLASH_MODE_QIO) || defined(FLASH_MODE_QOUT)
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_SPIF, /* GPIO27 is used as direct I/O SPI HD for Flash/PSRAM */
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_SPIF, /* GPIO28 is used as direct I/O SPI WP for Flash/PSRAM */
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#else
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_GPIO, /* GPIO27 */
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_GPIO, /* GPIO28 */
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#endif
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_SPIF, /* GPIO29 is used as direct I/O SPI CS0 for Flash/PSRAM */
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_SPIF, /* GPIO30 is used as direct I/O SPI CLK for Flash/PSRAM */
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_SPIF, /* GPIO31 is used as direct I/O SPI Q for Flash/PSRAM */
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_SPIF, /* GPIO32 is used as direct I/O SPI D for Flash/PSRAM */
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_GPIO, /* GPIO33 */
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_GPIO, /* GPIO34 */
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_GPIO, /* GPIO35 */
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_GPIO, /* GPIO36 */
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_GPIO, /* GPIO37 */
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_GPIO, /* GPIO38 */
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_GPIO, /* GPIO39 */
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_GPIO, /* GPIO40 */
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_GPIO, /* GPIO41 */
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_GPIO, /* GPIO42 */
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_UART, /* GPIO43 is used as direct I/O UART0 TxD */
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_UART, /* GPIO44 is used as direct I/O UART0 RxD */
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_GPIO, /* GPIO45 */
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_GPIO, /* GPIO46 */
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_GPIO, /* GPIO47 */
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_GPIO, /* GPIO48 */
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};
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@ -147,7 +147,7 @@ void i2c_init(i2c_t dev)
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cfg.scl_io_num = i2c_config[dev].scl;
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cfg.sda_pullup_en = i2c_config[dev].sda_pullup;
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cfg.scl_pullup_en = i2c_config[dev].scl_pullup;
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#if SOC_I2C_SUPPORT_RTC
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#if defined(SOC_I2C_SUPPORT_RTC) && !defined(CPU_FAM_ESP32S3)
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cfg.clk_flags = I2C_SCLK_SRC_FLAG_LIGHT_SLEEP;
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#endif
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@ -105,7 +105,7 @@ uint64_t _rtc_get_counter(void)
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}
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/* read the time from 48-bit counter and return */
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return (((uint64_t)RTCCNTL.time1.val) << 32) + RTCCNTL.time0;
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#elif defined(CPU_FAM_ESP32C3)
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#elif defined(CPU_FAM_ESP32C3) || defined(CPU_FAM_ESP32S3)
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/* read the time from 48-bit counter and return */
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return (((uint64_t)RTCCNTL.time_high0.val) << 32) + RTCCNTL.time_low0;
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#else
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@ -274,10 +274,10 @@ void IRAM_ATTR spi_acquire(spi_t bus, spi_cs_t cs, spi_mode_t mode, spi_clk_t cl
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spi_ll_master_set_clock_by_reg(_spi[bus].periph->hw,
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&_spi[bus].timing.clock_reg);
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#if defined(CPU_FAM_ESP32C3)
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#if defined(CPU_FAM_ESP32C3) || defined(CPU_FAM_ESP32S3)
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/*
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* If the SPI mode has been changed, the clock signal is only set to the
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* correct level at the beginning of the transfer on the ESP32C3. However,
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* correct level at the beginning of the transfer on the ESP32x3. However,
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* if a generic GPIO is used as CS signal instead of the hardware CS,
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* the CS signal is already LOW at this time. Thus, the clock signal will
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* have the wrong level when the SPI mode is changed and the CS signal
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@ -312,6 +312,8 @@ void IRAM_ATTR spi_release(spi_t bus)
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static const char* _spi_names[] = { "CSPI/FSPI", "HSPI", "VSPI" };
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#elif defined(CPU_FAM_ESP32C3)
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static const char* _spi_names[] = { "SPI", "FSPI" };
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#elif defined(CPU_FAM_ESP32S3)
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static const char* _spi_names[] = { "SPI", "FSPI", "SPI" };
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#else
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#error Platform implementation required
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#endif
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@ -96,6 +96,11 @@
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#define HW_TIMER_CORRECTION 10
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#define HW_TIMER_DELTA_MIN (MAX(HW_TIMER_CORRECTION << 1, 5))
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#elif defined(CPU_FAM_ESP32S3)
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#define HW_TIMER_CORRECTION (RTC_PLL_320M / CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ)
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#define HW_TIMER_DELTA_MIN (MAX(HW_TIMER_CORRECTION << 1, 5))
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#else
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#error "MCU implementation needed"
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#endif
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@ -121,7 +126,7 @@ struct _hw_timer_desc_t {
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static const struct _hw_timer_desc_t _timers_desc[] =
|
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{
|
||||
#if defined(CPU_FAM_ESP32)
|
||||
#if defined(CPU_FAM_ESP32) || defined(CPU_FAM_ESP32S3)
|
||||
{
|
||||
.module = PERIPH_TIMG0_MODULE,
|
||||
.group = TIMER_GROUP_0,
|
||||
@ -389,12 +394,25 @@ void IRAM_ATTR timer_stop(tim_t dev)
|
||||
#define HW_TIMER_DELTA_RSHIFT 24
|
||||
#define HW_TIMER_FREQUENCY (1000000UL) /* only 1MHz is supported */
|
||||
|
||||
#if defined(CPU_FAM_ESP32)
|
||||
|
||||
#define HW_TIMER_CORRECTION (RTC_PLL_480M / CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ)
|
||||
#define HW_TIMER_DELTA_MIN (MAX(HW_TIMER_CORRECTION, 5))
|
||||
|
||||
#elif defined(CPU_FAM_ESP32S3)
|
||||
|
||||
#define HW_TIMER_CORRECTION (RTC_PLL_480M / CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ)
|
||||
#define HW_TIMER_DELTA_MIN (MAX(HW_TIMER_CORRECTION, 5))
|
||||
|
||||
#else
|
||||
#error "MCU implementation needed"
|
||||
#endif
|
||||
|
||||
#define US_TO_HW_TIMER_TICKS(t) (t * system_get_cpu_freq())
|
||||
#define HW_TIMER_TICKS_TO_US(t) (t / system_get_cpu_freq())
|
||||
|
||||
extern int esp_clk_cpu_freq(void);
|
||||
|
||||
struct hw_channel_t {
|
||||
bool used; /* indicates whether the channel is used */
|
||||
uint32_t start_time; /* physical time when the timer channel has been started */
|
||||
|
||||
@ -59,7 +59,7 @@
|
||||
#define I2C_CLOCK_STRETCH 200
|
||||
|
||||
/* gpio access macros */
|
||||
#if defined(CPU_FAM_ESP32)
|
||||
#if defined(CPU_FAM_ESP32) || defined(CPU_FAM_ESP32S3)
|
||||
#define GPIO_SET(lo, hi, b) if (b < 32) { GPIO.lo = BIT(b); } else { GPIO.hi.val = BIT(b-32); }
|
||||
#define GPIO_GET(lo, hi, b) ((b < 32) ? GPIO.lo & BIT(b) : GPIO.hi.val & BIT(b-32))
|
||||
#elif defined(CPU_FAM_ESP32C3)
|
||||
@ -119,6 +119,8 @@ static _i2c_bus_t _i2c_bus[I2C_NUMOF] = {};
|
||||
#define I2C_CLK_CAL 62 /* clock calibration offset */
|
||||
#elif defined(CPU_FAM_ESP32C3)
|
||||
#define I2C_CLK_CAL 32 /* clock calibration offset */
|
||||
#elif defined(CPU_FAM_ESP32S3)
|
||||
#define I2C_CLK_CAL 82 /* clock calibration offset */
|
||||
#elif defined(MCU_ESP8266)
|
||||
#define I2C_CLK_CAL 47 /* clock calibration offset */
|
||||
#else
|
||||
|
||||
@ -66,6 +66,7 @@
|
||||
#include "soc/gpio_struct.h"
|
||||
#include "soc/periph_defs.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "soc/soc_caps.h"
|
||||
#include "soc/uart_reg.h"
|
||||
#include "soc/uart_struct.h"
|
||||
|
||||
@ -106,9 +107,11 @@ static struct uart_hw_t _uarts[] = {
|
||||
.signal_txd = U0TXD_OUT_IDX,
|
||||
.signal_rxd = U0RXD_IN_IDX,
|
||||
.int_src = ETS_UART0_INTR_SOURCE
|
||||
#endif /* !MCU_ESP8266 */
|
||||
#endif /* !definedMCU_ESP8266 */
|
||||
},
|
||||
#if defined(UART1_TXD) || !defined(MCU_ESP8266)
|
||||
|
||||
#if !defined(MCU_ESP8266)
|
||||
#if defined(UART1_TXD) && defined(UART1_RXD) && (SOC_UART_NUM > 1)
|
||||
{
|
||||
.regs = &UART1,
|
||||
.used = false,
|
||||
@ -116,15 +119,14 @@ static struct uart_hw_t _uarts[] = {
|
||||
.data = UART_DATA_BITS_8,
|
||||
.stop = UART_STOP_BITS_1,
|
||||
.parity = UART_PARITY_NONE,
|
||||
#if !defined(MCU_ESP8266)
|
||||
.mod = PERIPH_UART1_MODULE,
|
||||
.signal_txd = U1TXD_OUT_IDX,
|
||||
.signal_rxd = U1RXD_IN_IDX,
|
||||
.int_src = ETS_UART1_INTR_SOURCE
|
||||
#endif /* !MCU_ESP8266 */
|
||||
},
|
||||
#endif /* defined(UART1_TXD) || !defined(MCU_ESP8266) */
|
||||
#if defined(CPU_FAM_ESP32)
|
||||
#endif /* defined(UART1_TXD) && defined(UART1_RXD) && (SOC_UART_NUM > 1) */
|
||||
|
||||
#if defined(UART2_TXD) && defined(UART2_RXD) && (SOC_UART_NUM > 2)
|
||||
{
|
||||
.regs = &UART2,
|
||||
.used = false,
|
||||
@ -137,7 +139,8 @@ static struct uart_hw_t _uarts[] = {
|
||||
.signal_rxd = U2RXD_IN_IDX,
|
||||
.int_src = ETS_UART2_INTR_SOURCE
|
||||
},
|
||||
#endif /* defined(CPU_FAM_ESP32) */
|
||||
#endif /* defined(UART2_TXD) && defined(UART2_RXD) && (SOC_UART_NUM > 2) */
|
||||
#endif /* !defined(MCU_ESP8266) */
|
||||
};
|
||||
|
||||
/* declaration of external functions */
|
||||
@ -162,8 +165,8 @@ int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
|
||||
assert(uart < UART_NUMOF);
|
||||
|
||||
/* UART1 and UART2 have configurable pins */
|
||||
if ((UART_NUMOF > 0 && uart == UART_DEV(1)) ||
|
||||
(UART_NUMOF > 1 && uart == UART_DEV(2))) {
|
||||
if ((UART_NUMOF > 1 && uart == UART_DEV(1)) ||
|
||||
(UART_NUMOF > 2 && uart == UART_DEV(2))) {
|
||||
|
||||
/* reset the pins when they were already used as UART pins */
|
||||
if (gpio_get_pin_usage(uart_config[uart].txd) == _UART) {
|
||||
@ -287,7 +290,11 @@ static void IRAM _uart_intr_handler(void *arg)
|
||||
DEBUG("%s uart=%d int_st=%08x\n", __func__,
|
||||
uart, (unsigned)_uarts[uart].regs->int_st.val);
|
||||
|
||||
#ifdef CPU_FAM_ESP32S3
|
||||
if (_uarts[uart].used && _uarts[uart].regs->int_st.rxfifo_full_int_st) {
|
||||
#else
|
||||
if (_uarts[uart].used && _uarts[uart].regs->int_st.rxfifo_full) {
|
||||
#endif
|
||||
/* read one byte of data */
|
||||
uint8_t data = _uart_rx_one_char(uart);
|
||||
/* if registered, call the RX callback function */
|
||||
@ -295,7 +302,11 @@ static void IRAM _uart_intr_handler(void *arg)
|
||||
_uarts[uart].isr_ctx.rx_cb(_uarts[uart].isr_ctx.arg, data);
|
||||
}
|
||||
/* clear interrupt flag */
|
||||
#ifdef CPU_FAM_ESP32S3
|
||||
_uarts[uart].regs->int_clr.rxfifo_full_int_clr = 1;
|
||||
#else
|
||||
_uarts[uart].regs->int_clr.rxfifo_full = 1;
|
||||
#endif
|
||||
}
|
||||
|
||||
/* TODO handle other types of interrupts, for the moment just clear them */
|
||||
@ -325,6 +336,9 @@ static uint8_t IRAM _uart_rx_one_char(uart_t uart)
|
||||
#if defined(CPU_FAM_ESP32) || defined(MCU_ESP8266)
|
||||
/* read the lowest byte from RX FIFO register */
|
||||
return _uarts[uart].regs->fifo.rw_byte;
|
||||
#elif defined(CPU_FAM_ESP32S3)
|
||||
/* read the lowest byte from RX FIFO register */
|
||||
return _uarts[uart].regs->fifo.rxfifo_rd_byte;
|
||||
#else
|
||||
/* read the lowest byte from RX FIFO register */
|
||||
return _uarts[uart].regs->ahb_fifo.rw_byte;
|
||||
@ -353,8 +367,13 @@ static void _uart_tx_one_char(uart_t uart, uint8_t data)
|
||||
|
||||
static void _uart_intr_enable(uart_t uart)
|
||||
{
|
||||
#ifdef CPU_FAM_ESP32S3
|
||||
_uarts[uart].regs->int_ena.rxfifo_full_int_ena = 1;
|
||||
_uarts[uart].regs->int_clr.rxfifo_full_int_clr = 1;
|
||||
#else
|
||||
_uarts[uart].regs->int_ena.rxfifo_full = 1;
|
||||
_uarts[uart].regs->int_clr.rxfifo_full = 1;
|
||||
#endif
|
||||
_uarts[uart].used = true;
|
||||
|
||||
DEBUG("%s %08x\n", __func__, (unsigned)_uarts[uart].regs->int_ena.val);
|
||||
@ -433,13 +452,18 @@ static int _uart_set_baudrate(uart_t uart, uint32_t baudrate)
|
||||
/* use APB_CLK */
|
||||
_uarts[uart].regs->conf0.tick_ref_always_on = 1;
|
||||
#endif
|
||||
#ifdef CPU_FAM_ESP32C3
|
||||
#if defined(CPU_FAM_ESP32C3) || defined(CPU_FAM_ESP32S3)
|
||||
_uarts[uart].regs->clk_conf.sclk_sel = 1; /* APB clock used instead of XTAL */
|
||||
#endif
|
||||
/* compute and set the integral and the decimal part */
|
||||
uint32_t clk_div = (UART_CLK_FREQ << 4) / _uarts[uart].baudrate;
|
||||
#ifdef CPU_FAM_ESP32S3
|
||||
_uarts[uart].regs->clkdiv.clkdiv = clk_div >> 4;
|
||||
_uarts[uart].regs->clkdiv.clkdiv_frag = clk_div & 0xf;
|
||||
#else
|
||||
_uarts[uart].regs->clk_div.div_int = clk_div >> 4;
|
||||
_uarts[uart].regs->clk_div.div_frag = clk_div & 0xf;
|
||||
#endif /* CPU_FAM_ESP32S3 */
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user