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Merge #19412
19412: cpu/stm32/periph: Add GPIO LL IRQ support for STM32F1 r=gschorcht a=maribu ### Contribution description As the title says ### Testing procedure <details><summary><code>make BOARD=nucleo-f103rb flash test-with-config -C tests/periph_gpio_ll</code></summary> ``` make: Entering directory '/home/maribu/Repos/software/RIOT/tests/periph_gpio_ll' Building application "tests_periph_gpio_ll" for "nucleo-f103rb" with MCU "stm32". "make" -C /home/maribu/Repos/software/RIOT/boards/common/init "make" -C /home/maribu/Repos/software/RIOT/boards/nucleo-f103rb "make" -C /home/maribu/Repos/software/RIOT/boards/common/nucleo "make" -C /home/maribu/Repos/software/RIOT/core "make" -C /home/maribu/Repos/software/RIOT/core/lib "make" -C /home/maribu/Repos/software/RIOT/cpu/stm32 "make" -C /home/maribu/Repos/software/RIOT/cpu/cortexm_common "make" -C /home/maribu/Repos/software/RIOT/cpu/cortexm_common/periph "make" -C /home/maribu/Repos/software/RIOT/cpu/stm32/periph "make" -C /home/maribu/Repos/software/RIOT/cpu/stm32/stmclk "make" -C /home/maribu/Repos/software/RIOT/cpu/stm32/vectors "make" -C /home/maribu/Repos/software/RIOT/drivers "make" -C /home/maribu/Repos/software/RIOT/drivers/periph_common "make" -C /home/maribu/Repos/software/RIOT/sys "make" -C /home/maribu/Repos/software/RIOT/sys/auto_init "make" -C /home/maribu/Repos/software/RIOT/sys/div "make" -C /home/maribu/Repos/software/RIOT/sys/frac "make" -C /home/maribu/Repos/software/RIOT/sys/isrpipe "make" -C /home/maribu/Repos/software/RIOT/sys/libc "make" -C /home/maribu/Repos/software/RIOT/sys/malloc_thread_safe "make" -C /home/maribu/Repos/software/RIOT/sys/newlib_syscalls_default "make" -C /home/maribu/Repos/software/RIOT/sys/pm_layered "make" -C /home/maribu/Repos/software/RIOT/sys/preprocessor "make" -C /home/maribu/Repos/software/RIOT/sys/stdio_uart "make" -C /home/maribu/Repos/software/RIOT/sys/test_utils/interactive_sync "make" -C /home/maribu/Repos/software/RIOT/sys/test_utils/print_stack_usage "make" -C /home/maribu/Repos/software/RIOT/sys/tsrb "make" -C /home/maribu/Repos/software/RIOT/sys/ztimer text data bss dec hex filename 20760 176 2728 23664 5c70 /home/maribu/Repos/software/RIOT/tests/periph_gpio_ll/bin/nucleo-f103rb/tests_periph_gpio_ll.elf /home/maribu/Repos/software/RIOT/dist/tools/openocd/openocd.sh flash /home/maribu/Repos/software/RIOT/tests/periph_gpio_ll/bin/nucleo-f103rb/tests_periph_gpio_ll.elf ### Flashing Target ### Open On-Chip Debugger 0.12.0+dev-snapshot (2023-03-13-08:56) Licensed under GNU GPL v2 For bug reports, read http://openocd.org/doc/doxygen/bugs.html DEPRECATED! use 'adapter serial' not 'hla_serial' hla_swd Info : The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD srst_only separate srst_nogate srst_open_drain connect_assert_srst Info : clock speed 1000 kHz Info : STLINK V2J29M18 (API v2) VID:PID 0483:374B Info : Target voltage: 3.252984 Info : [stm32f1x.cpu] Cortex-M3 r1p1 processor detected Info : [stm32f1x.cpu] target has 6 breakpoints, 4 watchpoints Info : starting gdb server for stm32f1x.cpu on 0 Info : Listening on port 32843 for gdb connections TargetName Type Endian TapName State -- ------------------ ---------- ------ ------------------ ------------ 0* stm32f1x.cpu hla_target little stm32f1x.cpu unknown [stm32f1x.cpu] halted due to debug-request, current mode: Thread xPSR: 0x01000000 pc: 0x08001ae4 msp: 0x20000200 Info : device id = 0x20036410 Info : flash size = 128 KiB Warn : Adding extra erase range, 0x080051c8 .. 0x080053ff auto erase enabled wrote 20936 bytes from file /home/maribu/Repos/software/RIOT/tests/periph_gpio_ll/bin/nucleo-f103rb/tests_periph_gpio_ll.elf in 1.192543s (17.144 KiB/s) verified 20936 bytes in 0.333379s (61.328 KiB/s) shutdown command invoked Done flashing r /home/maribu/Repos/software/RIOT/dist/tools/pyterm/pyterm -p "/dev/ttyACM1" -b "115200" --no-reconnect --noprefix --no-repeat-command-on-empty-line Connect to serial port /dev/ttyACM1 Welcome to pyterm! Type '/exit' to exit. READY s START main(): This is RIOT! (Version: 2023.04-devel-685-gd0d5d-cpu/stm32/periph/gpio_ll_irq) Test / Hardware Details: ======================== Cabling: (INPUT -- OUTPUT) P2.10 (PC10) -- P1.8 (PB8) P2.12 (PC12) -- P1.9 (PB9) Number of pull resistor values supported: 1 Number of drive strengths supported: 1 Number of slew rates supported: 4 Valid GPIO ports: - PORT 0 (PORT A) - PORT 1 (PORT B) - PORT 2 (PORT C) - PORT 3 (PORT D) - PORT 4 (PORT E) Testing gpio_port_pack_addr() ============================= All OK Testing gpip_ng_init() ====================== Testing is_gpio_port_num_valid() is true for PORT_OUT and PORT_IN: Testing input configurations for PIN_IN_0: Support for input with pull up: yes state: in, pull: up, schmitt trigger: off, value: on Support for input with pull down: yes state: in, pull: down, schmitt trigger: off, value: off Support for input with pull to bus level: no Support for floating input (no pull resistors): yes state: in, pull: none, schmitt trigger: off, value: off Testing output configurations for PIN_OUT_0: Support for output (push-pull) with initial value of LOW: yes state: out-pp, slew: slowest, value: off Output is indeed LOW: yes state: out-pp, slew: slowest, value: on Output can be pushed HIGH: yes Support for output (push-pull) with initial value of HIGH: yes state: out-pp, slew: slowest, value: on Output is indeed HIGH: yes Support for output (open drain with pull up) with initial value of LOW: no Support for output (open drain with pull up) with initial value of HIGH: no Support for output (open drain) with initial value of LOW: yes state: out-od, slew: slowest, pull: none, schmitt trigger: off, value: off Output is indeed LOW: yes Support for output (open drain) with initial value of HIGH: yes state: out-od, slew: slowest, pull: none, schmitt trigger: off, value: on state: in, pull: down, schmitt trigger: off, value: off Output can indeed be pulled LOW: yes state: in, pull: up, schmitt trigger: off, value: on Output can indeed be pulled HIGH: yes Support for output (open source) with initial value of LOW: no Support for output (open source) with initial value of HIGH: no Support for output (open source with pull up) with initial value of HIGH: no Support for output (open source with pull up) with initial value of LOW: no Support for disconnecting GPIO: yes Output can indeed be pulled LOW: yes Output can indeed be pulled HIGH: yes Testing Reading/Writing GPIO Ports ================================== testing initial value of 0 after init ...OK testing setting both outputs_optional simultaneously ...OK testing clearing both outputs_optional simultaneously ...OK testing toggling first output (0 --> 1) ...OK testing toggling first output (1 --> 0) ...OK testing toggling second output (0 --> 1) ...OK testing toggling second output (1 --> 0) ...OK testing setting first output and clearing second with write ...OK testing setting second output and clearing first with write ...OK All input/output operations worked as expected Testing External IRQs ===================== Testing rising edge on PIN_IN_0 ... OK Testing falling edge on PIN_IN_0 ... OK Testing both edges on PIN_IN_0 ... OK Testing masking of IRQs (still both edges on PIN_IN_0) ... OK Testing level-triggered on HIGH on PIN_IN_0 (when input is LOW when setting up IRQ) ... OK Testing level-triggered on HIGH on PIN_IN_0 (when input is HIGH when setting up IRQ) ... OK Testing level-triggered on LOW on PIN_IN_0 (when input is HIGH when setting up IRQ) ... OK Testing level-triggered on LOW on PIN_IN_0 (when input is LOW when setting up IRQ) ... OK TEST SUCCEEDED ``` </details> ### Issues/PRs references Depends on https://github.com/RIOT-OS/RIOT/pull/19407 Co-authored-by: Marian Buschsieweke <marian.buschsieweke@ovgu.de>
This commit is contained in:
bors[bot]
GitHub
commit
9405bf7a26
@ -12,12 +12,9 @@ FEATURES_PROVIDED += periph_rtt_overflow
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FEATURES_PROVIDED += periph_uart_modecfg
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FEATURES_PROVIDED += periph_uart_nonblocking
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FEATURES_PROVIDED += periph_gpio_ll
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ifneq ($(CPU_FAM),f1)
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FEATURES_PROVIDED += periph_gpio_ll_irq
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FEATURES_PROVIDED += periph_gpio_ll_irq_level_triggered_high
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FEATURES_PROVIDED += periph_gpio_ll_irq_level_triggered_low
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endif
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FEATURES_PROVIDED += periph_gpio_ll_irq
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FEATURES_PROVIDED += periph_gpio_ll_irq_level_triggered_high
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FEATURES_PROVIDED += periph_gpio_ll_irq_level_triggered_low
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ifneq (,$(filter $(CPU_FAM),f0 f1 f3 g0 g4 l0 l1 l4 l5 u5 wb wl))
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FEATURES_PROVIDED += periph_flashpage
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@ -17,6 +17,9 @@ config CPU_FAM_F1
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select HAS_PERIPH_FLASHPAGE_PAGEWISE
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select HAS_PERIPH_FLASHPAGE_RAW
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select HAS_PERIPH_GPIO_LL
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select HAS_PERIPH_GPIO_LL_IRQ
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select HAS_PERIPH_GPIO_LL_IRQ_LEVEL_TRIGGERED_HIGH
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select HAS_PERIPH_GPIO_LL_IRQ_LEVEL_TRIGGERED_LOW
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select HAS_PERIPH_RTT_SET_COUNTER
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select HAS_PERIPH_WDT
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select HAVE_SHARED_PERIPH_RTT_PERIPH_RTC
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@ -41,43 +41,87 @@
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#define EXTI_MASK (0xFFFF)
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#if defined(EXTI_SWIER_SWI0) || defined(EXTI_SWIER_SWIER0)
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#define EXTI_REG_SWIER (EXTI->SWIER)
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# define EXTI_REG_SWIER (EXTI->SWIER)
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#endif
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#if defined(EXTI_SWIER1_SWI0) || defined(EXTI_SWIER1_SWIER0)
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#define EXTI_REG_SWIER (EXTI->SWIER1)
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# define EXTI_REG_SWIER (EXTI->SWIER1)
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#endif
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#if defined(EXTI_RTSR_RT0) || defined(EXTI_RTSR_TR0)
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#define EXTI_REG_RTSR (EXTI->RTSR)
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# define EXTI_REG_RTSR (EXTI->RTSR)
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#endif
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#if defined(EXTI_RTSR1_RT0) || defined(EXTI_RTSR1_TR0)
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#define EXTI_REG_RTSR (EXTI->RTSR1)
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# define EXTI_REG_RTSR (EXTI->RTSR1)
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#endif
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#if defined(EXTI_FTSR_FT0) || defined(EXTI_FTSR_TR0)
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#define EXTI_REG_FTSR (EXTI->FTSR)
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# define EXTI_REG_FTSR (EXTI->FTSR)
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#endif
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#if defined(EXTI_FTSR1_FT0) || defined (EXTI_FTSR1_TR0)
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#define EXTI_REG_FTSR (EXTI->FTSR1)
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# define EXTI_REG_FTSR (EXTI->FTSR1)
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#endif
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#ifdef EXTI_PR_PR0
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#define EXTI_REG_PR (EXTI->PR)
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#endif
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#ifdef EXTI_PR1_PIF0
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#define EXTI_REG_PR (EXTI->PR1)
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#if defined(EXTI_PR_PR0)
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# define EXTI_REG_PR (EXTI->PR)
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#elif defined(EXTI_PR1_PIF0)
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# define EXTI_REG_PR (EXTI->PR1)
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#else
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# define EXTI_REG_FPR (EXTI->FPR1)
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# define EXTI_REG_RPR (EXTI->RPR1)
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#endif
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#if defined(EXTI_C2_BASE)
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# define EXTI_REG_IMR (EXTI_C2->IMR1)
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# define EXTI_REG_IMR (EXTI_C2->IMR1)
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#elif defined(EXTI_IMR_IM0)
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# define EXTI_REG_IMR (EXTI->IMR)
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# define EXTI_REG_IMR (EXTI->IMR)
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#elif defined(EXTI_IMR1_IM0)
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# define EXTI_REG_IMR (EXTI->IMR1)
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# define EXTI_REG_IMR (EXTI->IMR1)
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#endif
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#ifdef RCC_APB2ENR_SYSCFGCOMPEN
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# define SYSFG_CLOCK APB2
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# define SYSFG_ENABLE_MASK RCC_APB2ENR_SYSCFGCOMPEN
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#endif
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#ifdef RCC_APBENR2_SYSCFGEN
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# define SYSFG_ENABLE_MASK RCC_APBENR2_SYSCFGEN
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# ifdef APB12
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# define SYSFG_CLOCK APB12
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# else
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# define SYSFG_CLOCK APB2
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# endif
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#endif
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#ifdef RCC_APB3ENR_SYSCFGEN
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# define SYSFG_CLOCK APB3
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# define SYSFG_ENABLE_MASK RCC_APB3ENR_SYSCFGEN
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#endif
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#ifdef EXTI_EXTICR1_EXTI0
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# define EXTICR_REG(num) (EXTI->EXTICR[(num) >> 2])
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#endif
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#ifdef SYSCFG_EXTICR1_EXTI0
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# define EXTICR_REG(num) (SYSCFG->EXTICR[(num) >> 2])
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#endif
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#ifdef AFIO_EXTICR1_EXTI0
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# define EXTICR_REG(num) (AFIO->EXTICR[(num) >> 2])
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#endif
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#ifdef SYSCFG_EXTICR1_EXTI1_Pos
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# define EXTICR_FIELD_SIZE SYSCFG_EXTICR1_EXTI1_Pos
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#endif
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#ifdef EXTI_EXTICR1_EXTI1_Pos
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# define EXTICR_FIELD_SIZE EXTI_EXTICR1_EXTI1_Pos
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#endif
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#ifdef AFIO_EXTICR1_EXTI1_Pos
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# define EXTICR_FIELD_SIZE AFIO_EXTICR1_EXTI1_Pos
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#endif
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void gpio_ll_irq_mask(gpio_port_t port, uint8_t pin)
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@ -102,6 +146,8 @@ static uint16_t level_triggered;
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static IRQn_Type get_irqn(uint8_t pin)
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{
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/* TODO: Come up with a way that this doesn't need updates whenever a new
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* MCU family gets added */
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#if defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5)
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return EXTI0_IRQn + pin;
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#elif defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32L0) || \
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@ -155,48 +201,29 @@ static IRQn_Type get_irqn(uint8_t pin)
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static void clear_pending_irqs(uint8_t pin)
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{
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#if defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) || \
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defined(CPU_FAM_STM32U5) || defined(CPU_FAM_STM32MP1)
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/* clear any pending requests */
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EXTI->RPR1 = (1 << pin);
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EXTI->FPR1 = (1 << pin);
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#ifdef EXTI_REG_PR
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/* same IRQ flag no matter if falling or rising edge detected */
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EXTI_REG_PR = (1U << pin);
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#else
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/* clear any pending requests */
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EXTI_REG_PR = (1 << pin);
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/* distinct IRQ flags for falling and rising edge, clearing both */
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EXTI_REG_FPR = (1U << pin);
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EXTI_REG_RPR = (1U << pin);
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#endif
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}
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static void set_exti_port(uint8_t exti_num, uint8_t port_num)
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{
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#if defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) || \
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defined(CPU_FAM_STM32U5)
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/* enable specific pin as exti sources */
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EXTI->EXTICR[exti_num >> 2] &= ~(0xf << ((exti_num & 0x03) * 8));
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EXTI->EXTICR[exti_num >> 2] |= (port_num << ((exti_num & 0x03) * 8));
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#elif defined(CPU_FAM_STM32MP1)
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/* enable specific pin as exti sources */
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EXTI->EXTICR[exti_num >> 2] &= ~(0xf << ((exti_num & 0x03) * 4));
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EXTI->EXTICR[exti_num >> 2] |= (port_num << ((exti_num & 0x03) * 4));
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#else
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/* enable specific pin as exti sources */
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SYSCFG->EXTICR[exti_num >> 2] &= ~(0xf << ((exti_num & 0x03) * 4));
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SYSCFG->EXTICR[exti_num >> 2] |= (port_num << ((exti_num & 0x03) * 4));
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#endif
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uint32_t tmp = EXTICR_REG(exti_num);
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tmp &= ~(0xf << ((exti_num & 0x03) * EXTICR_FIELD_SIZE));
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tmp |= (port_num << ((exti_num & 0x03) * EXTICR_FIELD_SIZE));
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EXTICR_REG(exti_num) = tmp;
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}
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static uint8_t get_exti_port(uint8_t exti_num)
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{
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#if defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) || \
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defined(CPU_FAM_STM32U5)
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/* enable specific pin as exti sources */
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return 0xf & (EXTI->EXTICR[exti_num >> 2] >> ((exti_num & 0x03) * 8));
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#elif defined(CPU_FAM_STM32MP1)
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/* enable specific pin as exti sources */
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return 0xf & (EXTI->EXTICR[exti_num >> 2] >> ((exti_num & 0x03) * 4));
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#else
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/* enable specific pin as exti sources */
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return 0xf & (SYSCFG->EXTICR[exti_num >> 2] >> ((exti_num & 0x03) * 4));
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#endif
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uint32_t reg = EXTICR_REG(exti_num);
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reg >>= (exti_num & 0x03) * EXTICR_FIELD_SIZE;
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return reg & 0xf;
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}
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int gpio_ll_irq(gpio_port_t port, uint8_t pin, gpio_irq_trig_t trig, gpio_ll_cb_t cb, void *arg)
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@ -209,17 +236,8 @@ int gpio_ll_irq(gpio_port_t port, uint8_t pin, gpio_irq_trig_t trig, gpio_ll_cb_
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isr_ctx[pin].arg = arg;
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/* enable clock of the SYSCFG module for EXTI configuration */
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#if !defined(CPU_FAM_STM32WB) && !defined(CPU_FAM_STM32MP1) && \
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!defined(CPU_FAM_STM32WL)
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#ifdef CPU_FAM_STM32F0
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periph_clk_en(APB2, RCC_APB2ENR_SYSCFGCOMPEN);
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#elif defined(CPU_FAM_STM32G0)
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periph_clk_en(APB12, RCC_APBENR2_SYSCFGEN);
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#elif defined(CPU_FAM_STM32U5)
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periph_clk_en(APB3, RCC_APB3ENR_SYSCFGEN);
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#else
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periph_clk_en(APB2, RCC_APB2ENR_SYSCFGEN);
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#endif
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#ifdef SYSFG_CLOCK
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periph_clk_en(SYSFG_CLOCK, SYSFG_ENABLE_MASK);
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#endif
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/* enable global pin interrupt */
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@ -262,30 +280,35 @@ int gpio_ll_irq(gpio_port_t port, uint8_t pin, gpio_irq_trig_t trig, gpio_ll_cb_
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return 0;
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}
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void isr_exti(void)
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static uint32_t get_and_clear_pending_irqs(void)
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{
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#if defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) || \
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defined(CPU_FAM_STM32U5) || defined(CPU_FAM_STM32MP1)
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/* get all interrupts handled by this ISR */
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uint32_t pending_rising_isr = (EXTI->RPR1 & EXTI_MASK);
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uint32_t pending_falling_isr = (EXTI->FPR1 & EXTI_MASK);
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#ifdef EXTI_REG_PR
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/* only one pending IRQ flag register for both falling and rising flanks */
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uint32_t pending_isr = (EXTI_REG_PR & EXTI_MASK);
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/* clear by writing a 1 */
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EXTI_REG_PR = pending_isr;
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return pending_isr;
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#else
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/* distinct registers for pending IRQ flags depending on rising or falling
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* flank */
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uint32_t pending_rising_isr = (EXTI_REG_RPR & EXTI_MASK);
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uint32_t pending_falling_isr = (EXTI_REG_FPR & EXTI_MASK);
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/* clear by writing a 1 */
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EXTI->RPR1 = pending_rising_isr;
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EXTI->FPR1 = pending_falling_isr;
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/* only generate interrupts against lines which have their IMR set */
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uint32_t pending_isr = (pending_rising_isr | pending_falling_isr) & EXTI_REG_IMR;
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#else
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/* read all pending interrupts wired to isr_exti */
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uint32_t pending_isr = (EXTI_REG_PR & EXTI_MASK);
|
||||
return pending_rising_isr | pending_falling_isr;
|
||||
#endif
|
||||
}
|
||||
|
||||
/* clear by writing a 1 */
|
||||
EXTI_REG_PR = pending_isr;
|
||||
void isr_exti(void)
|
||||
{
|
||||
uint32_t pending_isr = get_and_clear_pending_irqs();
|
||||
|
||||
/* only generate soft interrupts against lines which have their IMR set */
|
||||
pending_isr &= EXTI_REG_IMR;
|
||||
#endif
|
||||
|
||||
/* iterate over all set bits */
|
||||
uint8_t pin = 0;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user