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Merge pull request #1456 from haukepetersen/board_stm32f3discovery

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board/cpu: Added support for the stm32f3discovery board and stm32f3 cpu
This commit is contained in:
Hauke Petersen 2014-07-31 23:55:05 +02:00
commit 938c61a5a2
33 changed files with 10037 additions and 15 deletions
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4
boards/stm32f3discovery/Makefile Normal file
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# tell the Makefile.base which module to build
MODULE = $(BOARD)_base
include $(RIOTBASE)/Makefile.base

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boards/stm32f3discovery/Makefile.include Normal file
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# define the cpu used by the stm32f3-discovery board
export CPU = stm32f3
export CPU_MODEL = stm32f303vc
#define the default port depending on the host OS
OS := $(shell uname)
ifeq ($(OS),Linux)
PORT ?= /dev/ttyUSB0
else ifeq ($(OS),Darwin)
PORT ?= $(shell ls -1 /dev/tty.SLAB_USBtoUART* | head -n 1)
else
$(info CAUTION: No flash tool for your host system found!)
# TODO: add support for windows as host platform
endif
export PORT
# define tools used for building the project
export PREFIX = arm-none-eabi-
export CC = $(PREFIX)gcc
export AR = $(PREFIX)ar
export AS = $(PREFIX)as
export LINK = $(PREFIX)gcc
export SIZE = $(PREFIX)size
export OBJCOPY = $(PREFIX)objcopy
export TERMPROG = $(RIOTBASE)/dist/tools/pyterm/pyterm.py
export FLASHER = st-flash
export DEBUGGER = $(RIOTBOARD)/$(BOARD)/dist/debug.sh
# define build specific options
CPU_USAGE = -mcpu=cortex-m4
FPU_USAGE = -mfloat-abi=hard -mfpu=fpv4-sp-d16
export CFLAGS += -ggdb -g3 -std=gnu99 -Os -Wall -Wstrict-prototypes $(CPU_USAGE) $(FPU_USAGE) -mlittle-endian -mthumb -mthumb-interwork -nostartfiles
export CFLAGS += -ffunction-sections -fdata-sections -fno-builtin
export ASFLAGS += -ggdb -g3 $(CPU_USAGE) $(FPU_USAGE) -mlittle-endian
export LINKFLAGS += -g3 -ggdb -std=gnu99 $(CPU_USAGE) $(FPU_USAGE) -mlittle-endian -static -lgcc -mthumb -mthumb-interwork -nostartfiles
export LINKFLAGS += -T$(LINKERSCRIPT)
export OFLAGS = -O binary
export FFLAGS = write bin/$(BOARD)/$(APPLICATION).hex 0x8000000
export DEBUGGER_FLAGS = $(RIOTBOARD)/$(BOARD)/dist/gdb.conf $(BINDIR)/$(APPLICATION).elf
# use newLib nano-specs if available
ifeq ($(shell $(LINK) -specs=nano.specs -E - 2>/dev/null >/dev/null </dev/null ; echo $$?),0)
export LINKFLAGS += -specs=nano.specs -lc -lnosys
endif
# export board specific includes to the global includes-listing
export INCLUDES += -I$(RIOTBOARD)/$(BOARD)/include

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boards/stm32f3discovery/board.c Normal file
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/*
* Copyright (C) 2014 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup board_stm32f3discovery
* @{
*
* @file
* @brief Board specific implementations for the STM32F3Discovery evaluation board
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
* @}
*/
#include "board.h"
static void leds_init(void);
void board_init(void)
{
/* initialize the boards LEDs */
leds_init();
/* initialize the CPU */
cpu_init();
}
/**
* @brief Initialize the boards on-board LEDs (LD3 to LD10)
*
* The LED initialization is hard-coded in this function. As the LEDs are soldered
* onto the board they are fixed to their CPU pins.
*
* The LEDs are connected to the following pins:
* - LD3: PE9
* - LD4: PE8
* - LD5: PE10
* - LD6: PE15
* - LD7: PE11
* - LD8: PE14
* - LD9: PE12
* - LD10: PE13
*/
static void leds_init(void)
{
/* enable clock for port GPIOE */
RCC->AHBENR |= RCC_AHBENR_GPIOEEN;
/* set output speed to 50MHz */
LED_PORT->OSPEEDR |= 0xffff0000;
/* set output type to push-pull */
LED_PORT->OTYPER &= ~(0x0000ff00);
/* configure pins as general outputs */
LED_PORT->MODER &= ~(0xffff0000);
LED_PORT->MODER |= 0x55550000;
/* disable pull resistors */
LED_PORT->PUPDR &= ~(0xffff0000);
/* turn all LEDs off */
LED_PORT->BRR = 0xff00;
}

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boards/stm32f3discovery/dist/debug.sh vendored Executable file
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#!/bin/sh
echo "Debugging $1"
arm-none-eabi-gdb -tui -command=$1 $2

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boards/stm32f3discovery/dist/gdb.conf vendored Normal file
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tar extended-remote :4242

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boards/stm32f3discovery/include/board.h Normal file
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/*
* Copyright (C) 2014 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @defgroup board_stm32f3discovery STM32F3Discovery
* @ingroup boards
* @brief Board specific files for the STM32F3Discovery board
* @{
*
* @file
* @brief Board specific definitions for the STM32F3Discovery evaluation board
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*/
#ifndef __BOARD_H
#define __BOARD_H
#include "cpu.h"
/**
* Define the nominal CPU core clock in this board
*/
#define F_CPU (72000000UL)
/**
* @name Assign the hardware timer
*/
#define HW_TIMER TIMER_0
/**
* @name Define the UART used for stdio
* @{
*/
#define STDIO UART_0
#define STDIO_BAUDRATE (115200U)
#define STDIO_BUFSIZE (64U)
/** @} */
/**
* @name LED pin definitions
* @{
*/
#define LED_PORT GPIOE
#define LD3_PIN (1 << 9)
#define LD4_PIN (1 << 8)
#define LD5_PIN (1 << 10)
#define LD6_PIN (1 << 15)
#define LD7_PIN (1 << 11)
#define LD8_PIN (1 << 14)
#define LD9_PIN (1 << 12)
#define LD10_PIN (1 << 13)
/** @} */
/**
* @name Macros for controlling the on-board LEDs.
* @{
*/
#define LD3_ON (LED_PORT->BSRRL = LD3_PIN)
#define LD3_OFF (LED_PORT->BSRRH = LD3_PIN)
#define LD3_TOGGLE (LED_PORT->ODR ^= LD3_PIN)
#define LD4_ON (LED_PORT->BSRRL = LD4_PIN)
#define LD4_OFF (LED_PORT->BSRRH = LD4_PIN)
#define LD4_TOGGLE (LED_PORT->ODR ^= LD4_PIN)
#define LD5_ON (LED_PORT->BSRRL = LD5_PIN)
#define LD5_OFF (LED_PORT->BSRRH = LD5_PIN)
#define LD5_TOGGLE (LED_PORT->ODR ^= LD5_PIN)
#define LD6_ON (LED_PORT->BSRRL = LD6_PIN)
#define LD6_OFF (LED_PORT->BSRRH = LD6_PIN)
#define LD6_TOGGLE (LED_PORT->ODR ^= LD6_PIN)
#define LD7_ON (LED_PORT->BSRRL = LD7_PIN)
#define LD7_OFF (LED_PORT->BSRRH = LD7_PIN)
#define LD7_TOGGLE (LED_PORT->ODR ^= LD7_PIN)
#define LD8_ON (LED_PORT->BSRRL = LD8_PIN)
#define LD8_OFF (LED_PORT->BSRRH = LD8_PIN)
#define LD8_TOGGLE (LED_PORT->ODR ^= LD8_PIN)
#define LD9_ON (LED_PORT->BSRRL = LD9_PIN)
#define LD9_OFF (LED_PORT->BSRRH = LD9_PIN)
#define LD9_TOGGLE (LED_PORT->ODR ^= LD9_PIN)
#define LD10_ON (LED_PORT->BSRRL = LD10_PIN)
#define LD10_OFF (LED_PORT->BSRRH = LD10_PIN)
#define LD10_TOGGLE (LED_PORT->ODR ^= LD10_PIN)
/* for compatability to other boards */
#define LED_GREEN_ON LD4_ON
#define LED_GREEN_OFF LD4_OFF
#define LED_GREEN_TOGGLE LD4_TOGGLE
#define LED_RED_ON LD5_ON
#define LED_RED_OFF LD5_OFF
#define LED_RED_TOGGLE LD5_TOGGLE
/** @} */
/**
* @brief Initialize board specific hardware, including clock, LEDs and std-IO
*/
void board_init(void);
#endif /** __BOARD_H */
/** @} */

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boards/stm32f3discovery/include/periph_conf.h Normal file
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/*
* Copyright (C) 2014 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup board_stm32f3discovery
* @{
*
* @file
* @brief Peripheral MCU configuration for the STM32F3discovery board
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*/
#ifndef __PERIPH_CONF_H
#define __PERIPH_CONF_H
/**
* @name Clock system configuration
* @{
*/
#define CLOCK_HSE (8000000U) /* external oscillator */
#define CLOCK_CORECLOCK (72000000U) /* desired core clock frequency */
/* the actual PLL values are automatically generated */
#define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSE)
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_1
/** @} */
/**
* @brief Timer configuration
* @{
*/
#define TIMER_NUMOF (1U)
#define TIMER_0_EN 1
#define TIMER_IRQ_PRIO 1
/* Timer 0 configuration */
#define TIMER_0_DEV TIM2
#define TIMER_0_CHANNELS 4
#define TIMER_0_PRESCALER (71U)
#define TIMER_0_MAX_VALUE (0xffffffff)
#define TIMER_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_TIM2EN)
#define TIMER_0_ISR isr_tim2
#define TIMER_0_IRQ_CHAN TIM2_IRQn
/** @} */
/**
* @brief UART configuration
* @{
*/
#define UART_NUMOF (3U)
#define UART_0_EN 1
#define UART_1_EN 1
#define UART_2_EN 1
#define UART_IRQ_PRIO 1
/* UART 0 device configuration */
#define UART_0_DEV USART1
#define UART_0_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_USART1EN)
#define UART_0_CLK (CLOCK_CORECLOCK / 1) /* UART clock runs with 72MHz (F_CPU / 1) */
#define UART_0_IRQ_CHAN USART1_IRQn
#define UART_0_ISR isr_usart1
/* UART 0 pin configuration */
#define UART_0_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
#define UART_0_PORT GPIOA
#define UART_0_TX_PIN 9
#define UART_0_RX_PIN 10
#define UART_0_AF 7
/* UART 1 device configuration */
#define UART_1_DEV USART2
#define UART_1_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_USART2EN)
#define UART_1_CLK (CLOCK_CORECLOCK / 2) /* UART clock runs with 36MHz (F_CPU / 2) */
#define UART_1_IRQ_CHAN USART2_IRQn
#define UART_1_ISR isr_usart2
/* UART 1 pin configuration */
#define UART_1_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIODEN)
#define UART_1_PORT GPIOD
#define UART_1_TX_PIN 5
#define UART_1_RX_PIN 6
#define UART_1_AF 7
/* UART 1 device configuration */
#define UART_2_DEV USART3
#define UART_2_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_USART3EN)
#define UART_2_CLK (CLOCK_CORECLOCK / 2) /* UART clock runs with 36MHz (F_CPU / 2) */
#define UART_2_IRQ_CHAN USART3_IRQn
#define UART_2_ISR isr_usart3
/* UART 1 pin configuration */
#define UART_2_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIODEN)
#define UART_2_PORT GPIOD
#define UART_2_TX_PIN 8
#define UART_2_RX_PIN 9
#define UART_2_AF 7
/** @} */
/**
* @brief GPIO configuration
* @{
*/
#define GPIO_NUMOF 12
#define GPIO_0_EN 1
#define GPIO_1_EN 1
#define GPIO_2_EN 1
#define GPIO_3_EN 1
#define GPIO_4_EN 1
#define GPIO_5_EN 1
#define GPIO_6_EN 1
#define GPIO_7_EN 1
#define GPIO_8_EN 1
#define GPIO_9_EN 1
#define GPIO_10_EN 1
#define GPIO_11_EN 1
#define GPIO_IRQ_PRIO 1
/* IRQ config */
#define GPIO_IRQ_0 GPIO_11 /* alternatively GPIO_4 could be used here */
#define GPIO_IRQ_1 GPIO_5
#define GPIO_IRQ_2 GPIO_0
#define GPIO_IRQ_3 GPIO_3
#define GPIO_IRQ_4 GPIO_1
#define GPIO_IRQ_5 GPIO_2
#define GPIO_IRQ_6 (-1) /* not configured */
#define GPIO_IRQ_7 (-1) /* not configured */
#define GPIO_IRQ_8 (-1) /* not configured */
#define GPIO_IRQ_9 (-1) /* not configured */
#define GPIO_IRQ_10 (-1) /* not configured */
#define GPIO_IRQ_11 GPIO_6
#define GPIO_IRQ_12 GPIO_7
#define GPIO_IRQ_13 GPIO_8
#define GPIO_IRQ_14 GPIO_9
#define GPIO_IRQ_15 GPIO_10
/* GPIO channel 0 config */
#define GPIO_0_PORT GPIOE /* LSM303DLHC -> DRDY */
#define GPIO_0_PIN 2
#define GPIO_0_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOEEN)
#define GPIO_0_EXTI_CFG1() (SYSCFG->EXTICR[0] &= ~(SYSCFG_EXTICR1_EXTI2))
#define GPIO_0_EXTI_CFG2() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI2_PE)
#define GPIO_0_IRQ EXTI2_TSC_IRQn
/* GPIO channel 1 config */
#define GPIO_1_PORT GPIOE /* LSM303DLHC -> INT1 */
#define GPIO_1_PIN 4
#define GPIO_1_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOEEN)
#define GPIO_1_EXTI_CFG1() (SYSCFG->EXTICR[1] &= ~(SYSCFG_EXTICR2_EXTI4))
#define GPIO_1_EXTI_CFG2() (SYSCFG->EXTICR[1] |= SYSCFG_EXTICR2_EXTI4_PE)
#define GPIO_1_IRQ EXTI4_IRQn
/* GPIO channel 2 config */
#define GPIO_2_PORT GPIOE /* LSM303DLHC -> INT2 */
#define GPIO_2_PIN 5
#define GPIO_2_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOEEN)
#define GPIO_2_EXTI_CFG1() (SYSCFG->EXTICR[1] &= ~(SYSCFG_EXTICR2_EXTI5))
#define GPIO_2_EXTI_CFG2() (SYSCFG->EXTICR[1] |= SYSCFG_EXTICR2_EXTI5_PE)
#define GPIO_2_IRQ EXTI9_5_IRQn
/* GPIO channel 3 config */
#define GPIO_3_PORT GPIOE /* L2GD20 -> CS */
#define GPIO_3_PIN 3
#define GPIO_3_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOEEN)
#define GPIO_3_EXTI_CFG1() (SYSCFG->EXTICR[0] &= ~(SYSCFG_EXTICR1_EXTI3))
#define GPIO_3_EXTI_CFG2() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI3_PE)
#define GPIO_3_IRQ EXTI3_IRQn
/* GPIO channel 4 config */
#define GPIO_4_PORT GPIOE /* L2GD20 -> INT1 */
#define GPIO_4_PIN 0
#define GPIO_4_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOEEN)
#define GPIO_4_EXTI_CFG1() (SYSCFG->EXTICR[0] &= ~(SYSCFG_EXTICR1_EXTI0))
#define GPIO_4_EXTI_CFG2() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI0_PE)
#define GPIO_4_IRQ EXTI0_IRQn
/* GPIO channel 5 config */
#define GPIO_5_PORT GPIOE /* L2GD20 -> INT2/DRDY */
#define GPIO_5_PIN 1
#define GPIO_5_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOEEN)
#define GPIO_5_EXTI_CFG1() (SYSCFG->EXTICR[0] &= ~(SYSCFG_EXTICR1_EXTI1))
#define GPIO_5_EXTI_CFG2() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI1_PE)
#define GPIO_5_IRQ EXTI1_IRQn
/* GPIO channel 6 config */
#define GPIO_6_PORT GPIOB
#define GPIO_6_PIN 11
#define GPIO_6_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOBEN)
#define GPIO_6_EXTI_CFG1() (SYSCFG->EXTICR[2] &= ~(SYSCFG_EXTICR3_EXTI11))
#define GPIO_6_EXTI_CFG2() (SYSCFG->EXTICR[2] |= SYSCFG_EXTICR3_EXTI11_PB)
#define GPIO_6_IRQ EXTI15_10_IRQn
/* GPIO channel 7 config */
#define GPIO_7_PORT GPIOB
#define GPIO_7_PIN 12
#define GPIO_7_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOBEN)
#define GPIO_7_EXTI_CFG1() (SYSCFG->EXTICR[3] &= ~(SYSCFG_EXTICR4_EXTI12))
#define GPIO_7_EXTI_CFG2() (SYSCFG->EXTICR[3] |= SYSCFG_EXTICR4_EXTI12_PB)
#define GPIO_7_IRQ EXTI15_10_IRQn
/* GPIO channel 8 config */
#define GPIO_8_PORT GPIOB
#define GPIO_8_PIN 13
#define GPIO_8_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOBEN)
#define GPIO_8_EXTI_CFG1() (SYSCFG->EXTICR[3] &= ~(SYSCFG_EXTICR4_EXTI13))
#define GPIO_8_EXTI_CFG2() (SYSCFG->EXTICR[3] |= SYSCFG_EXTICR4_EXTI13_PB)
#define GPIO_8_IRQ EXTI15_10_IRQn
/* GPIO channel 9 config */
#define GPIO_9_PORT GPIOB
#define GPIO_9_PIN 14
#define GPIO_9_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOBEN)
#define GPIO_9_EXTI_CFG1() (SYSCFG->EXTICR[3] &= ~(SYSCFG_EXTICR4_EXTI14))
#define GPIO_9_EXTI_CFG2() (SYSCFG->EXTICR[3] |= SYSCFG_EXTICR4_EXTI14_PB)
#define GPIO_9_IRQ EXTI15_10_IRQn
/* GPIO channel 10 config */
#define GPIO_10_PORT GPIOB
#define GPIO_10_PIN 15
#define GPIO_10_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOBEN)
#define GPIO_10_EXTI_CFG1() (SYSCFG->EXTICR[3] &= ~(SYSCFG_EXTICR4_EXTI15))
#define GPIO_10_EXTI_CFG2() (SYSCFG->EXTICR[3] |= SYSCFG_EXTICR4_EXTI15_PB)
#define GPIO_10_IRQ EXTI15_10_IRQn
/* GPIO channel 11 config */
#define GPIO_11_PORT GPIOA /* User button 1 */
#define GPIO_11_PIN 0
#define GPIO_11_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
#define GPIO_11_EXTI_CFG1() (SYSCFG->EXTICR[0] &= ~(SYSCFG_EXTICR1_EXTI0))
#define GPIO_11_EXTI_CFG2() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI0_PA)
#define GPIO_11_IRQ EXTI0_IRQn
/** @} */
#endif /* __PERIPH_CONF_H */

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cpu/cortex-m4_common/thread_arch.c
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@ -141,13 +141,6 @@ void thread_arch_stack_print(void)
__attribute__((naked)) void NORETURN thread_arch_start_threading(void)
{
/* switch to user mode use PSP instead of MSP in ISR Mode*/
CONTROL_Type mode;
mode.w = __get_CONTROL();
mode.b.SPSEL = 1; /* select PSP */
mode.b.nPRIV = 0; /* privilege */
__set_CONTROL(mode.w);
/* enable IRQs to make sure the SVC interrupt is reachable */
enableIRQ();

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cpu/stm32f3/Makefile Normal file
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# define the module that is build
MODULE = cpu
# add a list of subdirectories, that should also be build
DIRS = periph $(CORTEX_M4_COMMON)
include $(RIOTBASE)/Makefile.base

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cpu/stm32f3/Makefile.include Normal file
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# this CPU implementation is using the explicit core/CPU interface
export CFLAGS += -DCOREIF_NG=1
# export the peripheral drivers to be linked into the final binary
export USEMODULE += periph
# this CPU implementation makes use of the ringbuffer, so include the lib module
export USEMODULE += lib
# tell the build system that the CPU depends on the Cortex-M common files
export USEMODULE += cortex-m4_common
# define path to cortex-m common module, which is needed for this CPU
export CORTEX_M4_COMMON = $(RIOTCPU)/cortex-m4_common/
# CPU depends on the cortex-m common module, so include it
include $(CORTEX_M4_COMMON)Makefile.include
# define the linker script to use for this CPU
export LINKERSCRIPT = $(RIOTCPU)/$(CPU)/$(CPU_MODEL)_linkerscript.ld
#export the CPU model
MODEL = $(shell echo $(CPU_MODEL)|tr 'a-z' 'A-Z')
export CFLAGS += -DCPU_MODEL_$(MODEL)
# include CPU specific includes
export INCLUDES += -I$(RIOTCPU)/$(CPU)/include
# add the CPU specific system calls implementations for the linker
export UNDEF += $(BINDIR)cpu/syscalls.o
export UNDEF += $(BINDIR)cpu/startup.o

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cpu/stm32f3/cpu.c Normal file
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/*
* Copyright (C) 2014 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_stm32f3
* @{
*
* @file
* @brief Implementation of the CPU initialization
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @}
*/
#include <stdint.h>
#include "cpu.h"
#include "periph_conf.h"
/**
* @name Pattern to write into the Coprocessor Access Control Register to allow full FPU access
*/
#define FULL_FPU_ACCESS (0x00f00000)
static void cpu_clock_init(void);
/**
* @brief Initialize the CPU, set IRQ priorities
*/
void cpu_init(void)
{
/* give full access to the FPU */
SCB->CPACR |= (uint32_t)FULL_FPU_ACCESS;
/* configure the vector table location to internal flash */
SCB->VTOR = FLASH_BASE;
/* initialize the clock system */
cpu_clock_init();
/* set pendSV interrupt to lowest possible priority */
NVIC_SetPriority(PendSV_IRQn, 0xff);
}
/**
* @brief Configure the controllers clock system
*
* The clock initialization make the following assumptions:
* - the external HSE clock from an external oscillator is used as base clock
* - the internal PLL circuit is used for clock refinement
*
* The actual used values are specified in the board's `periph_conf.h` file.
*
* NOTE: currently there is not timeout for initialization of PLL and other locks
* -> when wrong values are chosen, the initialization could stall
*/
static void cpu_clock_init(void)
{
/* configure the HSE clock */
/* enable the HSI clock */
RCC->CR |= RCC_CR_HSION;
/* reset clock configuration register */
RCC->CFGR = 0;
/* disable HSE, CSS and PLL */
RCC->CR &= ~(RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON | RCC_CR_PLLON);
/* disable all clock interrupts */
RCC->CIR = 0;
/* enable the HSE clock */
RCC->CR |= RCC_CR_HSEON;
/* wait for HSE to be ready */
while (!(RCC->CR & RCC_CR_HSERDY));
/* setup the peripheral bus prescalers */
/* set the AHB clock divider */
RCC->CFGR &= ~RCC_CFGR_HPRE;
RCC->CFGR |= CLOCK_AHB_DIV;
/* set the APB2 (high speed) bus clock divider */
RCC->CFGR &= ~RCC_CFGR_PPRE2;
RCC->CFGR |= CLOCK_APB2_DIV;
/* set the APB1 (low speed) bus clock divider */
RCC->CFGR &= ~RCC_CFGR_PPRE1;
RCC->CFGR |= CLOCK_APB1_DIV;
/* configure the PLL */
/* reset PLL configuration */
RCC->CFGR &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMUL);
/* set PLL to use HSE clock with prescaler 1 as input */
RCC->CFGR |= RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 |
(((CLOCK_PLL_MUL - 2) & 0xf) << 18);
/* enable PLL again */
RCC->CR |= RCC_CR_PLLON;
/* wait until PLL is stable */
while(!(RCC->CR & RCC_CR_PLLRDY));
/* configure flash latency */
/* reset flash access control register */
FLASH->ACR = 0;
/* enable pre-fetch buffer */
FLASH->ACR |= FLASH_ACR_PRFTBE;
/* set flash latency */
FLASH->ACR &= ~FLASH_ACR_LATENCY;
FLASH->ACR |= CLOCK_FLASH_LATENCY;
/* configure the sysclock and the peripheral clocks */
/* set sysclock to be driven by the PLL clock */
RCC->CFGR &= ~RCC_CFGR_SW;
RCC->CFGR |= RCC_CFGR_SW_PLL;
/* wait for sysclock to be stable */
while (!(RCC->CFGR & RCC_CFGR_SWS_PLL));
}

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/*
* Copyright (C) 2014 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_stm32f3
* @{
*
* @file
* @brief Implementation of the kernels hwtimer interface
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
* @}
*/
#include "arch/hwtimer_arch.h"
#include "board.h"
#include "periph/timer.h"
#include "thread.h"
void irq_handler(int channel);
void (*timeout_handler)(int);
void hwtimer_arch_init(void (*handler)(int), uint32_t fcpu)
{
timeout_handler = handler;
timer_init(HW_TIMER, 1, &irq_handler);
}
void hwtimer_arch_enable_interrupt(void)
{
timer_irq_enable(HW_TIMER);
}
void hwtimer_arch_disable_interrupt(void)
{
timer_irq_disable(HW_TIMER);
}
void hwtimer_arch_set(unsigned long offset, short timer)
{
timer_set(HW_TIMER, timer, offset);
}
void hwtimer_arch_set_absolute(unsigned long value, short timer)
{
timer_set_absolute(HW_TIMER, timer, value);
}
void hwtimer_arch_unset(short timer)
{
timer_clear(HW_TIMER, timer);
}
unsigned long hwtimer_arch_now(void)
{
return timer_read(HW_TIMER);
}
void irq_handler(int channel)
{
timeout_handler((short)(channel));
}

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/*
* Copyright (C) 2014 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @defgroup cpu_stm32f3 STM32F3
* @ingroup cpu
* @brief CPU specific implementations for the STM32F3
* @{
*
* @file
* @brief Implementation specific CPU configuration options
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*/
#ifndef __CPU_CONF_H
#define __CPU_CONF_H
#ifdef CPU_MODEL_STM32F303VC
#include "stm32f303xc.h"
#endif
/**
* @name Kernel configuration
*
* TODO: measure and adjust for the Cortex-M4f
* @{
*/
#define KERNEL_CONF_STACKSIZE_PRINTF (1024)
#ifndef KERNEL_CONF_STACKSIZE_DEFAULT
#define KERNEL_CONF_STACKSIZE_DEFAULT (1024)
#endif
#define KERNEL_CONF_STACKSIZE_IDLE (256)
/** @} */
/**
* @name UART0 buffer size definition for compatibility reasons
*
* TODO: remove once the remodeling of the uart0 driver is done
* @{
*/
#ifndef UART0_BUFSIZE
#define UART0_BUFSIZE (128)
#endif
/** @} */
#endif /* __CPU_CONF_H */
/** @} */

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/*
* Copyright (C) 2014 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_stm32f3
* @{
*
* @file
* @brief CPU specific hwtimer configuration options
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*/
#ifndef __HWTIMER_CPU_H
#define __HWTIMER_CPU_H
/**
* @name Hardware timer configuration
* @{
*/
#define HWTIMER_MAXTIMERS 4 /**< the CPU implementation supports 4 HW timers */
#define HWTIMER_SPEED 1000000 /**< the HW timer runs with 1MHz */
#define HWTIMER_MAXTICKS (0xFFFFFFFF) /**< 32-bit timer */
/** @} */
#endif /* __HWTIMER_CPU_H */
/** @} */

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/*
* Copyright (C) 2014 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_stm32f3
* @{
*
* @file
* @brief Implementation of the kernel's architecture dependent IO interface
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
* @}
*/
#include "board.h"
#include "arch/io_arch.h"
#include "periph/uart.h"
int io_arch_puts(char *data, int size)
{
int i = 0;
for (; i < size; i++) {
uart_write_blocking(STDIO, data[i]);
}
return i;
}

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/*
* Copyright (C) 2014 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_stm32f3
* @{
*
* @file
* @brief Implementation of the kernels power management interface
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
* @}
*/
#include "arch/lpm_arch.h"
void lpm_arch_init(void)
{
/* TODO */
}
enum lpm_mode lpm_arch_set(enum lpm_mode target)
{
/* TODO */
return 0;
}
enum lpm_mode lpm_arch_get(void)
{
/* TODO */
return 0;
}
void lpm_arch_awake(void)
{
/* TODO */
}
void lpm_arch_begin_awake(void)
{
/* TODO */
}
void lpm_arch_end_awake(void)
{
/* TODO */
}

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MODULE = periph
include $(RIOTBASE)/Makefile.base

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/*
* Copyright (C) 2014 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_stm32f3
* @{
*
* @file
* @brief Low-level GPIO driver implementation
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
* @}
*/
#include "cpu.h"
#include "sched.h"
#include "thread.h"
#include "periph/gpio.h"
#include "periph_conf.h"
typedef struct {
void (*cb)(void);
} gpio_state_t;
static inline void irq_handler(gpio_t dev);
static gpio_state_t config[GPIO_NUMOF];
int gpio_init_out(gpio_t dev, gpio_pp_t pushpull)
{
GPIO_TypeDef *port;
uint32_t pin;
switch (dev) {
#if GPIO_0_EN
case GPIO_0:
GPIO_0_CLKEN();
port = GPIO_0_PORT;
pin = GPIO_0_PIN;
break;
#endif
#if GPIO_1_EN
case GPIO_1:
GPIO_1_CLKEN();
port = GPIO_1_PORT;
pin = GPIO_1_PIN;
break;
#endif
#if GPIO_2_EN
case GPIO_2:
GPIO_2_CLKEN();
port = GPIO_2_PORT;
pin = GPIO_2_PIN;
break;
#endif
#if GPIO_3_EN
case GPIO_3:
GPIO_3_CLKEN();
port = GPIO_3_PORT;
pin = GPIO_3_PIN;
break;
#endif
#if GPIO_4_EN
case GPIO_4:
GPIO_4_CLKEN();
port = GPIO_4_PORT;
pin = GPIO_4_PIN;
break;
#endif
#if GPIO_5_EN
case GPIO_5:
GPIO_5_CLKEN();
port = GPIO_5_PORT;
pin = GPIO_5_PIN;
break;
#endif
#if GPIO_6_EN
case GPIO_6:
GPIO_6_CLKEN();
port = GPIO_6_PORT;
pin = GPIO_6_PIN;
break;
#endif
#if GPIO_7_EN
case GPIO_7:
GPIO_7_CLKEN();
port = GPIO_7_PORT;
pin = GPIO_7_PIN;
break;
#endif
#if GPIO_8_EN
case GPIO_8:
GPIO_8_CLKEN();
port = GPIO_8_PORT;
pin = GPIO_8_PIN;
break;
#endif
#if GPIO_9_EN
case GPIO_9:
GPIO_9_CLKEN();
port = GPIO_9_PORT;
pin = GPIO_9_PIN;
break;
#endif
#if GPIO_10_EN
case GPIO_10:
GPIO_10_CLKEN();
port = GPIO_10_PORT;
pin = GPIO_10_PIN;
break;
#endif
#if GPIO_11_EN
case GPIO_11:
GPIO_11_CLKEN();
port = GPIO_11_PORT;
pin = GPIO_11_PIN;
break;
#endif
case GPIO_UNDEFINED:
default:
return -1;
}
port->MODER &= ~(2 << (2 * pin)); /* set pin to output mode */
port->MODER |= (1 << (2 * pin));
port->OTYPER &= ~(1 << pin); /* set to push-pull configuration */
port->OSPEEDR |= (3 << (2 * pin)); /* set to high speed */
port->PUPDR &= ~(3 << (2 * pin)); /* configure push-pull resistors */
port->PUPDR |= (pushpull << (2 * pin));
port->ODR &= ~(1 << pin); /* set pin to low signal */
return 0; /* all OK */
}
int gpio_init_in(gpio_t dev, gpio_pp_t pushpull)
{
GPIO_TypeDef *port;
uint32_t pin;
switch (dev) {
#if GPIO_0_EN
case GPIO_0:
GPIO_0_CLKEN();
port = GPIO_0_PORT;
pin = GPIO_0_PIN;
break;
#endif
#if GPIO_1_EN
case GPIO_1:
GPIO_1_CLKEN();
port = GPIO_1_PORT;
pin = GPIO_1_PIN;
break;
#endif
#if GPIO_2_EN
case GPIO_2:
GPIO_2_CLKEN();
port = GPIO_2_PORT;
pin = GPIO_2_PIN;
break;
#endif
#if GPIO_3_EN
case GPIO_3:
GPIO_3_CLKEN();
port = GPIO_3_PORT;
pin = GPIO_3_PIN;
break;
#endif
#if GPIO_4_EN
case GPIO_4:
GPIO_4_CLKEN();
port = GPIO_4_PORT;
pin = GPIO_4_PIN;
break;
#endif
#if GPIO_5_EN
case GPIO_5:
GPIO_5_CLKEN();
port = GPIO_5_PORT;
pin = GPIO_5_PIN;
break;
#endif
#if GPIO_6_EN
case GPIO_6:
GPIO_6_CLKEN();
port = GPIO_6_PORT;
pin = GPIO_6_PIN;
break;
#endif
#if GPIO_7_EN
case GPIO_7:
GPIO_7_CLKEN();
port = GPIO_7_PORT;
pin = GPIO_7_PIN;
break;
#endif
#if GPIO_8_EN
case GPIO_8:
GPIO_8_CLKEN();
port = GPIO_8_PORT;
pin = GPIO_8_PIN;
break;
#endif
#if GPIO_9_EN
case GPIO_9:
GPIO_9_CLKEN();
port = GPIO_9_PORT;
pin = GPIO_9_PIN;
break;
#endif
#if GPIO_10_EN
case GPIO_10:
GPIO_10_CLKEN();
port = GPIO_10_PORT;
pin = GPIO_10_PIN;
break;
#endif
#if GPIO_11_EN
case GPIO_11:
GPIO_11_CLKEN();
port = GPIO_11_PORT;
pin = GPIO_11_PIN;
break;
#endif
case GPIO_UNDEFINED:
default:
return -1;
}
port->MODER &= ~(3 << (2 * pin)); /* configure pin as input */
port->PUPDR &= ~(3 << (2 * pin)); /* configure push-pull resistors */
port->PUPDR |= (pushpull << (2 * pin));
return 0; /* everything alright here */
}
int gpio_init_int(gpio_t dev, gpio_pp_t pushpull, gpio_flank_t flank, void (*cb)(void))
{
uint32_t pin;
int res = gpio_init_in(dev, pushpull);
if (res < 0) {
return res;
}
/* enable the SYSCFG clock */
RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
switch (dev) {
#if GPIO_0_EN
case GPIO_0:
pin = GPIO_0_PIN;
GPIO_0_EXTI_CFG1();
GPIO_0_EXTI_CFG2();
NVIC_SetPriority(GPIO_0_IRQ, GPIO_IRQ_PRIO);
NVIC_EnableIRQ(GPIO_0_IRQ);
break;
#endif
#if GPIO_1_EN
case GPIO_1:
pin = GPIO_1_PIN;
GPIO_1_EXTI_CFG1();
GPIO_1_EXTI_CFG2();
NVIC_SetPriority(GPIO_1_IRQ, GPIO_IRQ_PRIO);
NVIC_EnableIRQ(GPIO_1_IRQ);
break;
#endif
#if GPIO_2_EN
case GPIO_2:
pin = GPIO_2_PIN;
GPIO_2_EXTI_CFG1();
GPIO_2_EXTI_CFG2();
NVIC_SetPriority(GPIO_2_IRQ, GPIO_IRQ_PRIO);
NVIC_EnableIRQ(GPIO_2_IRQ);
break;
#endif
#if GPIO_3_EN
case GPIO_3:
pin = GPIO_3_PIN;
GPIO_3_EXTI_CFG1();
GPIO_3_EXTI_CFG2();
NVIC_SetPriority(GPIO_3_IRQ, GPIO_IRQ_PRIO);
NVIC_EnableIRQ(GPIO_3_IRQ);
break;
#endif
#if GPIO_4_EN
case GPIO_4:
pin = GPIO_4_PIN;
GPIO_4_EXTI_CFG1();
GPIO_4_EXTI_CFG2();
NVIC_SetPriority(GPIO_4_IRQ, GPIO_IRQ_PRIO);
NVIC_EnableIRQ(GPIO_4_IRQ);
break;
#endif
#if GPIO_5_EN
case GPIO_5:
pin = GPIO_5_PIN;
GPIO_5_EXTI_CFG1();
GPIO_5_EXTI_CFG2();
NVIC_SetPriority(GPIO_5_IRQ, GPIO_IRQ_PRIO);
NVIC_EnableIRQ(GPIO_5_IRQ);
break;
#endif
#if GPIO_6_EN
case GPIO_6:
pin = GPIO_6_PIN;
GPIO_6_EXTI_CFG1();
GPIO_6_EXTI_CFG2();
NVIC_SetPriority(GPIO_6_IRQ, GPIO_IRQ_PRIO);
NVIC_EnableIRQ(GPIO_6_IRQ);
break;
#endif
#if GPIO_7_EN
case GPIO_7:
pin = GPIO_7_PIN;
GPIO_7_EXTI_CFG1();
GPIO_7_EXTI_CFG2();
NVIC_SetPriority(GPIO_7_IRQ, GPIO_IRQ_PRIO);
NVIC_EnableIRQ(GPIO_7_IRQ);
break;
#endif
#if GPIO_8_EN
case GPIO_8:
pin = GPIO_8_PIN;
GPIO_8_EXTI_CFG1();
GPIO_8_EXTI_CFG2();
NVIC_SetPriority(GPIO_8_IRQ, GPIO_IRQ_PRIO);
NVIC_EnableIRQ(GPIO_8_IRQ);
break;
#endif
#if GPIO_9_EN
case GPIO_9:
pin = GPIO_9_PIN;
GPIO_9_EXTI_CFG1();
GPIO_9_EXTI_CFG2();
NVIC_SetPriority(GPIO_9_IRQ, GPIO_IRQ_PRIO);
NVIC_EnableIRQ(GPIO_9_IRQ);
break;
#endif
#if GPIO_10_EN
case GPIO_10:
pin = GPIO_10_PIN;
GPIO_10_EXTI_CFG1();
GPIO_10_EXTI_CFG2();
NVIC_SetPriority(GPIO_10_IRQ, GPIO_IRQ_PRIO);
NVIC_EnableIRQ(GPIO_10_IRQ);
break;
#endif
#if GPIO_11_EN
case GPIO_11:
pin = GPIO_11_PIN;
GPIO_11_EXTI_CFG1();
GPIO_11_EXTI_CFG2();
NVIC_SetPriority(GPIO_11_IRQ, GPIO_IRQ_PRIO);
NVIC_EnableIRQ(GPIO_11_IRQ);
break;
#endif
case GPIO_UNDEFINED:
default:
return -1;
}
/* set callback */
config[dev].cb = cb;
/* configure the active edges */
switch (flank) {
case GPIO_RISING:
EXTI->RTSR |= (1 << pin);
break;
case GPIO_FALLING:
EXTI->FTSR |= (1 << pin);
break;
case GPIO_BOTH:
EXTI->RTSR |= (1 << pin);
EXTI->FTSR |= (1 << pin);
break;
}
/* enable interrupt for EXTI line */
EXTI->IMR |= (1 << pin);
return 0;
}
int gpio_read(gpio_t dev)
{
GPIO_TypeDef *port;
uint32_t pin;
switch (dev) {
#if GPIO_0_EN
case GPIO_0:
port = GPIO_0_PORT;
pin = GPIO_0_PIN;
break;
#endif
#if GPIO_1_EN
case GPIO_1:
port = GPIO_1_PORT;
pin = GPIO_1_PIN;
break;
#endif
#if GPIO_2_EN
case GPIO_2:
port = GPIO_2_PORT;
pin = GPIO_2_PIN;
break;
#endif
#if GPIO_3_EN
case GPIO_3:
port = GPIO_3_PORT;
pin = GPIO_3_PIN;
break;
#endif
#if GPIO_4_EN
case GPIO_4:
port = GPIO_4_PORT;
pin = GPIO_4_PIN;
break;
#endif
#if GPIO_5_EN
case GPIO_5:
port = GPIO_5_PORT;
pin = GPIO_5_PIN;
break;
#endif
#if GPIO_6_EN
case GPIO_6:
port = GPIO_6_PORT;
pin = GPIO_6_PIN;
break;
#endif
#if GPIO_7_EN
case GPIO_7:
port = GPIO_7_PORT;
pin = GPIO_7_PIN;
break;
#endif
#if GPIO_8_EN
case GPIO_8:
port = GPIO_8_PORT;
pin = GPIO_8_PIN;
break;
#endif
#if GPIO_9_EN
case GPIO_9:
port = GPIO_9_PORT;
pin = GPIO_9_PIN;
break;
#endif
#if GPIO_10_EN
case GPIO_10:
port = GPIO_10_PORT;
pin = GPIO_10_PIN;
break;
#endif
#if GPIO_11_EN
case GPIO_11:
port = GPIO_11_PORT;
pin = GPIO_11_PIN;
break;
#endif
case GPIO_UNDEFINED:
default:
return -1;
}
if (port->MODER & (3 << (pin * 2))) { /* if configured as output */
return port->ODR & (1 << pin); /* read output data register */
}
else {
return port->IDR & (1 << pin); /* else read input data register */
}
}
int gpio_set(gpio_t dev)
{
switch (dev) {
#if GPIO_0_EN
case GPIO_0:
GPIO_0_PORT->BSRRL = (1 << GPIO_0_PIN);
break;
#endif
#if GPIO_1_EN
case GPIO_1:
GPIO_1_PORT->BSRRL = (1 << GPIO_1_PIN);
break;
#endif
#if GPIO_2_EN
case GPIO_2:
GPIO_2_PORT->BSRRL = (1 << GPIO_2_PIN);
break;
#endif
#if GPIO_3_EN
case GPIO_3:
GPIO_3_PORT->BSRRL = (1 << GPIO_3_PIN);
break;
#endif
#if GPIO_4_EN
case GPIO_4:
GPIO_4_PORT->BSRRL = (1 << GPIO_4_PIN);
break;
#endif
#if GPIO_5_EN
case GPIO_5:
GPIO_5_PORT->BSRRL = (1 << GPIO_5_PIN);
break;
#endif
#if GPIO_6_EN
case GPIO_6:
GPIO_6_PORT->BSRRL = (1 << GPIO_6_PIN);
break;
#endif
#if GPIO_7_EN
case GPIO_7:
GPIO_7_PORT->BSRRL = (1 << GPIO_7_PIN);
break;
#endif
#if GPIO_8_EN
case GPIO_8:
GPIO_8_PORT->BSRRL = (1 << GPIO_8_PIN);
break;
#endif
#if GPIO_9_EN
case GPIO_9:
GPIO_9_PORT->BSRRL = (1 << GPIO_9_PIN);
break;
#endif
#if GPIO_10_EN
case GPIO_10:
GPIO_10_PORT->BSRRL = (1 << GPIO_10_PIN);
break;
#endif
#if GPIO_11_EN
case GPIO_11:
GPIO_11_PORT->BSRRL = (1 << GPIO_11_PIN);
#endif
break;
case GPIO_UNDEFINED:
default:
return -1;
}
return 0;
}
int gpio_clear(gpio_t dev)
{
switch (dev) {
#if GPIO_0_EN
case GPIO_0:
GPIO_0_PORT->BSRRH = (1 << GPIO_0_PIN);
break;
#endif
#if GPIO_1_EN
case GPIO_1:
GPIO_1_PORT->BSRRH = (1 << GPIO_1_PIN);
break;
#endif
#if GPIO_2_EN
case GPIO_2:
GPIO_2_PORT->BSRRH = (1 << GPIO_2_PIN);
break;
#endif
#if GPIO_3_EN
case GPIO_3:
GPIO_3_PORT->BSRRH = (1 << GPIO_3_PIN);
break;
#endif
#if GPIO_4_EN
case GPIO_4:
GPIO_4_PORT->BSRRH = (1 << GPIO_4_PIN);
break;
#endif
#if GPIO_5_EN
case GPIO_5:
GPIO_5_PORT->BSRRH = (1 << GPIO_5_PIN);
break;
#endif
#if GPIO_6_EN
case GPIO_6:
GPIO_6_PORT->BSRRH = (1 << GPIO_6_PIN);
break;
#endif
#if GPIO_7_EN
case GPIO_7:
GPIO_7_PORT->BSRRH = (1 << GPIO_7_PIN);
break;
#endif
#if GPIO_8_EN
case GPIO_8:
GPIO_8_PORT->BSRRH = (1 << GPIO_8_PIN);
break;
#endif
#if GPIO_9_EN
case GPIO_9:
GPIO_9_PORT->BSRRH = (1 << GPIO_9_PIN);
break;
#endif
#if GPIO_10_EN
case GPIO_10:
GPIO_10_PORT->BSRRH = (1 << GPIO_10_PIN);
break;
#endif
#if GPIO_11_EN
case GPIO_11:
GPIO_11_PORT->BSRRH = (1 << GPIO_11_PIN);
break;
#endif
case GPIO_UNDEFINED:
default:
return -1;
}
return 0;
}
int gpio_toggle(gpio_t dev)
{
if (gpio_read(dev)) {
return gpio_clear(dev);
}
else {
return gpio_set(dev);
}
}
int gpio_write(gpio_t dev, int value)
{
if (value) {
return gpio_set(dev);
}
else {
return gpio_clear(dev);
}
}
static inline void irq_handler(gpio_t dev)
{
config[dev].cb();
if (sched_context_switch_request) {
thread_yield();
}
}
__attribute__((naked)) void isr_exti0(void)
{
ISR_ENTER();
if (EXTI->PR & EXTI_PR_PR0) {
EXTI->PR |= EXTI_PR_PR0; /* clear status bit by writing a 1 to it */
irq_handler(GPIO_IRQ_0);
}
ISR_EXIT();
}
__attribute__((naked)) void isr_exti1(void)
{
ISR_ENTER();
if (EXTI->PR & EXTI_PR_PR1) {
EXTI->PR |= EXTI_PR_PR1; /* clear status bit by writing a 1 to it */
irq_handler(GPIO_IRQ_1);
}
ISR_EXIT();
}
__attribute__((naked)) void isr_exti2(void)
{
ISR_ENTER();
if (EXTI->PR & EXTI_PR_PR2) {
EXTI->PR |= EXTI_PR_PR2; /* clear status bit by writing a 1 to it */
irq_handler(GPIO_IRQ_2);
}
ISR_EXIT();
}
__attribute__((naked)) void isr_exti3(void)
{
ISR_ENTER();
if (EXTI->PR & EXTI_PR_PR3) {
EXTI->PR |= EXTI_PR_PR3; /* clear status bit by writing a 1 to it */
irq_handler(GPIO_IRQ_3);
}
ISR_EXIT();
}
__attribute__((naked)) void isr_exti4(void)
{
ISR_ENTER();
if (EXTI->PR & EXTI_PR_PR4) {
EXTI->PR |= EXTI_PR_PR4; /* clear status bit by writing a 1 to it */
irq_handler(GPIO_IRQ_4);
}
ISR_EXIT();
}
__attribute__((naked)) void isr_exti9_5(void)
{
ISR_ENTER();
if (EXTI->PR & EXTI_PR_PR5) {
EXTI->PR |= EXTI_PR_PR5; /* clear status bit by writing a 1 to it */
irq_handler(GPIO_IRQ_5);
}
else if (EXTI->PR & EXTI_PR_PR6) {
EXTI->PR |= EXTI_PR_PR6; /* clear status bit by writing a 1 to it */
irq_handler(GPIO_IRQ_6);
}
else if (EXTI->PR & EXTI_PR_PR7) {
EXTI->PR |= EXTI_PR_PR7; /* clear status bit by writing a 1 to it */
irq_handler(GPIO_IRQ_7);
}
else if (EXTI->PR & EXTI_PR_PR8) {
EXTI->PR |= EXTI_PR_PR8; /* clear status bit by writing a 1 to it */
irq_handler(GPIO_IRQ_8);
}
else if (EXTI->PR & EXTI_PR_PR9) {
EXTI->PR |= EXTI_PR_PR9; /* clear status bit by writing a 1 to it */
irq_handler(GPIO_IRQ_9);
}
ISR_EXIT();
}
__attribute__((naked)) void isr_exti15_10(void)
{
ISR_ENTER();
if (EXTI->PR & EXTI_PR_PR10) {
EXTI->PR |= EXTI_PR_PR10; /* clear status bit by writing a 1 to it */
irq_handler(GPIO_IRQ_10);
}
else if (EXTI->PR & EXTI_PR_PR11) {
EXTI->PR |= EXTI_PR_PR11; /* clear status bit by writing a 1 to it */
irq_handler(GPIO_IRQ_11);
}
else if (EXTI->PR & EXTI_PR_PR12) {
EXTI->PR |= EXTI_PR_PR12; /* clear status bit by writing a 1 to it */
irq_handler(GPIO_IRQ_12);
}
else if (EXTI->PR & EXTI_PR_PR13) {
EXTI->PR |= EXTI_PR_PR13; /* clear status bit by writing a 1 to it */
irq_handler(GPIO_IRQ_13);
}
else if (EXTI->PR & EXTI_PR_PR14) {
EXTI->PR |= EXTI_PR_PR14; /* clear status bit by writing a 1 to it */
irq_handler(GPIO_IRQ_14);
}
else if (EXTI->PR & EXTI_PR_PR15) {
EXTI->PR |= EXTI_PR_PR15; /* clear status bit by writing a 1 to it */
irq_handler(GPIO_IRQ_15);
}
ISR_EXIT();
}

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/*
* Copyright (C) 2014 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_stm32f3
* @{
*
* @file
* @brief Low-level timer driver implementation
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
* @}
*/
#include <stdlib.h>
#include "cpu.h"
#include "board.h"
#include "sched.h"
#include "thread.h"
#include "periph_conf.h"
#include "periph/timer.h"
/** Unified IRQ handler for all timers */
static inline void irq_handler(tim_t timer, TIM_TypeDef *dev);
/** Type for timer state */
typedef struct {
void (*cb)(int);
} timer_conf_t;
/** Timer state memory */
timer_conf_t config[TIMER_NUMOF];
int timer_init(tim_t dev, unsigned int ticks_per_us, void (*callback)(int))
{
TIM_TypeDef *timer;
switch (dev) {
#if TIMER_0_EN
case TIMER_0:
/* enable timer peripheral clock */
TIMER_0_CLKEN();
/* set timer's IRQ priority */
NVIC_SetPriority(TIMER_0_IRQ_CHAN, TIMER_IRQ_PRIO);
/* select timer */
timer = TIMER_0_DEV;
break;
#endif
case TIMER_UNDEFINED:
default:
return -1;
}
/* set callback function */
config[dev].cb = callback;
/* set timer to run in counter mode */
timer->CR1 = 0;
timer->CR2 = 0;
/* set auto-reload and prescaler values and load new values */
timer->PSC = TIMER_0_PRESCALER * ticks_per_us;
timer->EGR |= TIM_EGR_UG;
/* enable the timer's interrupt */
timer_irq_enable(dev);
/* start the timer */
timer_start(dev);
return 0;
}
int timer_set(tim_t dev, int channel, unsigned int timeout)
{
int now = timer_read(dev);
return timer_set_absolute(dev, channel, now + timeout - 1);
}
int timer_set_absolute(tim_t dev, int channel, unsigned int value)
{
TIM_TypeDef *timer;
switch (dev) {
#if TIMER_0_EN
case TIMER_0:
timer = TIMER_0_DEV;
break;
#endif
default:
return -1;
}
switch (channel) {
case 0:
timer->CCR1 = value;
timer->SR &= ~TIM_SR_CC1IF;
timer->DIER |= TIM_DIER_CC1IE;
break;
case 1:
timer->CCR2 = value;
timer->SR &= ~TIM_SR_CC2IF;
timer->DIER |= TIM_DIER_CC2IE;
break;
case 2:
timer->CCR3 = value;
timer->SR &= ~TIM_SR_CC3IF;
timer->DIER |= TIM_DIER_CC3IE;
break;
case 3:
timer->CCR4 = value;
timer->SR &= ~TIM_SR_CC4IF;
timer->DIER |= TIM_DIER_CC4IE;
break;
default:
return -1;
}
return 0;
}
int timer_clear(tim_t dev, int channel)
{
TIM_TypeDef *timer;
switch (dev) {
#if TIMER_0_EN
case TIMER_0:
timer = TIMER_0_DEV;
break;
#endif
case TIMER_UNDEFINED:
default:
return -1;
}
switch (channel) {
case 0:
timer->DIER &= ~TIM_DIER_CC1IE;
break;
case 1:
timer->DIER &= ~TIM_DIER_CC2IE;
break;
case 2:
timer->DIER &= ~TIM_DIER_CC3IE;
break;
case 3:
timer->DIER &= ~TIM_DIER_CC4IE;
break;
default:
return -1;
}
return 0;
}
unsigned int timer_read(tim_t dev)
{
switch (dev) {
#if TIMER_0_EN
case TIMER_0:
return TIMER_0_DEV->CNT;
break;
#endif
case TIMER_UNDEFINED:
default:
return 0;
}
}
void timer_start(tim_t dev)
{
switch (dev) {
#if TIMER_0_EN
case TIMER_0:
TIMER_0_DEV->CR1 |= TIM_CR1_CEN;
break;
#endif
case TIMER_UNDEFINED:
break;
}
}
void timer_stop(tim_t dev)
{
switch (dev) {
#if TIMER_0_EN
case TIMER_0:
TIMER_0_DEV->CR1 &= ~TIM_CR1_CEN;
break;
#endif
case TIMER_UNDEFINED:
break;
}
}
void timer_irq_enable(tim_t dev)
{
switch (dev) {
#if TIMER_0_EN
case TIMER_0:
NVIC_EnableIRQ(TIMER_0_IRQ_CHAN);
break;
#endif
case TIMER_UNDEFINED:
break;
}
}
void timer_irq_disable(tim_t dev)
{
switch (dev) {
#if TIMER_0_EN
case TIMER_0:
NVIC_DisableIRQ(TIMER_0_IRQ_CHAN);
break;
#endif
case TIMER_UNDEFINED:
break;
}
}
void timer_reset(tim_t dev)
{
switch (dev) {
#if TIMER_0_EN
case TIMER_0:
TIMER_0_DEV->CNT = 0;
break;
#endif
case TIMER_UNDEFINED:
break;
}
}
#if TIMER_0_EN
__attribute__ ((naked)) void TIMER_0_ISR(void)
{
ISR_ENTER();
irq_handler(TIMER_0, TIMER_0_DEV);
ISR_EXIT();
}
#endif
static inline void irq_handler(tim_t timer, TIM_TypeDef *dev)
{
if (dev->SR & TIM_SR_CC1IF) {
dev->DIER &= ~TIM_DIER_CC1IE;
dev->SR &= ~TIM_SR_CC1IF;
config[timer].cb(0);
}
else if (dev->SR & TIM_SR_CC2IF) {
dev->DIER &= ~TIM_DIER_CC2IE;
dev->SR &= ~TIM_SR_CC2IF;
config[timer].cb(1);
}
else if (dev->SR & TIM_SR_CC3IF) {
dev->DIER &= ~TIM_DIER_CC3IE;
dev->SR &= ~TIM_SR_CC3IF;
config[timer].cb(2);
}
else if (dev->SR & TIM_SR_CC4IF) {
dev->DIER &= ~TIM_DIER_CC4IE;
dev->SR &= ~TIM_SR_CC4IF;
config[timer].cb(3);
}
if (sched_context_switch_request) {
thread_yield();
}
}

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/*
* Copyright (C) 2014 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_stm32f3
* @{
*
* @file
* @brief Low-level UART driver implementation
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
* @}
*/
#include "cpu.h"
#include "sched.h"
#include "thread.h"
#include "periph_conf.h"
#include "periph/uart.h"
/**
* @brief Each UART device has to store two callbacks.
*/
typedef struct {
void (*rx_cb)(char);
void (*tx_cb)(void);
} uart_conf_t;
/**
* @brief Unified interrupt handler for all UART devices
*
* @param uartnum the number of the UART that triggered the ISR
* @param uart the UART device that triggered the ISR
*/
static inline void irq_handler(uart_t uartnum, USART_TypeDef *uart);
/**
* @brief Allocate memory to store the callback functions.
*/
static uart_conf_t config[UART_NUMOF];
int uart_init(uart_t uart, uint32_t baudrate, void (*rx_cb)(char), void (*tx_cb)(void))
{
/* do basic initialization */
int res = uart_init_blocking(uart, baudrate);
if (res < 0) {
return res;
}
/* remember callback addresses */
config[uart].rx_cb = rx_cb;
config[uart].tx_cb = tx_cb;
/* enable receive interrupt */
switch (uart) {
#if UART_0_EN
case UART_0:
NVIC_SetPriority(UART_0_IRQ_CHAN, UART_IRQ_PRIO);
NVIC_EnableIRQ(UART_0_IRQ_CHAN);
UART_0_DEV->CR1 |= USART_CR1_RXNEIE;
break;
#endif
#if UART_1_EN
case UART_1:
NVIC_SetPriority(UART_1_IRQ_CHAN, UART_IRQ_PRIO);
NVIC_EnableIRQ(UART_1_IRQ_CHAN);
UART_1_DEV->CR1 |= USART_CR1_RXNEIE;
break;
#endif
#if UART_2_EN
case UART_2:
NVIC_SetPriority(UART_2_IRQ_CHAN, UART_IRQ_PRIO);
NVIC_EnableIRQ(UART_2_IRQ_CHAN);
UART_2_DEV->CR1 |= USART_CR1_RXNEIE;
break;
#endif
case UART_UNDEFINED:
default:
return -2;
break;
}
return 0;
}
int uart_init_blocking(uart_t uart, uint32_t baudrate)
{
USART_TypeDef *dev;
GPIO_TypeDef *port;
uint32_t tx_pin;
uint32_t rx_pin;
uint8_t af;
float clk;
float divider;
uint16_t mantissa;
uint8_t fraction;
switch (uart) {
#if UART_0_EN
case UART_0:
dev = UART_0_DEV;
port = UART_0_PORT;
clk = UART_0_CLK;
tx_pin = UART_0_TX_PIN;
rx_pin = UART_0_RX_PIN;
af = UART_0_AF;
UART_0_CLKEN();
UART_0_PORT_CLKEN();
break;
#endif
#if UART_1_EN
case UART_1:
dev = UART_1_DEV;
port = UART_1_PORT;
clk = UART_1_CLK;
tx_pin = UART_1_TX_PIN;
rx_pin = UART_1_RX_PIN;
af = UART_1_AF;
UART_1_CLKEN();
UART_1_PORT_CLKEN();
break;
#endif
#if UART_2_EN
case UART_2:
dev = UART_2_DEV;
port = UART_2_PORT;
clk = UART_2_CLK;
tx_pin = UART_2_TX_PIN;
rx_pin = UART_2_RX_PIN;
af = UART_2_AF;
UART_2_CLKEN();
UART_2_PORT_CLKEN();
break;
#endif
case UART_UNDEFINED:
default:
return -1;
}
/* configure RX and TX pins, set pin to use alternative function mode */
port->MODER &= ~(3 << (rx_pin * 2) | 3 << (tx_pin * 2));
port->MODER |= 2 << (rx_pin * 2) | 2 << (tx_pin * 2);
/* and assign alternative function */
if (rx_pin < 8) {
port->AFR[0] &= ~(0xf << (rx_pin * 4));
port->AFR[0] |= af << (rx_pin * 4);
}
else {
port->AFR[1] &= ~(0xf << ((rx_pin - 8) * 4));
port->AFR[1] |= af << ((rx_pin - 8) * 4);
}
if (tx_pin < 8) {
port->AFR[0] &= ~(0xf << (tx_pin * 4));
port->AFR[0] |= af << (tx_pin * 4);
}
else {
port->AFR[1] &= ~(0xf << ((tx_pin - 8) * 4));
port->AFR[1] |= af << ((tx_pin - 8) * 4);
}
/* configure UART to mode 8N1 with given baudrate */
divider = clk / (16 * baudrate);
mantissa = (uint16_t)divider;
fraction = (uint8_t)((divider - mantissa) * 16);
dev->BRR = ((mantissa & 0x0fff) << 4) | (0x0f & fraction);
/* enable receive and transmit mode */
dev->CR3 = 0;
dev->CR2 = 0;
dev->CR1 |= USART_CR1_UE | USART_CR1_TE | USART_CR1_RE;
return 0;
}
void uart_tx_begin(uart_t uart)
{
switch (uart) {
#if UART_0_EN
case UART_0:
UART_0_DEV->CR1 |= USART_CR1_TXEIE;
break;
#endif
#if UART_1_EN
case UART_1:
UART_1_DEV->CR1 |= USART_CR1_TXEIE;
break;
#endif
#if UART_2_EN
case UART_2:
UART_2_DEV->CR1 |= USART_CR1_TXEIE;
break;
#endif
case UART_UNDEFINED:
default:
break;
}
}
void uart_tx_end(uart_t uart)
{
switch (uart) {
#if UART_0_EN
case UART_0:
UART_0_DEV->CR1 &= ~USART_CR1_TXEIE;
break;
#endif
#if UART_1_EN
case UART_1:
UART_1_DEV->CR1 &= ~USART_CR1_TXEIE;
break;
#endif
#if UART_2_EN
case UART_2:
UART_2_DEV->CR1 &= ~USART_CR1_TXEIE;
break;
#endif
case UART_UNDEFINED:
default:
break;
}
}
int uart_write(uart_t uart, char data)
{
USART_TypeDef *dev;
switch (uart) {
#if UART_0_EN
case UART_0:
dev = UART_0_DEV;
break;
#endif
#if UART_1_EN
case UART_1:
dev = UART_1_DEV;
break;
#endif
#if UART_2_EN
case UART_2:
dev = UART_2_DEV;
break;
#endif
case UART_UNDEFINED:
default:
return -2;
break;
}
if (dev->ISR & USART_ISR_TXE) {
dev->TDR = (uint8_t)data;
}
return 0;
}
int uart_read_blocking(uart_t uart, char *data)
{
USART_TypeDef *dev;
switch (uart) {
#if UART_0_EN
case UART_0:
dev = UART_0_DEV;
break;
#endif
#if UART_1_EN
case UART_1:
dev = UART_1_DEV;
break;
#endif
#if UART_2_EN
case UART_2:
dev = UART_2_DEV;
break;
#endif
case UART_UNDEFINED:
default:
return -2;
break;
}
while (!(dev->ISR & USART_ISR_RXNE));
*data = (char)dev->RDR;
return 1;
}
int uart_write_blocking(uart_t uart, char data)
{
USART_TypeDef *dev;
switch (uart) {
#if UART_0_EN
case UART_0:
dev = UART_0_DEV;
break;
#endif
#if UART_1_EN
case UART_1:
dev = UART_1_DEV;
break;
#endif
#if UART_2_EN
case UART_2:
dev = UART_2_DEV;
break;
#endif
case UART_UNDEFINED:
default:
return -2;
break;
}
while (!(dev->ISR & USART_ISR_TXE));
dev->TDR = (uint8_t)data;
return 1;
}
#if UART_0_EN
__attribute__((naked)) void UART_0_ISR(void)
{
ISR_ENTER();
irq_handler(UART_0, UART_0_DEV);
ISR_EXIT();
}
#endif
#if UART_1_EN
__attribute__((naked)) void UART_1_ISR(void)
{
ISR_ENTER();
irq_handler(UART_1, UART_1_DEV);
ISR_EXIT();
}
#endif
#if UART_2_EN
__attribute__((naked)) void UART_2_ISR(void)
{
ISR_ENTER();
irq_handler(UART_2, UART_2_DEV);
ISR_EXIT();
}
#endif
static inline void irq_handler(uint8_t uartnum, USART_TypeDef *dev)
{
if (dev->ISR & USART_ISR_RXNE) {
char data = (char)dev->RDR;
config[uartnum].rx_cb(data);
}
else if (dev->ISR & USART_ISR_TXE) {
config[uartnum].tx_cb();
}
if (sched_context_switch_request) {
thread_yield();
}
}

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/*
* Copyright (C) 2014 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_stm32f3
* @{
*
* @file
* @brief Implementation of the kernels reboot interface
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
* @}
*/
#include <stdio.h>
#include "arch/reboot_arch.h"
#include "cpu.h"
int reboot_arch(int mode)
{
printf("Going into reboot, mode %i\n", mode);
NVIC_SystemReset();
return 0;
}

292
cpu/stm32f3/startup.c Normal file
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/*
* Copyright (C) 2014 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_stm32f3
* @{
*
* @file
* @brief Startup code and interrupt vector definition
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
* @}
*/
#include <stdint.h>
#include "board.h"
/**
* memory markers as defined in the linker script
*/
extern uint32_t _sfixed;
extern uint32_t _efixed;
extern uint32_t _etext;
extern uint32_t _srelocate;
extern uint32_t _erelocate;
extern uint32_t _szero;
extern uint32_t _ezero;
extern uint32_t _sstack;
extern uint32_t _estack;
/**
* @brief functions for initializing the board, std-lib and kernel
*/
extern void board_init(void);
extern void kernel_init(void);
extern void __libc_init_array(void);
/**
* @brief This function is the entry point after a system reset
*
* After a system reset, the following steps are necessary and carried out:
* 1. load data section from flash to ram
* 2. overwrite uninitialized data section (BSS) with zeros
* 3. initialize the newlib
* 4. initialize the board (sync clock, setup std-IO)
* 5. initialize and start RIOTs kernel
*/
void reset_handler(void)
{
uint32_t *dst;
uint32_t *src = &_etext;
/* load data section from flash to ram */
for (dst = &_srelocate; dst < &_erelocate; ) {
*(dst++) = *(src++);
}
/* default bss section to zero */
for (dst = &_szero; dst < &_ezero; ) {
*(dst++) = 0;
}
/* initialize the board and startup the kernel */
board_init();
/* initialize std-c library (this should be done after board_init) */
__libc_init_array();
/* startup the kernel */
kernel_init();
}
/**
* @brief Default handler is called in case no interrupt handler was defined
*/
void dummy_handler(void)
{
while (1) {asm ("nop");}
}
void isr_nmi(void)
{
while (1) {asm ("nop");}
}
void isr_mem_manage(void)
{
while (1) {asm ("nop");}
}
void isr_debug_mon(void)
{
while (1) {asm ("nop");}
}
void isr_hard_fault(void)
{
while (1) {asm ("nop");}
}
void isr_bus_fault(void)
{
while (1) {asm ("nop");}
}
void isr_usage_fault(void)
{
while (1) {asm ("nop");}
}
/* Cortex-M specific interrupt vectors */
void isr_svc(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_pendsv(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_systick(void) __attribute__ ((weak, alias("dummy_handler")));
/* STM32F3 specific interrupt vector */
void isr_wwdg(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_pvd(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_tamp_stamp(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_rtc_wkup(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_flash(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_rcc(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_exti0(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_exti1(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_exti2_tsc(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_exti3(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_exti4(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_dma1_channel1(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_dma1_channel2(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_dma1_channel3(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_dma1_channel4(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_dma1_channel5(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_dma1_channel6(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_dma1_channel7(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_adc1_2(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_usb_hp_can_tx(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_usb_lp_can_rx0(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_can_rx1(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_can_sce(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_exti9_5(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_tim1_brk_tim15(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_tim1_up_tim16(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_tim1_trg_com_tim17(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_tim1_cc(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_tim2(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_tim3(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_tim4(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_i2c1_ev(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_i2c1_er(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_i2c2_ev(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_i2c2_er(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_spi1(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_spi2(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_usart1(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_usart2(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_usart3(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_exti15_10(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_rtc_alarm(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_usbwakeup(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_tim8_brk(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_tim8_up(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_tim8_trg_com(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_tim8_cc(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_adc3(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_spi3(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_uart4(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_uart5(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_tim6_dac(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_tim7(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_dma2_channel1(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_dma2_channel2(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_dma2_channel3(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_dma2_channel4(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_dma2_channel5(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_adc4(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_comp1_2_3(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_comp4_5_6(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_comp7(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_usb_hp(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_usb_lp(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_usbwakeup_rmp(void) __attribute__ ((weak, alias("dummy_handler")));
void isr_fpu(void) __attribute__ ((weak, alias("dummy_handler")));
/* interrupt vector table */
__attribute__ ((section(".vectors")))
const void *interrupt_vector[] = {
/* Stack pointer */
(void*) (&_estack), /* pointer to the top of the empty stack */
/* Cortex-M4 handlers */
(void*) reset_handler, /* */
(void*) isr_nmi, /* */
(void*) isr_hard_fault, /* */
(void*) isr_mem_manage, /* */
(void*) isr_bus_fault, /* */
(void*) isr_usage_fault, /* */
(void*) (0UL), /* reserved */
(void*) (0UL), /* reserved */
(void*) (0UL), /* reserved */
(void*) (0UL), /* reserved */
(void*) isr_svc, /* */
(void*) isr_debug_mon, /* */
(void*) (0UL), /* reserved */
(void*) isr_pendsv, /* */
(void*) isr_systick, /* */
/* STMF3 specific peripheral handlers */
(void*) isr_wwdg, /* */
(void*) isr_pvd, /* */
(void*) isr_tamp_stamp, /* */
(void*) isr_rtc_wkup, /* */
(void*) isr_flash, /* */
(void*) isr_rcc, /* */
(void*) isr_exti0, /* */
(void*) isr_exti1, /* */
(void*) isr_exti2_tsc, /* */
(void*) isr_exti3, /* */
(void*) isr_exti4, /* */
(void*) isr_dma1_channel1, /* */
(void*) isr_dma1_channel2, /* */
(void*) isr_dma1_channel3, /* */
(void*) isr_dma1_channel4, /* */
(void*) isr_dma1_channel5, /* */
(void*) isr_dma1_channel6, /* */
(void*) isr_dma1_channel7, /* */
(void*) isr_adc1_2, /* */
(void*) isr_usb_hp_can_tx, /* */
(void*) isr_usb_lp_can_rx0, /* */
(void*) isr_can_rx1, /* */
(void*) isr_can_sce, /* */
(void*) isr_exti9_5, /* */
(void*) isr_tim1_brk_tim15, /* */
(void*) isr_tim1_up_tim16, /* */
(void*) isr_tim1_trg_com_tim17, /* */
(void*) isr_tim1_cc, /* */
(void*) isr_tim2, /* */
(void*) isr_tim3, /* */
(void*) isr_tim4, /* */
(void*) isr_i2c1_ev, /* */
(void*) isr_i2c1_er, /* */
(void*) isr_i2c2_ev, /* */
(void*) isr_i2c2_er, /* */
(void*) isr_spi1, /* */
(void*) isr_spi2, /* */
(void*) isr_usart1, /* */
(void*) isr_usart2, /* */
(void*) isr_usart3, /* */
(void*) isr_exti15_10, /* */
(void*) isr_rtc_alarm, /* */
(void*) isr_usbwakeup, /* */
(void*) isr_tim8_brk, /* */
(void*) isr_tim8_up, /* */
(void*) isr_tim8_trg_com, /* */
(void*) isr_tim8_cc, /* */
(void*) isr_adc3, /* */
(void*) (0UL), /* reserved */
(void*) (0UL), /* reserved */
(void*) (0UL), /* reserved */
(void*) isr_spi3, /* */
(void*) isr_uart4, /* */
(void*) isr_uart5, /* */
(void*) isr_tim6_dac, /* */
(void*) isr_tim7, /* */
(void*) isr_dma2_channel1, /* */
(void*) isr_dma2_channel2, /* */
(void*) isr_dma2_channel3, /* */
(void*) isr_dma2_channel4, /* */
(void*) isr_dma2_channel5, /* */
(void*) isr_adc4, /* */
(void*) (0UL), /* reserved */
(void*) (0UL), /* reserved */
(void*) isr_comp1_2_3, /* */
(void*) isr_comp4_5_6, /* */
(void*) isr_comp7, /* */
(void*) (0UL), /* reserved */
(void*) (0UL), /* reserved */
(void*) (0UL), /* reserved */
(void*) (0UL), /* reserved */
(void*) (0UL), /* reserved */
(void*) (0UL), /* reserved */
(void*) (0UL), /* reserved */
(void*) isr_usb_hp, /* */
(void*) isr_usb_lp, /* */
(void*) isr_usbwakeup_rmp, /* */
(void*) (0UL), /* reserved */
(void*) (0UL), /* reserved */
(void*) (0UL), /* reserved */
(void*) (0UL), /* reserved */
(void*) isr_fpu, /* */
};

143
cpu/stm32f3/stm32f303vc_linkerscript.ld Normal file
View File

@ -0,0 +1,143 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2012, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following condition is met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
/* Memory Spaces Definitions */
MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 256K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 40K
ccmram (rwx): ORIGIN = 0x10000000, LENGTH = 8K
}
/* The stack size used by the application. NOTE: you need to adjust */
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0xa00; /* 2.5K */
/* Section Definitions */
SECTIONS
{
.text :
{
. = ALIGN(4);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(0x4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(4);
KEEP(*(.fini))
. = ALIGN(4);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(4);
_efixed = .; /* End of text section */
} > rom
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > rom
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(4);
_etext = .;
.relocate : AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(4);
_erelocate = .;
} > ram
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(4);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(4);
_ebss = . ;
_ezero = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
. = ALIGN(4);
_end = . ;
}

293
cpu/stm32f3/syscalls.c Normal file
View File

@ -0,0 +1,293 @@
/*
* Copyright (C) 2014 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_stm32f3
* @{
*
* @file
* @brief NewLib system call implementations for STM32F3
*
* @author Michael Baar <michael.baar@fu-berlin.de>
* @author Stefan Pfeiffer <pfeiffer@inf.fu-berlin.de>
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
* @}
*/
#include <errno.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/stat.h>
#include <sys/unistd.h>
#include <stdint.h>
#include "cpu.h"
#include "board.h"
#include "thread.h"
#include "kernel.h"
#include "mutex.h"
#include "ringbuffer.h"
#include "irq.h"
#include "periph/uart.h"
/**
* @brief manage the heap
*/
extern uint32_t _end; /* address of last used memory cell */
caddr_t heap_top = (caddr_t)&_end + 4;
/**
* @brief use mutex for waiting on incoming UART chars
*/
static mutex_t uart_rx_mutex;
static char rx_buf_mem[STDIO_BUFSIZE];
static ringbuffer_t rx_buf;
/**
* @brief Receive a new character from the UART and put it into the receive buffer
*/
void rx_cb(char data)
{
ringbuffer_add_one(&rx_buf, data);
mutex_unlock(&uart_rx_mutex);
}
/**
* @brief Initialize NewLib, called by __libc_init_array() from the startup script
*/
void _init(void)
{
mutex_init(&uart_rx_mutex);
ringbuffer_init(&rx_buf, rx_buf_mem, STDIO_BUFSIZE);
uart_init(STDIO, STDIO_BAUDRATE, rx_cb, 0);
}
/**
* @brief Free resources on NewLib de-initialization, not used for RIOT
*/
void _fini(void)
{
/* nothing to do here */
}
/**
* @brief Exit a program without cleaning up files
*
* If your system doesn't provide this, it is best to avoid linking with subroutines that
* require it (exit, system).
*
* @param n the exit code, 0 for all OK, >0 for not OK
*/
void _exit(int n)
{
printf("#! exit %i: resetting\n", n);
NVIC_SystemReset();
while(1);
}
/**
* @brief Allocate memory from the heap.
*
* The current heap implementation is very rudimentary, it is only able to allocate
* memory. But it does not
* - check if the returned address is valid (no check if the memory very exists)
* - have any means to free memory again
*
* TODO: check if the requested memory is really available
*
* @return [description]
*/
caddr_t _sbrk_r(struct _reent *r, size_t incr)
{
unsigned int state = disableIRQ();
caddr_t res = heap_top;
heap_top += incr;
restoreIRQ(state);
return res;
}
/**
* @brief Get the process-ID of the current thread
*
* @return the process ID of the current thread
*/
int _getpid(void)
{
return sched_active_thread->pid;
}
/**
* @brief Send a signal to a given thread
*
* @param r TODO
* @param pid TODO
* @param sig TODO
*
* @return TODO
*/
int _kill_r(struct _reent *r, int pid, int sig)
{
r->_errno = ESRCH; /* not implemented yet */
return -1;
}
/**
* @brief Open a file
*
* @param r TODO
* @param name TODO
* @param mode TODO
*
* @return TODO
*/
int _open_r(struct _reent *r, const char *name, int mode)
{
r->_errno = ENODEV; /* not implemented yet */
return -1;
}
/**
* @brief Read from a file
*
* All input is read from UART_0. The function will block until a byte is actually read.
*
* Note: the read function does not buffer - data will be lost if the function is not
* called fast enough.
*
* TODO: implement more sophisticated read call.
*
* @param r TODO
* @param fd TODO
* @param buffer TODO
* @param int TODO
*
* @return TODO
*/
int _read_r(struct _reent *r, int fd, void *buffer, unsigned int count)
{
while (rx_buf.avail == 0) {
mutex_lock(&uart_rx_mutex);
}
return ringbuffer_get(&rx_buf, (char*)buffer, rx_buf.avail);
}
/**
* @brief Write characters to a file
*
* All output is currently directed to UART_0, independent of the given file descriptor.
* The write call will further block until the byte is actually written to the UART.
*
* TODO: implement more sophisticated write call.
*
* @param r TODO
* @param fd TODO
* @param data TODO
* @param int TODO
*
* @return TODO
*/
int _write_r(struct _reent *r, int fd, const void *data, unsigned int count)
{
int i = 0;
while (i < count) {
uart_write_blocking(STDIO, ((char*)data)[i++]);
}
return i;
}
/**
* @brief Close a file
*
* @param r TODO
* @param fd TODO
*
* @return TODO
*/
int _close_r(struct _reent *r, int fd)
{
r->_errno = ENODEV; /* not implemented yet */
return -1;
}
/**
* @brief Set position in a file
*
* @param r TODO
* @param fd TODO
* @param pos TODO
* @param dir TODO
*
* @return TODO
*/
_off_t _lseek_r(struct _reent *r, int fd, _off_t pos, int dir)
{
r->_errno = ENODEV; /* not implemented yet */
return -1;
}
/**
* @brief Status of an open file
*
* @param r TODO
* @param fd TODO
* @param stat TODO
*
* @return TODO
*/
int _fstat_r(struct _reent *r, int fd, struct stat * st)
{
r->_errno = ENODEV; /* not implemented yet */
return -1;
}
/**
* @brief Status of a file (by name)
*
* @param r TODO
* @param name TODO
* @param stat TODO
*
* @return TODO
*/
int _stat_r(struct _reent *r, char *name, struct stat *st)
{
r->_errno = ENODEV; /* not implemented yet */
return -1;
}
/**
* @brief Query whether output stream is a terminal
*
* @param r TODO
* @param fd TODO
*
* @return TODO
*/
int _isatty_r(struct _reent *r, int fd)
{
r->_errno = 0;
return -1;
}
/**
* @brief Remove a file's directory entry
*
* @param r TODO
* @param path TODO
*
* @return TODO
*/
int _unlink_r(struct _reent *r, char* path)
{
r->_errno = ENODEV; /* not implemented yet */
return -1;
}

3
examples/ccn-lite-client/Makefile
View File

@ -29,12 +29,13 @@ QUIET ?= 1
BOARD_INSUFFICIENT_RAM := chronos msb-430h telosb wsn430-v1_3b wsn430-v1_4 z1 redbee-econotag
BOARD_BLACKLIST := arduino-due mbed_lpc1768 msb-430 pttu udoo qemu-i386 \
stm32f0discovery stm32f4discovery
stm32f0discovery stm32f3discovery stm32f4discovery
# mbed_lpc1768: see https://github.com/RIOT-OS/RIOT/issues/675
# msb-430: see https://github.com/RIOT-OS/RIOT/issues/658
# pttu: see https://github.com/RIOT-OS/RIOT/issues/659
# qemu-i386: no transceiver, yet
# stm32f0discovery: no transceiver, yet
# stm32f3discovery: no transceiver, yet
# stm32f4discovery: no transceiver, yet
# Modules to include:

3
examples/ccn-lite-relay/Makefile
View File

@ -29,12 +29,13 @@ QUIET ?= 1
BOARD_INSUFFICIENT_RAM := chronos msb-430h telosb wsn430-v1_3b wsn430-v1_4 z1 redbee-econotag
BOARD_BLACKLIST := arduino-due mbed_lpc1768 msb-430 pttu udoo qemu-i386 \
stm32f0discovery stm32f4discovery
stm32f0discovery stm32f3discovery stm32f4discovery
# mbed_lpc1768: see https://github.com/RIOT-OS/RIOT/issues/675
# msb-430: see https://github.com/RIOT-OS/RIOT/issues/658
# pttu: see https://github.com/RIOT-OS/RIOT/issues/659
# qemu-i386: no transceiver, yet
# stm32f0discovery: no transceiver, yet
# stm32f3discovery: no transceiver, yet
# stm32f4discovery: no transceiver, yet
# Modules to include:

3
examples/riot_and_cpp/Makefile
View File

@ -30,12 +30,13 @@ QUIET ?= 1
# Blacklist boards
BOARD_BLACKLIST := arduino-due avsextrem chronos mbed_lpc1768 msb-430h msba2 redbee-econotag \
telosb wsn430-v1_3b wsn430-v1_4 msb-430 pttu udoo qemu-i386 z1 stm32f0discovery \
stm32f4discovery
stm32f3discovery stm32f4discovery
# This example only works with native for now.
# msb430-based boards: msp430-g++ is not provided in mspgcc.
# (People who want use c++ can build c++ compiler from source, or get binaries from Energia http://energia.nu/)
# msba2: some changes should be applied to successfully compile c++. (_kill_r, _kill, __dso_handle)
# stm32f0discovery: g++ does not support some used flags (e.g. -mthumb...)
# stm32f3discovery: g++ does not support some used flags (e.g. -mthumb...)
# stm32f4discovery: g++ does not support some used flags (e.g. -mthumb...)
# others: untested.

3
examples/rpl_udp/Makefile
View File

@ -36,12 +36,13 @@ endif
BOARD_INSUFFICIENT_RAM := chronos msb-430h redbee-econotag telosb wsn430-v1_3b wsn430-v1_4 z1
BOARD_BLACKLIST := arduino-due mbed_lpc1768 msb-430 pttu udoo qemu-i386 stm32f0discovery \
stm32f4discovery
stm32f3discovery stm32f4discovery
# mbed_lpc1768: see https://github.com/RIOT-OS/RIOT/issues/675
# msb-430: see https://github.com/RIOT-OS/RIOT/issues/658
# pttu: see https://github.com/RIOT-OS/RIOT/issues/659
# qemu-i386: no transceiver, yet
# stm32f0discovery: no transceiver, yet
# stm32f3discovery: no transceiver, yet
# stm32f4discovery: no transceiver, yet
# Modules to include:

3
tests/bloom/Makefile
View File

@ -2,7 +2,8 @@ APPLICATION = bloom
include ../Makefile.tests_common
BOARD_INSUFFICIENT_RAM := chronos mbed_lpc1768 msb-430 msb-430h redbee-econotag \
telosb wsn430-v1_3b wsn430-v1_4 z1 stm32f0discovery
telosb wsn430-v1_3b wsn430-v1_4 z1 stm32f0discovery \
stm32f3discovery
USEMODULE += hashes
USEMODULE += bloom

2
tests/coap/Makefile
View File

@ -2,7 +2,7 @@ APPLICATION = coap
include ../Makefile.tests_common
BOARD_BLACKLIST := arduino-due chronos mbed_lpc1768 msb-430 msb-430h qemu-i386 stm32f0discovery \
stm32f4discovery telosb wsn430-v1_3b wsn430-v1_4 udoo z1
stm32f3discovery stm32f4discovery telosb wsn430-v1_3b wsn430-v1_4 udoo z1
BOARD_INSUFFICIENT_RAM := redbee-econotag
#MSP boards: no assert.h
#rest: no radio

4
tests/net_if/Makefile
View File

@ -1,8 +1,10 @@
APPLICATION = net_if
BOARD_BLACKLIST = mbed_lpc1768 arduino-due udoo qemu-i386 stm32f0discovery stm32f4discovery
BOARD_BLACKLIST = mbed_lpc1768 arduino-due udoo qemu-i386 stm32f0discovery stm32f3discovery \
stm32f4discovery
# qemu-i386: no transceiver, yet
# stm32f0discovery: no transceiver, yet
# stm32f3discovery: no transceiver, yet
# stm32f4discovery: no transceiver, yet
include ../Makefile.tests_common

3
tests/pnet/Makefile
View File

@ -3,11 +3,12 @@ include ../Makefile.tests_common
BOARD_INSUFFICIENT_RAM := chronos msb-430h redbee-econotag telosb wsn430-v1_3b wsn430-v1_4 z1
BOARD_BLACKLIST := arduino-due mbed_lpc1768 msb-430 udoo qemu-i386 stm32f0discovery \
stm32f4discovery
stm32f3discovery stm32f4discovery
# mbed_lpc1768: see https://github.com/RIOT-OS/RIOT/issues/675
# msb-430: see https://github.com/RIOT-OS/RIOT/issues/658
# qemu-i386: no transceiver, yet
# stm32f0discovery: no transceiver, yet
# stm32f3discovery: no transceiver, yet
# stm32f4discovery: no transceiver, yet
USEMODULE += posix