From 91a294aa45d48f1369b6a2b77b85a019125a05cd Mon Sep 17 00:00:00 2001 From: Marian Buschsieweke Date: Thu, 2 Jul 2020 20:39:22 +0200 Subject: [PATCH] cpu/cortexm_common: Drop LTO workaround for Cortex M thread_arch.c The `ldr r1, =sched_active_thread` instruction couldn't be assembled with LTO, as the no immediate offset could be found to construct the address of `sched_active_thread`. This commit instructs the assembler to generate a literate pool which can be used to construct the address. While this issue was only triggered during LTO, it theoretically could also pop up without LTO due to unrelated changes. Thus, it is a good idea to create the literate pool even without LTO enabled. --- cpu/cortexm_common/Makefile | 3 --- cpu/cortexm_common/thread_arch.c | 2 ++ 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/cpu/cortexm_common/Makefile b/cpu/cortexm_common/Makefile index cbf1ed7f2e..e09377cd1e 100644 --- a/cpu/cortexm_common/Makefile +++ b/cpu/cortexm_common/Makefile @@ -1,6 +1,3 @@ -# see https://github.com/RIOT-OS/RIOT/issues/5775. -SRC_NOLTO += vectors_cortexm.c - DIRS = periph include $(RIOTBASE)/Makefile.base diff --git a/cpu/cortexm_common/thread_arch.c b/cpu/cortexm_common/thread_arch.c index 40ea9eb5e7..b7ebf7fe21 100644 --- a/cpu/cortexm_common/thread_arch.c +++ b/cpu/cortexm_common/thread_arch.c @@ -372,6 +372,8 @@ void __attribute__((naked)) __attribute__((used)) isr_pendsv(void) { * causes end of exception*/ #endif /* {r0-r3,r12,LR,PC,xPSR,s0-s15,FPSCR} are restored automatically on exception return */ + ".ltorg \n" /* literal pool needed to access + * sched_active_thread */ ); }