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Merge pull request #12457 from kaspar030/update_msp430

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cpu/msp430: update to modern gcc/ELF/newlib toolchain
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Marian Buschsieweke 2020-08-05 17:46:07 +02:00 committed by GitHub
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153 changed files with 12421 additions and 5545 deletions
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12
LOSTANDFOUND.md
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@ -48,6 +48,18 @@ Reasons for removal:
- Not maintained anymore
- Not used in GNRC
### boards/chronos [f7ef85d6559eb421d3ddf313c5ad4e5c3c10c64c]
Author(s):
- Oliver Hahm <oliver.hahm@inria.fr>
- Kaspar Schleiser <kaspar@schleiser.de>
Reason for removal:
- board is quite outdated
- board cannot be automatically tested for lack of UART
- board has many special cases, which hurt upgrade to msp430-elf-gcc 9.x
- the onboard radio has been unsupported for a while
- noone seems to use the board, noone seems to maintain it
### sys/net/gnrc/application_layer/tftp [0e2a62078850e1ecc74db2db4d639cf2d8fb96d3]
Author:
- DipSwitch <dipswitch@ownage4u.nl>

15
boards/chronos/Kconfig
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@ -1,15 +0,0 @@
# Copyright (c) 2020 HAW Hamburg
#
# This file is subject to the terms and conditions of the GNU Lesser
# General Public License v2.1. See the file LICENSE in the top level
# directory for more details.
config BOARD
default "chronos" if BOARD_CHRONOS
config BOARD_CHRONOS
bool
default y
select CPU_MODEL_CC430F6137
select HAS_PERIPH_TIMER
select HAS_PERIPH_RTC

5
boards/chronos/Makefile
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@ -1,5 +0,0 @@
MODULE = board
DIRS = drivers
include $(RIOTBASE)/Makefile.base

1
boards/chronos/Makefile.dep
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@ -1 +0,0 @@
USEMODULE += chronos-drivers

8
boards/chronos/Makefile.features
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@ -1,8 +0,0 @@
CPU = cc430
CPU_MODEL = cc430f6137
# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_rtc
# Various other features (if any)

6
boards/chronos/Makefile.include
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@ -1,6 +0,0 @@
# flasher configuration
FLASHFILE ?= $(HEXFILE)
FLASHER = mspdebug
FFLAGS = rf2500 "prog $(FLASHFILE)"
INCLUDES += -I$(RIOTBOARD)/chronos/drivers/include

106
boards/chronos/board_init.c
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@ -1,106 +0,0 @@
/*
* Copyright (C) 2014 INRIA
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_chronos
* @{
*/
/**
* @file
* @brief eZ430-chronos board initialization
*
* @author Oliver Hahm <oliver.hahm@inria.fr>
* @author Ludwig Knüpfer <ludwig.knuepfer@fu-berlin.de>
*
*/
#include <stdint.h>
#include "board.h"
#include "cpu.h"
#include "irq.h"
#include "debug.h"
#include "display.h"
#include "display_putchar.h"
void cc430_cpu_init(void)
{
volatile uint16_t i;
volatile unsigned char *ptr;
/* disable watchdog */
WDTCTL = WDTPW + WDTHOLD;
// ---------------------------------------------------------------------
// Enable 32kHz ACLK
P5SEL |= 0x03; // Select XIN, XOUT on P5.0 and P5.1
UCSCTL6 &= ~XT1OFF; // XT1 On, Highest drive strength
UCSCTL6 |= XCAP_3; // Internal load cap
UCSCTL3 = SELA__XT1CLK; // Select XT1 as FLL reference
UCSCTL4 = SELA__XT1CLK | SELS__DCOCLKDIV | SELM__DCOCLKDIV;
// ---------------------------------------------------------------------
// Configure CPU clock for 12MHz
_BIS_SR(SCG0); // Disable the FLL control loop
UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx
UCSCTL1 = DCORSEL_5; // Select suitable range
UCSCTL2 = FLLD_1 + 0x16E; // Set DCO Multiplier
_BIC_SR(SCG0); // Enable the FLL control loop
// Worst-case settling time for the DCO when the DCO range bits have been
// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
// UG for optimization.
// 32 x 32 x 8 MHz / 32,768 Hz = 250000 = MCLK cycles for DCO to settle
for (i = 0xFF; i > 0; i--); // Time for flag to set
// Loop until XT1 & DCO stabilizes, use do-while to insure that
// body is executed at least once
do {
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
SFRIFG1 &= ~OFIFG; // Clear fault flags
}
while ((SFRIFG1 & OFIFG));
// Disable all interrupts
__disable_interrupt();
// Get write-access to port mapping registers:
PMAPPWD = 0x02D52;
// Allow reconfiguration during runtime:
PMAPCTL = PMAPRECFG;
// P2.7 = TA0CCR1A or TA1CCR0A output (buzzer output)
ptr = &P2MAP0;
*(ptr + 7) = PM_TA1CCR0A;
P2OUT &= ~BIT7;
P2DIR |= BIT7;
// P1.5 = SPI MISO input
ptr = &P1MAP0;
*(ptr + 5) = PM_UCA0SOMI;
// P1.6 = SPI MOSI output
*(ptr + 6) = PM_UCA0SIMO;
// P1.7 = SPI CLK output
*(ptr + 7) = PM_UCA0CLK;
// Disable write-access to port mapping registers:
PMAPPWD = 0;
// Re-enable all interrupts
irq_enable();
}
void board_init(void)
{
cc430_cpu_init();
lcd_init();
init_display_putchar();
DEBUG("DISP OK");
}

44
boards/chronos/doc.txt
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@ -1,44 +0,0 @@
/**
@defgroup boards_chronos Chronos
@ingroup boards
@brief Support for the chronos board
# Hardware
![TI eZ430-Chronos running RIOT]
(http://riot-os.org/images/hardware-watch-riot.png)
# MCU
| MCU | TI CC430F6137 |
|:----------------------------- |:--------------------- |
| Family | MSP430 |
| Vendor | Texas Instruments |
| Package | 64VQFN |
| RAM | 4KiB |
| Flash | 32KiB |
| Frequency | 20MHz |
| FPU | no |
| Timers | 2 (2x 16bit) |
| ADCs | 1x 8 channel 12-bit |
| UARTs | 1 |
| SPIs | 2 |
| I2Cs | 1 |
| Vcc | 2.0V - 3.6V |
| Datasheet / Reference Manual | [Datasheet](http://www.ti.com/lit/gpn/cc430f6137) |
| Board Manual | [User Guide](http://www.ti.com/lit/pdf/slau292)|
## Flashing RIOT
Flashing RIOT on the eZ430-Chronos is quite straight forward, just connect
your eZ430-Chronos using the USB programming dongle to your host computer and
type:
`make flash`
This should take care of everything!
# Vendor information
[TI Wiki](http://processors.wiki.ti.com/index.php/EZ430-Chronos)
[MCU information](http://www.ti.com/product/cc430f6137)
*/

3
boards/chronos/drivers/Makefile
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@ -1,3 +0,0 @@
MODULE = chronos-drivers
include $(RIOTBASE)/Makefile.base

38
boards/chronos/drivers/battery.c
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@ -1,38 +0,0 @@
/*
* Copyright (C) 2014 INRIA
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_chronos
* @{
*/
/**
* @file
* @brief eZ430-chronos battery readout (via ADC)
*
* @author Oliver Hahm <oliver.hahm@inria.fr>
* @author Ludwig Knüpfer <ludwig.knuepfer@fu-berlin.de>
*
*/
#include <stdint.h>
#include <stdint.h>
#include <cc430f6137.h>
#include "cc430-adc.h"
uint32_t battery_get_voltage(void)
{
uint32_t voltage;
voltage = adc12_single_conversion(REFVSEL_1, ADC12SHT0_10, ADC12INCH_11);
/* Ideally we have A11=0->AVCC=0V ... A11=4095(2^12-1)->AVCC=4V
* --> (A11/4095)*4V=AVCC --> AVCC=(A11*4)/4095 */
voltage = (voltage * 2 * 2 * 1000) / 4095;
return voltage;
}

54
boards/chronos/drivers/buzzer.c
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@ -1,54 +0,0 @@
/*
* Copyright (C) 2014 INRIA
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_chronos
* @{
*/
/**
* @file
* @brief eZ430-chronos beeper
*
* @author Oliver Hahm <oliver.hahm@inria.fr>
* @author Ludwig Knüpfer <ludwig.knuepfer@fu-berlin.de>
* @author mikoff
*
*/
#include <stdint.h>
#include <stdint.h>
#include <cc430f6137.h>
#include "buzzer.h"
#include "xtimer.h"
void buzzer_beep(uint8_t pitch, uint32_t duration)
{
// Reset TA1R, set up mode, TA1 runs from 32768Hz ACLK
TA1CTL = TACLR | MC_1 | TASSEL__ACLK;
// Set PWM frequency
TA1CCR0 = pitch;
// Enable IRQ, set output mode "toggle"
TA1CCTL0 = OUTMOD_4;
// Allow buzzer PWM output on P2.7
P2SEL |= BIT7;
xtimer_usleep(duration);
// Stop PWM timer
TA1CTL &= ~(BIT4 | BIT5);
// Reset and disable buzzer PWM output
P2OUT &= ~BIT7;
P2SEL &= ~BIT7;
TA1CCTL0 &= ~CCIE;
}

409
boards/chronos/drivers/display.c
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@ -1,409 +0,0 @@
/**
*
* Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/**
* @ingroup boards_chronos
* @{
*/
/**
* @file
* @brief eZ430-chronos display driver
*
* @author Oliver Hahm <oliver.hahm@inria.fr>
* @author Ludwig Knüpfer <ludwig.knuepfer@fu-berlin.de>
* @author Kaspar Schleiser <kaspar@schleiser.de>
* @author mikoff
*
*/
#include <string.h>
#include <cc430f6137.h>
#include "display.h"
void write_lcd_mem(uint8_t *lcdmem, uint8_t bits, uint8_t bitmask, uint8_t state);
void clear_line(uint8_t line);
void display_symbol(uint8_t symbol, uint8_t mode);
/** Display flags */
volatile s_display_flags_t display;
/** Global return string for itoa function */
char itoa_str[8];
void lcd_init(void)
{
/* Clear entire display memory */
LCDBMEMCTL |= LCDCLRBM + LCDCLRM;
/* LCD_FREQ = ACLK/16/8 = 256Hz */
/* Frame frequency = 256Hz/4 = 64Hz, LCD mux 4, LCD on */
LCDBCTL0 = (LCDDIV0 + LCDDIV1 + LCDDIV2 + LCDDIV3) | (LCDPRE0 + LCDPRE1) | LCD4MUX | LCDON;
/* LCB_BLK_FREQ = ACLK/8/4096 = 1Hz */
LCDBBLKCTL = LCDBLKPRE0 | LCDBLKPRE1 | LCDBLKDIV0 | LCDBLKDIV1 | LCDBLKDIV2 | LCDBLKMOD0;
/* I/O to COM outputs */
P5SEL |= (BIT5 | BIT6 | BIT7);
P5DIR |= (BIT5 | BIT6 | BIT7);
/* Activate LCD output */
LCDBPCTL0 = 0xFFFF; /* Select LCD segments S0-S15 */
LCDBPCTL1 = 0x00FF; /* Select LCD segments S16-S22 */
#ifdef USE_LCD_CHARGE_PUMP
/* Charge pump voltage generated internally, internal bias (V2-V4) generation */
LCDBVCTL = LCDCPEN | VLCD_2_72;
#endif
}
void clear_display_all(void)
{
// Clear generic content
clear_line(LINE1);
clear_line(LINE2);
}
void clear_display(void)
{
clear_line(LINE1);
clear_line(LINE2);
}
void clear_line(uint8_t line)
{
display_chars(switch_seg(line, LCD_SEG_L1_3_0, LCD_SEG_L2_5_0), NULL, SEG_OFF);
if (line == LINE1) {
display_symbol(LCD_SEG_L1_DP1, SEG_OFF);
display_symbol(LCD_SEG_L1_DP0, SEG_OFF);
display_symbol(LCD_SEG_L1_COL, SEG_OFF);
}
/* line == LINE2 */
else {
display_symbol(LCD_SEG_L2_DP, SEG_OFF);
display_symbol(LCD_SEG_L2_COL1, SEG_OFF);
display_symbol(LCD_SEG_L2_COL0, SEG_OFF);
}
}
void write_lcd_mem(uint8_t *lcdmem, uint8_t bits, uint8_t bitmask, uint8_t state)
{
if (state == SEG_ON) {
/* Clear segments before writing */
*lcdmem = (uint8_t)(*lcdmem & ~bitmask);
/* Set visible segments */
*lcdmem = (uint8_t)(*lcdmem | bits);
}
else if (state == SEG_OFF) {
/* Clear segments */
*lcdmem = (uint8_t)(*lcdmem & ~bitmask);
}
else if (state == SEG_ON_BLINK_ON) {
/* Clear visible / blink segments before writing */
*lcdmem = (uint8_t)(*lcdmem & ~bitmask);
*(lcdmem + 0x20) = (uint8_t)(*(lcdmem + 0x20) & ~bitmask);
/* Set visible / blink segments */
*lcdmem = (uint8_t)(*lcdmem | bits);
*(lcdmem + 0x20) = (uint8_t)(*(lcdmem + 0x20) | bits);
}
else if (state == SEG_ON_BLINK_OFF) {
/* Clear visible segments before writing */
*lcdmem = (uint8_t)(*lcdmem & ~bitmask);
/* Set visible segments */
*lcdmem = (uint8_t)(*lcdmem | bits);
/* Clear blink segments */
*(lcdmem + 0x20) = (uint8_t)(*(lcdmem + 0x20) & ~bitmask);
}
else if (state == SEG_OFF_BLINK_OFF) {
/* Clear segments */
*lcdmem = (uint8_t)(*lcdmem & ~bitmask);
/* Clear blink segments */
*(lcdmem + 0x20) = (uint8_t)(*(lcdmem + 0x20) & ~bitmask);
}
}
char *itoa(uint32_t n, uint8_t digits, uint8_t blanks)
{
uint8_t digits1 = digits;
/* Preset result string */
memcpy(itoa_str, "0000000", 7);
/* Return empty string if number of digits is invalid (valid range for digits: 1-7) */
if ((digits == 0) || (digits > 7)) {
return (itoa_str);
}
/* Numbers 0 .. 180 can be copied from itoa_conversion_table without conversion */
if (n <= 180) {
if (digits >= 3) {
memcpy(itoa_str + (digits - 3), itoa_conversion_table[n], 3);
}
/* digits == 1 || 2 */
else {
memcpy(itoa_str, itoa_conversion_table[n] + (3 - digits), digits);
}
}
/* For n > 180 need to calculate string content */
else {
/* Calculate digits from least to most significant number */
do {
itoa_str[digits - 1] = n % 10 + '0';
n /= 10;
}
while (--digits > 0);
}
/* Remove specified number of leading '0', always keep last one */
uint8_t i = 0;
while ((i < digits1 - 1) && (itoa_str[i] == '0')) {
if (blanks > 0) {
/* Convert only specified number of leading '0' */
itoa_str[i] = ' ';
blanks--;
}
i++;
}
return (itoa_str);
}
void display_value1(uint8_t segments, uint32_t value, uint8_t digits, uint8_t blanks, uint8_t disp_mode)
{
char *str;
str = itoa(value, digits, blanks);
/* Display string in blink mode */
display_chars(segments, str, disp_mode);
}
void display_symbol(uint8_t symbol, uint8_t mode)
{
if (symbol <= LCD_SEG_L2_DP) {
/* Get LCD memory address for symbol from table */
uint8_t *lcdmem = (uint8_t *)segments_lcdmem[symbol];
/* Get bits for symbol from table */
uint8_t bits = segments_bitmask[symbol];
/* Bitmask for symbols equals bits */
uint8_t bitmask = bits;
/* Write LCD memory */
write_lcd_mem(lcdmem, bits, bitmask, mode);
}
}
void display_char(uint8_t segment, char chr, uint8_t mode)
{
/* Write to single 7-segment character */
if ((segment >= LCD_SEG_L1_3) && (segment <= LCD_SEG_L2_DP)) {
uint8_t bits; /* Bits to write */
/* Get LCD memory address for segment from table */
uint8_t *lcdmem = (uint8_t *)segments_lcdmem[segment];
/* Get bitmask for character from table */
uint8_t bitmask = segments_bitmask[segment];
/* Get bits from font set */
if ((chr >= 0x30) && (chr <= 0x5A)) {
/* Use font set */
bits = lcd_font[chr - 0x30];
}
else if (chr == 0x2D) {
/* '-' not in font set */
bits = BIT1;
}
else {
/* Other characters map to ' ' (blank) */
bits = 0;
}
/* When addressing LINE2 7-segment characters need to swap high- and low-nibble, */
/* because LCD COM/SEG assignment is mirrored against LINE1 */
if (segment >= LCD_SEG_L2_5) {
uint8_t bits1 = ((bits << 4) & 0xF0) | ((bits >> 4) & 0x0F);
bits = bits1;
/* When addressing LCD_SEG_L2_5, need to convert ASCII '1' and 'L' to 1 bit, */
/* because LCD COM/SEG assignment is special for this incomplete character */
if (segment == LCD_SEG_L2_5) {
if ((chr == '1') || (chr == 'L')) {
bits = BIT7;
}
}
}
/* Physically write to LCD memory */
write_lcd_mem(lcdmem, bits, bitmask, mode);
}
}
void display_chars(uint8_t segments, char *str, uint8_t mode)
{
uint8_t length = 0; /* Write length */
uint8_t char_start = 0; /* Starting point for consecutive write */
switch (segments) {
/* LINE1 */
case LCD_SEG_L1_3_0:
length = 4;
char_start = LCD_SEG_L1_3;
break;
case LCD_SEG_L1_2_0:
length = 3;
char_start = LCD_SEG_L1_2;
break;
case LCD_SEG_L1_1_0:
length = 2;
char_start = LCD_SEG_L1_1;
break;
case LCD_SEG_L1_3_1:
length = 3;
char_start = LCD_SEG_L1_3;
break;
case LCD_SEG_L1_3_2:
length = 2;
char_start = LCD_SEG_L1_3;
break;
/* LINE2 */
case LCD_SEG_L2_5_0:
length = 6;
char_start = LCD_SEG_L2_5;
break;
case LCD_SEG_L2_4_0:
length = 5;
char_start = LCD_SEG_L2_4;
break;
case LCD_SEG_L2_3_0:
length = 4;
char_start = LCD_SEG_L2_3;
break;
case LCD_SEG_L2_2_0:
length = 3;
char_start = LCD_SEG_L2_2;
break;
case LCD_SEG_L2_1_0:
length = 2;
char_start = LCD_SEG_L2_1;
break;
case LCD_SEG_L2_5_4:
length = 2;
char_start = LCD_SEG_L2_5;
break;
case LCD_SEG_L2_5_2:
length = 4;
char_start = LCD_SEG_L2_5;
break;
case LCD_SEG_L2_3_2:
length = 2;
char_start = LCD_SEG_L2_3;
break;
case LCD_SEG_L2_4_2:
length = 3;
char_start = LCD_SEG_L2_4;
break;
}
/* Write to consecutive digits */
for (uint8_t i = 0; i < length; i++) {
/* Use single character routine to write display memory */
display_char(char_start + i, *(str + i), mode);
}
}
uint8_t switch_seg(uint8_t line, uint8_t index1, uint8_t index2)
{
if (line == LINE1) {
return index1;
}
/* line == LINE2 */
else {
return index2;
}
}
void start_blink(void)
{
LCDBBLKCTL |= LCDBLKMOD0;
}
void stop_blink(void)
{
LCDBBLKCTL &= ~LCDBLKMOD0;
}
void clear_blink_mem(void)
{
LCDBMEMCTL |= LCDCLRBM;
}
void set_blink_rate(uint8_t bits)
{
LCDBBLKCTL &= ~(BIT7 | BIT6 | BIT5);
LCDBBLKCTL |= bits;
}
void display_all_off(void)
{
uint8_t *lcdptr = (uint8_t *)0x0A20;
for (uint8_t i = 1; i <= 12; i++) {
*lcdptr = 0x00;
lcdptr++;
}
}

218
boards/chronos/drivers/display_chars.c
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@ -1,218 +0,0 @@
/* *************************************************************************************************
*
* Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ************************************************************************************************/
/* Basic display functions. */
/* ************************************************************************************************* */
/**
* @file
* @brief eZ430-chronos display driver character tables
*
* @author Oliver Hahm <oliver.hahm@inria.fr>
* @author Kaspar Schleiser <kaspar@schleiser.de>
*
*/
/* ************************************************************************************************* */
/* Include section */
#include <stdint.h>
#include <cc430f6137.h>
#include "display.h"
/* ************************************************************************************************* */
/* Global Variable section */
/* Table with memory bit assignment for digits "0" to "9" and characters "A" to "Z" */
/* A */
/* F B */
/* G */
/* E C */
/* D */
const uint8_t lcd_font[] = {
SEG_A + SEG_B + SEG_C + SEG_D + SEG_E + SEG_F, /* Displays "0" */
SEG_B + SEG_C, /* Displays "1" */
SEG_A + SEG_B + SEG_D + SEG_E + SEG_G, /* Displays "2" */
SEG_A + SEG_B + SEG_C + SEG_D + SEG_G, /* Displays "3" */
SEG_B + SEG_C + SEG_F + SEG_G, /* Displays "4" */
SEG_A + SEG_C + SEG_D + SEG_F + SEG_G, /* Displays "5" */
SEG_A + SEG_C + SEG_D + SEG_E + SEG_F + SEG_G, /* Displays "6" */
SEG_A + SEG_B + SEG_C, /* Displays "7" */
SEG_A + SEG_B + SEG_C + SEG_D + SEG_E + SEG_F + SEG_G, /* Displays "8" */
SEG_A + SEG_B + SEG_C + SEG_D + SEG_F + SEG_G, /* Displays "9" */
0, /* Displays " " (:) */
0, /* Displays " " (;) */
SEG_A + SEG_F + SEG_G, /* Displays "<" as high c */
SEG_D + SEG_G, /* Displays "=" */
0, /* Displays " " (>) */
SEG_A + SEG_B + SEG_E + SEG_G, /* Displays "?" */
0, /* Displays " " (@) */
SEG_A + SEG_B + SEG_C + SEG_E + SEG_F + SEG_G, /* Displays "A" */
SEG_C + SEG_D + SEG_E + SEG_F + SEG_G, /* Displays "b" */
SEG_D + SEG_E + SEG_G, /* Displays "c" */
SEG_B + SEG_C + SEG_D + SEG_E + SEG_G, /* Displays "d" */
SEG_A + SEG_D + SEG_E + SEG_F + SEG_G, /* Displays "E" */
SEG_A + SEG_E + SEG_F + SEG_G, /* Displays "f" */
SEG_A + SEG_B + SEG_C + SEG_D + SEG_F + SEG_G, /* Displays "g" same as 9 */
SEG_C + SEG_E + SEG_F + SEG_G, /* Displays "h" */
SEG_E, /* Displays "i" */
SEG_A + SEG_B + SEG_C + SEG_D, /* Displays "J" */
SEG_D + SEG_F + SEG_G, /* Displays "k" */
SEG_D + SEG_E + SEG_F, /* Displays "L" */
SEG_A + SEG_B + SEG_C + SEG_E + SEG_F, /* Displays "M" */
SEG_C + SEG_E + SEG_G, /* Displays "n" */
SEG_C + SEG_D + SEG_E + SEG_G, /* Displays "o" */
SEG_A + SEG_B + SEG_E + SEG_F + SEG_G, /* Displays "P" */
SEG_A + SEG_B + SEG_C + SEG_F + SEG_G, /* Displays "q" */
SEG_E + SEG_G, /* Displays "r" */
SEG_A + SEG_C + SEG_D + SEG_F + SEG_G, /* Displays "S" same as 5 */
SEG_D + SEG_E + SEG_F + SEG_G, /* Displays "t" */
SEG_C + SEG_D + SEG_E, /* Displays "u" */
SEG_C + SEG_D + SEG_E, /* Displays "v" same as u */
SEG_B + SEG_C + SEG_D + SEG_E + SEG_F + SEG_G, /* Displays "W" */
SEG_B + SEG_C + SEG_E + SEG_F + SEG_G, /* Displays "X" as H */
SEG_B + SEG_C + SEG_D + SEG_F + SEG_G, /* Displays "Y" */
SEG_A + SEG_B + SEG_D + SEG_E + SEG_G, /* Displays "Z" same as 2 */
};
/* Table with memory address for each display element */
const uint8_t *segments_lcdmem[] = {
LCD_SYMB_AM_MEM,
LCD_SYMB_PM_MEM,
LCD_SYMB_ARROW_UP_MEM,
LCD_SYMB_ARROW_DOWN_MEM,
LCD_SYMB_PERCENT_MEM,
LCD_SYMB_TOTAL_MEM,
LCD_SYMB_AVERAGE_MEM,
LCD_SYMB_MAX_MEM,
LCD_SYMB_BATTERY_MEM,
LCD_UNIT_L1_FT_MEM,
LCD_UNIT_L1_K_MEM,
LCD_UNIT_L1_M_MEM,
LCD_UNIT_L1_I_MEM,
LCD_UNIT_L1_PER_S_MEM,
LCD_UNIT_L1_PER_H_MEM,
LCD_UNIT_L1_DEGREE_MEM,
LCD_UNIT_L2_KCAL_MEM,
LCD_UNIT_L2_KM_MEM,
LCD_UNIT_L2_MI_MEM,
LCD_ICON_HEART_MEM,
LCD_ICON_STOPWATCH_MEM,
LCD_ICON_RECORD_MEM,
LCD_ICON_ALARM_MEM,
LCD_ICON_BEEPER1_MEM,
LCD_ICON_BEEPER2_MEM,
LCD_ICON_BEEPER3_MEM,
LCD_SEG_L1_3_MEM,
LCD_SEG_L1_2_MEM,
LCD_SEG_L1_1_MEM,
LCD_SEG_L1_0_MEM,
LCD_SEG_L1_COL_MEM,
LCD_SEG_L1_DP1_MEM,
LCD_SEG_L1_DP0_MEM,
LCD_SEG_L2_5_MEM,
LCD_SEG_L2_4_MEM,
LCD_SEG_L2_3_MEM,
LCD_SEG_L2_2_MEM,
LCD_SEG_L2_1_MEM,
LCD_SEG_L2_0_MEM,
LCD_SEG_L2_COL1_MEM,
LCD_SEG_L2_COL0_MEM,
LCD_SEG_L2_DP_MEM,
};
/* Table with bit mask for each display element */
const uint8_t segments_bitmask[] = {
LCD_SYMB_AM_MASK,
LCD_SYMB_PM_MASK,
LCD_SYMB_ARROW_UP_MASK,
LCD_SYMB_ARROW_DOWN_MASK,
LCD_SYMB_PERCENT_MASK,
LCD_SYMB_TOTAL_MASK,
LCD_SYMB_AVERAGE_MASK,
LCD_SYMB_MAX_MASK,
LCD_SYMB_BATTERY_MASK,
LCD_UNIT_L1_FT_MASK,
LCD_UNIT_L1_K_MASK,
LCD_UNIT_L1_M_MASK,
LCD_UNIT_L1_I_MASK,
LCD_UNIT_L1_PER_S_MASK,
LCD_UNIT_L1_PER_H_MASK,
LCD_UNIT_L1_DEGREE_MASK,
LCD_UNIT_L2_KCAL_MASK,
LCD_UNIT_L2_KM_MASK,
LCD_UNIT_L2_MI_MASK,
LCD_ICON_HEART_MASK,
LCD_ICON_STOPWATCH_MASK,
LCD_ICON_RECORD_MASK,
LCD_ICON_ALARM_MASK,
LCD_ICON_BEEPER1_MASK,
LCD_ICON_BEEPER2_MASK,
LCD_ICON_BEEPER3_MASK,
LCD_SEG_L1_3_MASK,
LCD_SEG_L1_2_MASK,
LCD_SEG_L1_1_MASK,
LCD_SEG_L1_0_MASK,
LCD_SEG_L1_COL_MASK,
LCD_SEG_L1_DP1_MASK,
LCD_SEG_L1_DP0_MASK,
LCD_SEG_L2_5_MASK,
LCD_SEG_L2_4_MASK,
LCD_SEG_L2_3_MASK,
LCD_SEG_L2_2_MASK,
LCD_SEG_L2_1_MASK,
LCD_SEG_L2_0_MASK,
LCD_SEG_L2_COL1_MASK,
LCD_SEG_L2_COL0_MASK,
LCD_SEG_L2_DP_MASK,
};
/* Quick integer to array conversion table for most common integer values
* discarding this would save aprox. 600 bytes codespace but increase cpu time
* for displaying values */
const uint8_t itoa_conversion_table[][3] = {
"000", "001", "002", "003", "004", "005", "006", "007", "008", "009", "010", "011", "012", "013", "014", "015",
"016", "017", "018", "019", "020", "021", "022", "023", "024", "025", "026", "027", "028", "029", "030", "031",
"032", "033", "034", "035", "036", "037", "038", "039", "040", "041", "042", "043", "044", "045", "046", "047",
"048", "049", "050", "051", "052", "053", "054", "055", "056", "057", "058", "059", "060", "061", "062", "063",
"064", "065", "066", "067", "068", "069", "070", "071", "072", "073", "074", "075", "076", "077", "078", "079",
"080", "081", "082", "083", "084", "085", "086", "087", "088", "089", "090", "091", "092", "093", "094", "095",
"096", "097", "098", "099", "100", "101", "102", "103", "104", "105", "106", "107", "108", "109", "110", "111",
"112", "113", "114", "115", "116", "117", "118", "119", "120", "121", "122", "123", "124", "125", "126", "127",
"128", "129", "130", "131", "132", "133", "134", "135", "136", "137", "138", "139", "140", "141", "142", "143",
"144", "145", "146", "147", "148", "149", "150", "151", "152", "153", "154", "155", "156", "157", "158", "159",
"160", "161", "162", "163", "164", "165", "166", "167", "168", "169", "170", "171", "172", "173", "174", "175",
"176", "177", "178", "179", "180",
};

70
boards/chronos/drivers/display_putchar.c
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/*
* Copyright (C) 2014 INRIA
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_chronos
* @{
*/
/**
* @file
* @brief eZ430-chronos putchar via display implementation
*
* @author Oliver Hahm <oliver.hahm@inria.fr>
* @author Kaspar Schleiser <kaspar@schleiser.de>
* @author Ludwig Knüpfer <ludwig.knuepfer@fu-berlin.de>
* @author Aleksandr Mikoff <sir.enmity@gmail.com>
*
*/
#include <stdio.h>
#include <string.h>
#include <ctype.h>
#include "display.h"
extern void (*_putchar)(int c);
static char display_buf[11];
void putchar_to_display(int c);
void init_display_putchar(void)
{
memset(display_buf, '\0', 11);
_putchar = putchar_to_display;
}
void putchar_to_display(int c)
{
if (c == '\n') {
display_buf[4] = 1;
return;
}
if (display_buf[4]) {
memset(display_buf, '\0', 11);
}
else {
display_buf[0] = display_buf[1];
display_buf[1] = display_buf[2];
display_buf[2] = display_buf[3];
display_buf[3] = display_buf[5];
display_buf[5] = display_buf[6];
display_buf[6] = display_buf[7];
display_buf[7] = display_buf[8];
display_buf[8] = display_buf[9];
}
display_buf[9] = toupper(c);
clear_display_all();
display_chars(LCD_SEG_L1_3_0, display_buf, SEG_ON);
display_chars(LCD_SEG_L2_5_0, display_buf + 4, SEG_ON);
}

22
boards/chronos/drivers/include/battery.h
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/*
* Copyright 2014 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
#ifndef BATTERY_H
#define BATTERY_H
#ifdef __cplusplus
extern "C" {
#endif
uint32_t battery_get_voltage(void);
#ifdef __cplusplus
}
#endif
#endif /* BATTERY_H */

24
boards/chronos/drivers/include/buzzer.h
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/*
* Copyright 2014 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
#ifndef BUZZER_H
#define BUZZER_H
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
void buzzer_beep(uint8_t pitch, uint32_t duration);
#ifdef __cplusplus
}
#endif
#endif /* BUZZER_H */

466
boards/chronos/drivers/include/display.h
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/* *************************************************************************************************
*
* Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* *************************************************************************************************
* Basic display functions.
* ************************************************************************************************/
#ifndef DISPLAY_H
#define DISPLAY_H
#ifdef __cplusplus
extern "C" {
#endif
#define CLOCK_24HR (0)
#define CLOCK_AM_PM (1)
#define CLOCK_DISPLAY_SELECT (2)
/* *************************************************************************************************
* Global Variable section */
/** Set of display flags */
typedef union {
struct {
/* Line1 + Line2 + Icons*/
uint16_t full_update : 1; /**< 1 = Redraw all content */
uint16_t partial_update : 1; /**< 1 = Update changes */
/* Line only */
uint16_t line1_full_update : 1; /**< 1 = Redraw Line1 content */
uint16_t line2_full_update : 1; /**< 1 = Redraw Line2 content */
/* Logic module data update flags */
uint16_t update_time : 1; /**< 1 = Time was updated */
uint16_t update_stopwatch : 1; /**< 1 = Stopwatch was updated */
uint16_t update_temperature : 1; /**< 1 = Temperature was updated */
uint16_t update_battery_voltage : 1; /**< 1 = Battery voltage was updated */
uint16_t update_date : 1; /**< 1 = Date was updated */
uint16_t update_alarm : 1; /**< 1 = Alarm time was updated */
uint16_t update_acceleration : 1; /**< 1 = Acceleration data was updated */
} flag; /**< Bitfield for the display flags */
uint16_t all_flags; /**< Shortcut to all display flags (for reset) */
} s_display_flags_t;
extern volatile s_display_flags_t display;
/* Constants defined in library */
extern const uint8_t lcd_font[];
extern const uint8_t *segments_lcdmem[];
extern const uint8_t segments_bitmask[];
extern const uint8_t itoa_conversion_table[][3];
/* ************************************************************************************************* */
/* Defines section */
/* Display function modes */
#define DISPLAY_LINE_UPDATE_FULL (BIT0)
#define DISPLAY_LINE_UPDATE_PARTIAL (BIT1)
#define DISPLAY_LINE_CLEAR (BIT2)
/* Definitions for line view style */
#define DISPLAY_DEFAULT_VIEW (0u)
#define DISPLAY_ALTERNATIVE_VIEW (1u)
#define DISPLAY_ALTERNATIVE2_VIEW (2u)
/* Definitions for line access */
#define LINE1 (1u)
#define LINE2 (2u)
/* LCD display modes */
#define SEG_OFF (0u)
#define SEG_ON (1u)
#define SEG_ON_BLINK_ON (2u)
#define SEG_ON_BLINK_OFF (3u)
#define SEG_OFF_BLINK_OFF (4u)
/* 7-segment character bit assignments */
#define SEG_A (BIT4)
#define SEG_B (BIT5)
#define SEG_C (BIT6)
#define SEG_D (BIT7)
#define SEG_E (BIT2)
#define SEG_F (BIT0)
#define SEG_G (BIT1)
/* ------------------------------------------
* LCD symbols for easier access
*
* xxx_SEG_xxx = Seven-segment character (sequence 5-4-3-2-1-0)
* xxx_SYMB_xxx = Display symbol, e.g. "AM" for ante meridiem
* xxx_UNIT_xxx = Display unit, e.g. "km/h" for kilometers per hour
* xxx_ICON_xxx = Display icon, e.g. heart to indicate reception of heart rate data
* xxx_L1_xxx = Item is part of Line1 information
* xxx_L2_xxx = Item is part of Line2 information
*/
//* Symbols for Line1 */
#define LCD_SYMB_AM 0
#define LCD_SYMB_PM 1
#define LCD_SYMB_ARROW_UP 2
#define LCD_SYMB_ARROW_DOWN 3
#define LCD_SYMB_PERCENT 4
/* Symbols for Line2 */
#define LCD_SYMB_TOTAL 5
#define LCD_SYMB_AVERAGE 6
#define LCD_SYMB_MAX 7
#define LCD_SYMB_BATTERY 8
/* Units for Line1 */
#define LCD_UNIT_L1_FT 9
#define LCD_UNIT_L1_K 10
#define LCD_UNIT_L1_M 11
#define LCD_UNIT_L1_I 12
#define LCD_UNIT_L1_PER_S 13
#define LCD_UNIT_L1_PER_H 14
#define LCD_UNIT_L1_DEGREE 15
/* Units for Line2 */
#define LCD_UNIT_L2_KCAL 16
#define LCD_UNIT_L2_KM 17
#define LCD_UNIT_L2_MI 18
/* Icons */
#define LCD_ICON_HEART 19
#define LCD_ICON_STOPWATCH 20
#define LCD_ICON_RECORD 21
#define LCD_ICON_ALARM 22
#define LCD_ICON_BEEPER1 23
#define LCD_ICON_BEEPER2 24
#define LCD_ICON_BEEPER3 25
/* Line1 7-segments */
#define LCD_SEG_L1_3 26
#define LCD_SEG_L1_2 27
#define LCD_SEG_L1_1 28
#define LCD_SEG_L1_0 29
#define LCD_SEG_L1_COL 30
#define LCD_SEG_L1_DP1 31
#define LCD_SEG_L1_DP0 32
/* Line2 7-segments */
#define LCD_SEG_L2_5 33
#define LCD_SEG_L2_4 34
#define LCD_SEG_L2_3 35
#define LCD_SEG_L2_2 36
#define LCD_SEG_L2_1 37
#define LCD_SEG_L2_0 38
#define LCD_SEG_L2_COL1 39
#define LCD_SEG_L2_COL0 40
#define LCD_SEG_L2_DP 41
/* Line1 7-segment arrays */
#define LCD_SEG_L1_3_0 70
#define LCD_SEG_L1_2_0 71
#define LCD_SEG_L1_1_0 72
#define LCD_SEG_L1_3_1 73
#define LCD_SEG_L1_3_2 74
/* Line2 7-segment arrays */
#define LCD_SEG_L2_5_0 90
#define LCD_SEG_L2_4_0 91
#define LCD_SEG_L2_3_0 92
#define LCD_SEG_L2_2_0 93
#define LCD_SEG_L2_1_0 94
#define LCD_SEG_L2_5_2 95
#define LCD_SEG_L2_3_2 96
#define LCD_SEG_L2_5_4 97
#define LCD_SEG_L2_4_2 98
/* LCD controller memory map */
#define LCD_MEM_1 ((uint8_t*)0x0A20)
#define LCD_MEM_2 ((uint8_t*)0x0A21)
#define LCD_MEM_3 ((uint8_t*)0x0A22)
#define LCD_MEM_4 ((uint8_t*)0x0A23)
#define LCD_MEM_5 ((uint8_t*)0x0A24)
#define LCD_MEM_6 ((uint8_t*)0x0A25)
#define LCD_MEM_7 ((uint8_t*)0x0A26)
#define LCD_MEM_8 ((uint8_t*)0x0A27)
#define LCD_MEM_9 ((uint8_t*)0x0A28)
#define LCD_MEM_10 ((uint8_t*)0x0A29)
#define LCD_MEM_11 ((uint8_t*)0x0A2A)
#define LCD_MEM_12 ((uint8_t*)0x0A2B)
/* Memory assignment */
#define LCD_SEG_L1_0_MEM (LCD_MEM_6)
#define LCD_SEG_L1_1_MEM (LCD_MEM_4)
#define LCD_SEG_L1_2_MEM (LCD_MEM_3)
#define LCD_SEG_L1_3_MEM (LCD_MEM_2)
#define LCD_SEG_L1_COL_MEM (LCD_MEM_1)
#define LCD_SEG_L1_DP1_MEM (LCD_MEM_1)
#define LCD_SEG_L1_DP0_MEM (LCD_MEM_5)
#define LCD_SEG_L2_0_MEM (LCD_MEM_8)
#define LCD_SEG_L2_1_MEM (LCD_MEM_9)
#define LCD_SEG_L2_2_MEM (LCD_MEM_10)
#define LCD_SEG_L2_3_MEM (LCD_MEM_11)
#define LCD_SEG_L2_4_MEM (LCD_MEM_12)
#define LCD_SEG_L2_5_MEM (LCD_MEM_12)
#define LCD_SEG_L2_COL1_MEM (LCD_MEM_1)
#define LCD_SEG_L2_COL0_MEM (LCD_MEM_5)
#define LCD_SEG_L2_DP_MEM (LCD_MEM_9)
#define LCD_SYMB_AM_MEM (LCD_MEM_1)
#define LCD_SYMB_PM_MEM (LCD_MEM_1)
#define LCD_SYMB_ARROW_UP_MEM (LCD_MEM_1)
#define LCD_SYMB_ARROW_DOWN_MEM (LCD_MEM_1)
#define LCD_SYMB_PERCENT_MEM (LCD_MEM_5)
#define LCD_SYMB_TOTAL_MEM (LCD_MEM_11)
#define LCD_SYMB_AVERAGE_MEM (LCD_MEM_10)
#define LCD_SYMB_MAX_MEM (LCD_MEM_8)
#define LCD_SYMB_BATTERY_MEM (LCD_MEM_7)
#define LCD_UNIT_L1_FT_MEM (LCD_MEM_5)
#define LCD_UNIT_L1_K_MEM (LCD_MEM_5)
#define LCD_UNIT_L1_M_MEM (LCD_MEM_7)
#define LCD_UNIT_L1_I_MEM (LCD_MEM_7)
#define LCD_UNIT_L1_PER_S_MEM (LCD_MEM_5)
#define LCD_UNIT_L1_PER_H_MEM (LCD_MEM_7)
#define LCD_UNIT_L1_DEGREE_MEM (LCD_MEM_5)
#define LCD_UNIT_L2_KCAL_MEM (LCD_MEM_7)
#define LCD_UNIT_L2_KM_MEM (LCD_MEM_7)
#define LCD_UNIT_L2_MI_MEM (LCD_MEM_7)
#define LCD_ICON_HEART_MEM (LCD_MEM_2)
#define LCD_ICON_STOPWATCH_MEM (LCD_MEM_3)
#define LCD_ICON_RECORD_MEM (LCD_MEM_1)
#define LCD_ICON_ALARM_MEM (LCD_MEM_4)
#define LCD_ICON_BEEPER1_MEM (LCD_MEM_5)
#define LCD_ICON_BEEPER2_MEM (LCD_MEM_6)
#define LCD_ICON_BEEPER3_MEM (LCD_MEM_7)
/* Bit masks for write access */
#define LCD_SEG_L1_0_MASK (BIT2+BIT1+BIT0+BIT7+BIT6+BIT5+BIT4)
#define LCD_SEG_L1_1_MASK (BIT2+BIT1+BIT0+BIT7+BIT6+BIT5+BIT4)
#define LCD_SEG_L1_2_MASK (BIT2+BIT1+BIT0+BIT7+BIT6+BIT5+BIT4)
#define LCD_SEG_L1_3_MASK (BIT2+BIT1+BIT0+BIT7+BIT6+BIT5+BIT4)
#define LCD_SEG_L1_COL_MASK (BIT5)
#define LCD_SEG_L1_DP1_MASK (BIT6)
#define LCD_SEG_L1_DP0_MASK (BIT2)
#define LCD_SEG_L2_0_MASK (BIT3+BIT2+BIT1+BIT0+BIT6+BIT5+BIT4)
#define LCD_SEG_L2_1_MASK (BIT3+BIT2+BIT1+BIT0+BIT6+BIT5+BIT4)
#define LCD_SEG_L2_2_MASK (BIT3+BIT2+BIT1+BIT0+BIT6+BIT5+BIT4)
#define LCD_SEG_L2_3_MASK (BIT3+BIT2+BIT1+BIT0+BIT6+BIT5+BIT4)
#define LCD_SEG_L2_4_MASK (BIT3+BIT2+BIT1+BIT0+BIT6+BIT5+BIT4)
#define LCD_SEG_L2_5_MASK (BIT7)
#define LCD_SEG_L2_COL1_MASK (BIT4)
#define LCD_SEG_L2_COL0_MASK (BIT0)
#define LCD_SEG_L2_DP_MASK (BIT7)
#define LCD_SYMB_AM_MASK (BIT1+BIT0)
#define LCD_SYMB_PM_MASK (BIT0)
#define LCD_SYMB_ARROW_UP_MASK (BIT2)
#define LCD_SYMB_ARROW_DOWN_MASK (BIT3)
#define LCD_SYMB_PERCENT_MASK (BIT4)
#define LCD_SYMB_TOTAL_MASK (BIT7)
#define LCD_SYMB_AVERAGE_MASK (BIT7)
#define LCD_SYMB_MAX_MASK (BIT7)
#define LCD_SYMB_BATTERY_MASK (BIT7)
#define LCD_UNIT_L1_FT_MASK (BIT5)
#define LCD_UNIT_L1_K_MASK (BIT6)
#define LCD_UNIT_L1_M_MASK (BIT1)
#define LCD_UNIT_L1_I_MASK (BIT0)
#define LCD_UNIT_L1_PER_S_MASK (BIT7)
#define LCD_UNIT_L1_PER_H_MASK (BIT2)
#define LCD_UNIT_L1_DEGREE_MASK (BIT1)
#define LCD_UNIT_L2_KCAL_MASK (BIT4)
#define LCD_UNIT_L2_KM_MASK (BIT5)
#define LCD_UNIT_L2_MI_MASK (BIT6)
#define LCD_ICON_HEART_MASK (BIT3)
#define LCD_ICON_STOPWATCH_MASK (BIT3)
#define LCD_ICON_RECORD_MASK (BIT7)
#define LCD_ICON_ALARM_MASK (BIT3)
#define LCD_ICON_BEEPER1_MASK (BIT3)
#define LCD_ICON_BEEPER2_MASK (BIT3)
#define LCD_ICON_BEEPER3_MASK (BIT3)
/* *************************************************************************************************
* API section
*/
/* Physical LCD memory write */
/* *************************************************************************************************
* @fn write_segment
* @brief Write to one or multiple LCD segments
* @param lcdmem Pointer to LCD byte memory
* bits Segments to address
* bitmask Bitmask for particular display item
* mode On, off or blink segments
* @return
* ************************************************************************************************/
void write_lcd_mem(uint8_t *lcdmem, uint8_t bits, uint8_t bitmask, uint8_t state);
/* Display init / clear */
/* *************************************************************************************************
* @fn lcd_init
* @brief Erase LCD memory. Init LCD peripheral.
* @param none
* @return none
* ************************************************************************************************/
void lcd_init(void);
/* *************************************************************************************************
* @fn clear_display
* @brief Erase LINE1 and LINE2 segments. Keep icons.
* @param none
* @return none
* ************************************************************************************************/
void clear_display(void);
/* *************************************************************************************************
* @fn clear_display_all
* @brief Erase LINE1 and LINE2 segments. Clear also function-specific content.
* @param none
* @return none
* ************************************************************************************************/
void clear_display_all(void);
/* *************************************************************************************************
* @fn clear_line
* @brief Erase segments of a given line.
* @param uint8_t line LINE1, LINE2
* @return none
* ************************************************************************************************/
void clear_line(uint8_t line);
/* Blinking function */
/* *************************************************************************************************
* @fn start_blink
* @brief Start blinking.
* @param none
* @return none
* ************************************************************************************************/
void start_blink(void);
/* *************************************************************************************************
* @fn stop_blink
* @brief Stop blinking.
* @param none
* @return none
* ************************************************************************************************/
void stop_blink(void);
/* *************************************************************************************************
* @fn stop_blink
* @brief Clear blinking memory.
* @param none
* @return none
* ************************************************************************************************/
void clear_blink_mem(void);
/* *************************************************************************************************
* @fn set_blink_rate
* @brief Set blink rate register bits.
* @param none
* @return none
* ************************************************************************************************/
void set_blink_rate(uint8_t bits);
/* Character / symbol draw functions */
/* *************************************************************************************************
* @fn display_char
* @brief Write to 7-segment characters.
* @param uint8_t segment A valid LCD segment
* uint8_t chr Character to display
* uint8_t mode SEG_ON, SEG_OFF, SEG_BLINK
* @return none
* ************************************************************************************************/
void display_char(uint8_t segment, char chr, uint8_t mode);
/* *************************************************************************************************
* @FN display_chars
* @brief Write to consecutive 7-segment characters.
* @param uint8_t segments LCD segment array
* uint8_t * str Pointer to a string
* uint8_t mode SEG_ON, SEG_OFF, SEG_BLINK
* @return none
* ************************************************************************************************/
void display_chars(uint8_t segments, char *str, uint8_t mode);
/* *************************************************************************************************
* @fn display_symbol
* @brief Switch symbol on or off on LCD.
* @param uint8_t symbol A valid LCD symbol (index 0..42)
* uint8_t state SEG_ON, SEG_OFF, SEG_BLINK
* @return none
* ************************************************************************************************/
void display_symbol(uint8_t symbol, uint8_t mode);
/* Set_value display functions */
/* *************************************************************************************************
* @fn display_value1
* @brief Generic decimal display routine. Used exclusively by set_value function.
* @param uint8_t segments LCD segments where value is displayed
* uint32_t value Integer value to be displayed
* uint8_t digits Number of digits to convert
* uint8_t blanks Number of leadings blanks in itoa result string
* @return none
* ************************************************************************************************/
void display_value1(uint8_t segments, uint32_t value, uint8_t digits, uint8_t blanks, uint8_t disp_mode);
/* Integer to string conversion */
/* *************************************************************************************************
* @fn itoa
* @brief Generic integer to array routine. Converts integer n to string.
* Default conversion result has leading zeros, e.g. "00123"
* Option to convert leading '0' into whitespace (blanks)
* @param uint32_t n integer to convert
* uint8_t digits number of digits
* uint8_t blanks fill up result string with number of whitespaces instead of leading zeros
* @return uint8_t string
* ************************************************************************************************/
char *itoa(uint32_t n, uint8_t digits, uint8_t blanks);
/* Segment index helper function */
/* *************************************************************************************************
* @fn switch_seg
* @brief Returns index of 7-segment character. Required for display routines that can draw
* information on both lines.
* @param uint8_t line LINE1, LINE2
* uint8_t index1 Index of LINE1
* uint8_t index2 Index of LINE2
* @return uint8
* ************************************************************************************************/
uint8_t switch_seg(uint8_t line, uint8_t index1, uint8_t index2);
/* *************************************************************************************************
* @fn display_all_off
* @brief Sets everything of on the display
* @param none
* @return none
* ************************************************************************************************/
void display_all_off(void);
#ifdef __cplusplus
}
#endif
#endif /* DISPLAY_H */

22
boards/chronos/drivers/include/display_putchar.h
View File

@ -1,22 +0,0 @@
/*
* Copyright 2014 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
#ifndef DISPLAY_PUTCHAR_H
#define DISPLAY_PUTCHAR_H
#ifdef __cplusplus
extern "C" {
#endif
void init_display_putchar(void);
#ifdef __cplusplus
}
#endif
#endif /* DISPLAY_PUTCHAR_H */

59
boards/chronos/include/board.h
View File

@ -1,59 +0,0 @@
/*
* Copyright (C) 2013,2015 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_chronos
* @{
*
* @file
* @brief Header for the chronos board
*
* @author unknown
*/
#ifndef BOARD_H
#define BOARD_H
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Define the CPU model for the <msp430.h>
*/
#ifndef __CC430F6137__
#define __CC430F6137__
#endif
/**
* @name Xtimer configuration
* @{
*/
#define XTIMER_WIDTH (16)
/** @} */
/**
* @name MSP430 core configuration
* @{
*/
/** @todo Move this to the periph_conf.h */
#define MSP430_INITIAL_CPU_SPEED 7372800uL
#define F_CPU MSP430_INITIAL_CPU_SPEED
#define F_RC_OSCILLATOR 32768
#define MSP430_HAS_DCOR 1
#define MSP430_HAS_EXTERNAL_CRYSTAL 1
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* BOARD_H */
/** @} */

27
boards/chronos/include/buttons.h
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@ -1,27 +0,0 @@
/*
* Copyright 2014 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
#ifndef BUTTONS_H
#define BUTTONS_H
#ifdef __cplusplus
extern "C" {
#endif
// Button ports
#define BUTTON_STAR_PIN (BIT2)
#define BUTTON_NUM_PIN (BIT1)
#define BUTTON_UP_PIN (BIT4)
#define BUTTON_DOWN_PIN (BIT0)
#define BUTTON_BACKLIGHT_PIN (BIT3)
#ifdef __cplusplus
}
#endif
#endif /* BUTTONS_H */

75
boards/chronos/include/periph_conf.h
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@ -1,75 +0,0 @@
/*
* Copyright (C) 2014 INRIA
* 2015 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup boards_chronos
* @{
*
* @file
* @brief Chronos peripheral configuration
*
* @author Oliver Hahm <oliver.hahm@inria.fr>
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*/
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock configuration
* @{
*/
/** @todo Move all clock configuration code here from the board.h */
#define CLOCK_CORECLOCK (12000000U)
#define CLOCK_CMCLK CLOCK_CORECLOCK /* no divider programmed */
/** @} */
/**
* @name Timer configuration
* @{
*/
#define TIMER_NUMOF (1U)
#define TIMER_BASE (TIMER_A0)
#define TIMER_CHAN (5)
#define TIMER_ISR_CC0 (TIMER0_A0_VECTOR)
#define TIMER_ISR_CCX (TIMER0_A1_VECTOR)
/** @} */
/**
* @name UART configuration
* @{
*/
#define UART_NUMOF (1U)
#define UART_0_EN (1U)
#define UART_DEV (USART_1)
#define UART_IE (SFR->IE2)
#define UART_IF (SFR->IFG2)
#define UART_IE_RX_BIT (1 << 4)
#define UART_IE_TX_BIT (1 << 5)
#define UART_ME (SFR->ME2)
#define UART_ME_BITS (0x30)
#define UART_PORT (PORT_3)
#define UART_RX_PIN (1 << 6)
#define UART_TX_PIN (1 << 7)
#define UART_RX_ISR (USART1RX_VECTOR)
#define UART_TX_ISR (USART1TX_VECTOR)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* PERIPH_CONF_H */

51
boards/chronos/stdio.c
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@ -1,51 +0,0 @@
/*
* Copyright (C) 2014 INRIA
* 2015 Kaspar Schleiser <kaspar@schleiser.de>
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_chronos
* @{
*/
/**
* @file
* @brief eZ430-chronos getchar/putchar dummy implementation
*
* @author Oliver Hahm <oliver.hahm@inria.fr>
* @author Kaspar Schleiser <kaspar@schleiser.de>
*
*/
#include <stdio.h>
static void _dummy(int c)
{
(void)c;
}
void (*_putchar)(int c) = _dummy;
int putchar(int c)
{
_putchar(c);
return c;
}
int getchar(void)
{
/* dummy implementation */
return EOF;
}
ssize_t write(int fildes, const void *buf, size_t nbyte)
{
(void)fildes;
(void)buf;
(void)nbyte;
return -1;
}

6
boards/common/msb-430/Makefile.include
View File

@ -18,6 +18,10 @@ FFLAGS = $(MSPDEBUGFLAGS) "prog $(FLASHFILE)"
DEBUGSERVER = $(FLASHER)
DEBUGSERVER_FLAGS = $(MSPDEBUGFLAGS) gdb
DEBUGGER = $(PREFIX)gdb
DEBUGGER_FLAGS = --tui --ex="target remote localhost:2000" --ex "monitor reset halt" --ex load -ex "monitor reset halt" $(ELFFILE)
DEBUGGER_FLAGS = --ex="target remote localhost:2000" --ex "monitor reset halt" --ex load -ex "monitor reset halt" $(ELFFILE)
INCLUDES += -I$(RIOTBOARD)/common/msb-430/include
# setup reset tool
RESET ?= mspdebug
RESET_FLAGS ?= $(MSPDEBUGFLAGS) reset

3
boards/common/msb-430/board_init.c
View File

@ -198,7 +198,4 @@ void board_init(void)
msb_ports_init();
msp430_set_cpu_speed(CLOCK_CORECLOCK);
/* finally initialize STDIO */
stdio_init();
}

4
boards/telosb/board.c
View File

@ -9,7 +9,6 @@
#include "cpu.h"
#include "board.h"
#include "stdio_uart.h"
void uart_init(void);
@ -122,9 +121,6 @@ void board_init(void)
telosb_ports_init();
msp430_init_dco();
/* initialize STDIO */
stdio_init();
/* enable interrupts */
__bis_SR_register(GIE);
}

4
boards/z1/board.c
View File

@ -24,7 +24,6 @@
#include "cpu.h"
#include "board.h"
#include "stdio_uart.h"
static void z1_ports_init(void)
{
@ -215,9 +214,6 @@ void board_init(void)
/* initializes DCO */
msp430_init_dco();
/* initialize STDIO */
stdio_init();
/* enable interrupts */
__bis_SR_register(GIE);
}

7
core/atomic_c11.c
View File

@ -48,7 +48,14 @@
/* GCC documentation refers to the types as I1, I2, I4, I8, I16 */
typedef uint8_t I1;
/* the builtins are declared with "unsigned int", but "uint16_t" is typedef'ed
* to "short unsigned int" on most platforms where "sizeof(int) == 2." */
#if __SIZEOF_INT__ == 2
typedef unsigned int I2;
#else
typedef uint16_t I2;
#endif
/* the builtins are declared with "unsigned int", but "uint32_t" is typedef'ed
* to "long unsigned int" on most platforms where "sizeof(int) == 4. */

35
cpu/cc430/Kconfig
View File

@ -1,35 +0,0 @@
# Copyright (c) 2020 Freie Universität Berlin
# 2020 HAW Hamburg
#
# This file is subject to the terms and conditions of the GNU Lesser
# General Public License v2.1. See the file LICENSE in the top level
# directory for more details.
#
config CPU_FAM_CC430
bool
select CPU_CORE_MSP430
select HAS_CPU_CC430
## CPU Models
config CPU_MODEL_CC430F6137
bool
select CPU_FAM_CC430
## Definition of specific features
config HAS_CPU_CC430
bool
help
Indicates that a 'cc430' cpu is being used.
## Common CPU symbols
config CPU_FAM
default "cc430" if CPU_FAM_CC430
config CPU_MODEL
default "cc430f6137" if CPU_MODEL_CC430F6137
config CPU
default "cc430" if CPU_FAM_CC430
source "$(RIOTCPU)/msp430_common/Kconfig"

5
cpu/cc430/Makefile
View File

@ -1,5 +0,0 @@
MODULE = cpu
DIRS = $(RIOTCPU)/msp430_common periph
include $(RIOTBASE)/Makefile.base

3
cpu/cc430/Makefile.dep
View File

@ -1,3 +0,0 @@
USEMODULE += periph
include $(RIOTCPU)/msp430_common/Makefile.dep

3
cpu/cc430/Makefile.features
View File

@ -1,3 +0,0 @@
CPU_FAM = cc430
include $(RIOTCPU)/msp430_common/Makefile.features

1
cpu/cc430/Makefile.include
View File

@ -1 +0,0 @@
include $(RIOTCPU)/msp430_common/Makefile.include

162
cpu/cc430/cc430-adc.c
View File

@ -1,162 +0,0 @@
/* *************************************************************************************************
*
* Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ************************************************************************************************/
/**
* @ingroup cpu_cc430
* @{
*/
/**
* @file
* @brief eZ430 ADC driver
*
* @author Oliver Hahm <oliver.hahm@inria.fr>
*
*/
#include <legacymsp430.h>
#include "irq.h"
#include "cpu.h"
#include "cc430-adc.h"
#include "xtimer.h"
uint16_t adc12_result;
uint8_t adc12_data_ready;
/************************************************************************************************
* @fn adc12_single_conversion
* @brief Init ADC12. Do single conversion. Turn off ADC12.
* @param none
* @return none
************************************************************************************************/
uint16_t adc12_single_conversion(uint16_t ref, uint16_t sht, uint16_t channel)
{
/* Initialize the shared reference module */
REFCTL0 |= REFMSTR + ref + REFON; /* Enable internal reference (1.5V or 2.5V) */
/* Initialize ADC12_A */
ADC12CTL0 = sht + ADC12ON; /* Set sample time */
ADC12CTL1 = ADC12SHP; /* Enable sample timer */
ADC12MCTL0 = ADC12SREF_1 + channel; /* ADC input channel */
ADC12IE = 0x001; /* ADC_IFG upon conv result-ADCMEMO */
irq_enable();
/* Wait 66us to allow internal reference to settle */
xtimer_usleep(66);
/* Start ADC12 */
ADC12CTL0 |= ADC12ENC;
/* Clear data ready flag */
adc12_data_ready = 0;
/* Sampling and conversion start */
ADC12CTL0 |= ADC12SC;
/* Wait until ADC12 has finished */
xtimer_usleep(150);
while (!adc12_data_ready);
/* Shut down ADC12 */
ADC12CTL0 &= ~(ADC12ENC | ADC12SC | sht);
ADC12CTL0 &= ~ADC12ON;
/* Shut down reference voltage */
REFCTL0 &= ~(REFMSTR + ref + REFON);
ADC12IE = 0;
/* Return ADC result */
return adc12_result;
}
/*************************************************************************************************
* @fn ADC12ISR
* @brief Store ADC12 conversion result. Set flag to indicate data ready.
* @param none
* @return none
*************************************************************************************************/
interrupt(ADC12_VECTOR) __attribute__((naked)) adc_isr(void)
{
__enter_isr();
switch(ADC12IV) {
case 0:
break; /* Vector 0: No interrupt */
case 2:
break; /* Vector 2: ADC overflow */
case 4:
break; /* Vector 4: ADC timing overflow */
case 6:
/* Vector 6: ADC12IFG0 */
adc12_result = ADC12MEM0; /* Move results, IFG is cleared */
adc12_data_ready = 1;
break;
case 8:
break; /* Vector 8: ADC12IFG1 */
case 10:
break; /* Vector 10: ADC12IFG2 */
case 12:
break; /* Vector 12: ADC12IFG3 */
case 14:
break; /* Vector 14: ADC12IFG4 */
case 16:
break; /* Vector 16: ADC12IFG5 */
case 18:
break; /* Vector 18: ADC12IFG6 */
case 20:
break; /* Vector 20: ADC12IFG7 */
case 22:
break; /* Vector 22: ADC12IFG8 */
case 24:
break; /* Vector 24: ADC12IFG9 */
case 26:
break; /* Vector 26: ADC12IFG10 */
case 28:
break; /* Vector 28: ADC12IFG11 */
case 30:
break; /* Vector 30: ADC12IFG12 */
case 32:
break; /* Vector 32: ADC12IFG13 */
case 34:
break; /* Vector 34: ADC12IFG14 */
default:
break;
}
__exit_isr();
}

13
cpu/cc430/doc.txt
View File

@ -1,13 +0,0 @@
/*
* Copyright (C) 2013 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @defgroup cpu_cc430 TI CC430
* @brief Texas Instruments CC430 specific code
* @ingroup cpu
*/

52
cpu/cc430/include/cc430-adc.h
View File

@ -1,52 +0,0 @@
/* *************************************************************************************************
*
* Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ************************************************************************************************/
#ifndef CC430_ADC_H
#define CC430_ADC_H
#ifdef __cplusplus
extern "C" {
#endif
extern uint16_t adc12_single_conversion(uint16_t ref, uint16_t sht, uint16_t channel);
extern uint16_t adc12_result;
extern uint8_t adc12_data_ready;
#ifdef __cplusplus
}
#endif
#endif /* CC430_ADC_H */

51
cpu/cc430/include/cc430-rtc.h
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@ -1,51 +0,0 @@
/*
* Copyright 2010, Freie Universitaet Berlin (FUB). All rights reserved.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
#ifndef CC430_RTC_H
#define CC430_RTC_H
#include "periph/rtc.h"
#include "time.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @ingroup cpu_cc430
*/
/**
* @file
* @brief CC430 Real Time Clock
*
* @author Freie Universität Berlin, Computer Systems & Telematics, RIOT
* @version $Revision $
*/
/**
* @brief Mask for RTC alarms
* @see ::rtc_set_alarm
*/
typedef enum {
RTC_ALARM_DISABLED = 0x00, /**< Alarm disables */
RTC_ALARM_MIN = 0x01, /**< Alarm mask for Minutes */
RTC_ALARM_HOUR = 0x02, /**< Alarm mask for Hours */
RTC_ALARM_DOW = 0x04, /**< Alarm mask for Day of Week */
RTC_ALARM_DOM = 0x08 /**< Alarm mask for Day of Month */
} rtc_alarm_mask_t;
/**
* @brief Resets any set alarm
*/
void rtc_remove_alarm(void);
#ifdef __cplusplus
}
#endif
#endif /* CC430_RTC_H */

123
cpu/cc430/include/cc430_regs.h
View File

@ -1,123 +0,0 @@
/*
* Copyright (C) 2015 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_cc430
* @{
*
* @file
* @brief Cortex CMSIS style definition of CC430 registers
*
* @todo This file is incomplete, not all registers are listed. Further
* There are probably some inconsistencies throughout the MSP430
* family which need to be addressed.
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*/
#ifndef CC430_REGS_H
#define CC430_REGS_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Shortcut to specify 8-bit wide registers
*/
#define REG8 volatile uint8_t
/**
* @brief Shortcut to specify 16-bit wide registers
*/
#define REG16 volatile uint16_t
/**
* @brief Timer module registers
*/
typedef struct {
REG16 CTL; /**< timer control */
REG16 CCTL[7]; /**< capture compare channel control */
REG16 R; /**< current counter value */
REG16 CCR[7]; /**< capture compare channel values */
REG16 reserved[7]; /**< reserved */
REG16 IV; /**< interrupt vector */
REG16 EX0; /**< expansion 0 */
} msp_timer_t;
/**
* @brief Timer Control register bitmap
* @{
*/
#define CTL_IFG (0x0001)
#define CTL_IE (0x0002)
#define CTL_CLR (0x0004)
#define CTL_MC_MASK (0x0030)
#define CTL_MC_STOP (0x0000)
#define CTL_MC_UP (0x0010)
#define CTL_MC_CONT (0x0020)
#define CTL_MC_UPDOWN (0x0030)
#define CTL_ID_MASK (0x00c0)
#define CTL_ID_DIV1 (0x0000)
#define CTL_ID_DIV2 (0x0040)
#define CTL_ID_DIV4 (0x0080)
#define CTL_ID_DIV8 (0x00c0)
#define CTL_TASSEL_MASK (0x0300)
#define CTL_TASSEL_TCLK (0x0000)
#define CTL_TASSEL_ACLK (0x0100)
#define CTL_TASSEL_SMCLK (0x0200)
#define CTL_TASSEL_INV_TCLK (0x0300)
/** @} */
/**
* @brief Timer Channel Control register bitmap
* @{
*/
#define CCTL_CCIFG (0x0001)
#define CCTL_COV (0x0002)
#define CCTL_OUT (0x0004)
#define CCTL_CCI (0x0008)
#define CCTL_CCIE (0x0010)
#define CCTL_OUTMOD_MASK (0x00e0)
#define CCTL_OUTMOD_OUTVAL (0x0000)
#define CCTL_OUTMOD_SET (0x0020)
#define CCTL_OUTMOD_TOG_RESET (0x0040)
#define CCTL_OUTMOD_SET_RESET (0x0060)
#define CCTL_OUTMOD_TOGGLE (0x0080)
#define CCTL_OUTMOD_RESET (0x00a0)
#define CCTL_OUTMOD_TOG_SET (0x00c0)
#define CCTL_OUTMOD_RESET_SET (0x00e0)
#define CCTL_CAP (0x0100)
#define CCTL_CLLD_MASK (0x0600)
#define CCTL_SCS (0x0800)
#define CCTL_CCIS_MASK (0x3000)
#define CCTL_CM_MASK (0xc000)
/** @} */
/**
* @brief Base register address definitions
* @{
*/
#define TIMER_A0_BASE ((uint16_t)0x0340)
#define TIMER_A1_BASE ((uint16_t)0x0380)
/** @} */
/**
* @brief Typing of base register objects
* @{
*/
#define TIMER_A0 ((msp_timer_t *)TIMER_A0_BASE)
#define TIMER_A1 ((msp_timer_t *)TIMER_A1_BASE)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* CC430_REGS_H */
/** @} */

36
cpu/cc430/include/periph_cpu.h
View File

@ -1,36 +0,0 @@
/*
* Copyright (C) 2015 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_cc430
* @{
*
* @file
* @brief CPU specific definitions for internal peripheral handling
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*/
#ifndef PERIPH_CPU_H
#define PERIPH_CPU_H
#include "cpu.h"
#include "cc430_regs.h"
#ifdef __cplusplus
extern "C" {
#endif
/* more to come here... */
#ifdef __cplusplus
}
#endif
#endif /* PERIPH_CPU_H */
/** @} */

1
cpu/cc430/periph/Makefile
View File

@ -1 +0,0 @@
include $(RIOTMAKE)/periph.mk

224
cpu/cc430/periph/rtc.c
View File

@ -1,224 +0,0 @@
/*
* Copyright 2010, Freie Universitaet Berlin (FUB).
* Copyright 2013, INRIA.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_cc430
* @ingroup drivers_periph_rtc
* @{
*
* @file
* @brief CC430 real time clock implementation
* @author Oliver Hahm <oliver.hahm@inria.fr>
*
* @}
*/
#include <string.h>
#include <legacymsp430.h>
#include "irq.h"
#include "cpu.h"
#include "cc430-rtc.h"
/* Alarm callback */
static rtc_alarm_cb_t _cb;
/* Argument to alarm callback */
static void *_cb_arg;
static struct tm time_to_set;
static int set_time = 0;
kernel_pid_t rtc_second_pid = KERNEL_PID_UNDEF;
void rtc_init(void)
{
/* Set to calendar mode */
RTCCTL1 |= RTCMODE_H;
}
void rtc_poweron(void)
{
/* Set RTC operational */
RTCCTL1 &= ~RTCHOLD_H;
}
void rtc_poweroff(void)
{
/* Stop RTC */
RTCCTL1 |= RTCHOLD_H;
}
int rtc_set_time(struct tm *localt)
{
if (localt == NULL) {
return -1;
}
/* normalize input */
rtc_tm_normalize(localt);
/* copy time to be set */
time_to_set = *localt;
set_time = 1;
return 0;
}
int rtc_get_time(struct tm *localt)
{
uint8_t success = 0;
uint8_t i;
uint16_t tmpyear;
if (localt == NULL) {
return -1;
}
while (!success) {
for (i = 0; i < 8; i++) {
/* try again when RTC is in transition */
if (!(RTCCTL1 & RTCRDY_H)) {
break;
}
switch(i) {
case 0:
localt->tm_sec = RTCSEC;
break;
case 1:
localt->tm_min = RTCMIN;
break;
case 2:
localt->tm_hour = RTCHOUR;
break;
case 3:
localt->tm_mday = RTCDAY;
break;
case 4:
localt->tm_wday = RTCDOW;
break;
case 5:
localt->tm_mon = RTCMON - 1;
break;
case 6:
tmpyear = RTCYEARL;
tmpyear |= (RTCYEARH << 0x08);
localt->tm_year = tmpyear - 1900;
break;
default:
success = 1;
break;
}
}
}
return 0;
}
int rtc_set_alarm(struct tm *localt, rtc_alarm_cb_t cb, void *arg)
{
(void)arg;
if (localt != NULL) {
/* normalize input */
rtc_tm_normalize(localt);
RTCAMIN = localt->tm_min;
RTCAMIN |= BIT7;
RTCAHOUR = localt->tm_hour;
RTCAHOUR |= BIT7;
RTCADOW = localt->tm_wday;
RTCADOW |= BIT7;
RTCADAY = localt->tm_mday;
RTCADAY |= BIT7;
RTCCTL0 |= RTCAIE;
return 0;
}
else if (cb == NULL) {
return -1;
}
return -2;
}
int rtc_get_alarm(struct tm *localt)
{
if (localt != NULL) {
localt->tm_sec = -1;
localt->tm_min = RTCAMIN;
localt->tm_hour = RTCAHOUR;
localt->tm_mday = -1;
localt->tm_wday = RTCADOW;
localt->tm_yday = -1;
localt->tm_mon = - 1;
localt->tm_year = -1;
localt->tm_isdst = -1; /* not available */
return 0;
}
return -1;
}
void rtc_clear_alarm(void)
{
/* reset all AE bits */
RTCAHOUR &= ~BIT7;
RTCAMIN &= ~BIT7;
RTCADAY &= ~BIT7;
RTCADOW &= ~BIT7;
/* reset alarm interrupt enable */
RTCCTL0 &= ~RTCAIE;
}
interrupt(RTC_VECTOR) __attribute__((naked)) rtc_isr(void)
{
__enter_isr();
/* RTC is save to write for up to one second now */
if (RTCIV == RTC_RTCRDYIFG) {
/* disable interrupt */
//RTCCTL0 &= ~RTCRDYIE;
if (set_time) {
set_time = 0;
/* set previous set time and reset it */
RTCSEC = time_to_set.tm_sec;
RTCMIN = time_to_set.tm_min;
RTCHOUR = time_to_set.tm_hour;
RTCDAY = time_to_set.tm_mday;
RTCDOW = time_to_set.tm_wday;
RTCMON = time_to_set.tm_mon + 1;
RTCYEARL = (time_to_set.tm_year + 1900) & 0xFF;
RTCYEARH = (time_to_set.tm_year + 1900) >> 0x08;
}
if (rtc_second_pid != KERNEL_PID_UNDEF) {
static msg_t m;
m.type = RTCSEC;
msg_send_int(&m, rtc_second_pid);
}
}
/* RTC alarm */
else if (RTCIV == RTC_RTCAIFG) {
if (_cb) {
_cb(_cb_arg);
}
}
__exit_isr();
}

128
cpu/cc430/periph/timer.c
View File

@ -1,128 +0,0 @@
/*
* Copyright (C) 2015 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_cc430
* @ingroup drivers_periph_timer
* @{
*
* @file
* @brief Low-level timer driver implementation
*
* This implementation does only support one fixed timer, as defined in the
* boards periph_conf.h file.
*
* @todo Generalize to handle more timers and make them configurable
* through the board's `periph_conf.h`
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
* @}
*/
#include "cpu.h"
#include "periph_cpu.h"
#include "periph_conf.h"
#include "periph/timer.h"
/**
* @brief Save reference to the timer callback
*/
static timer_cb_t isr_cb;
/**
* @brief Save argument for the callback
*/
static void *isr_arg;
int timer_init(tim_t dev, unsigned long freq, timer_cb_t cb, void *arg)
{
/* using fixed TIMER_BASE for now */
if (dev != 0) {
return -1;
}
/* TODO: configure time-base depending on freq value */
if (freq != 1000000ul) {
return -1;
}
/* reset the timer A configuration */
TIMER_BASE->CTL = CTL_CLR;
/* save callback */
isr_cb = cb;
isr_arg = arg;
/* configure timer to use the SMCLK with prescaler of 8 */
TIMER_BASE->CTL = (CTL_TASSEL_SMCLK | CTL_ID_DIV8);
/* configure CC channels */
for (int i = 0; i < TIMER_CHAN; i++) {
TIMER_BASE->CCTL[i] = 0;
}
/* start the timer in continuous mode */
TIMER_BASE->CTL |= CTL_MC_CONT;
return 0;
}
int timer_set_absolute(tim_t dev, int channel, unsigned int value)
{
if (dev != 0 || channel >= TIMER_CHAN) {
return -1;
}
TIMER_BASE->CCR[channel] = value;
TIMER_BASE->CCTL[channel] &= ~(CCTL_CCIFG);
TIMER_BASE->CCTL[channel] |= (CCTL_CCIE);
return 0;
}
int timer_clear(tim_t dev, int channel)
{
if (dev != 0 || channel >= TIMER_CHAN) {
return -1;
}
TIMER_BASE->CCTL[channel] &= ~(CCTL_CCIE);
return 0;
}
unsigned int timer_read(tim_t dev)
{
(void)dev;
return (unsigned int)TIMER_BASE->R;
}
void timer_start(tim_t dev)
{
(void)dev;
TIMER_BASE->CTL |= CTL_MC_CONT;
}
void timer_stop(tim_t dev)
{
(void)dev;
TIMER_BASE->CTL &= ~(CTL_MC_MASK);
}
ISR(TIMER_ISR_CC0, isr_timer_a_cc0)
{
__enter_isr();
TIMER_BASE->CCTL[0] &= ~(CCTL_CCIE);
isr_cb(isr_arg, 0);
__exit_isr();
}
ISR(TIMER_ISR_CCX, isr_timer_a_ccx_isr)
{
__enter_isr();
int chan = (int)(TIMER_BASE->IV >> 1);
TIMER_BASE->CCTL[chan] &= ~(CCTL_CCIE);
isr_cb(isr_arg, chan);
__exit_isr();
}

9
cpu/msp430_common/Makefile.dep
View File

@ -1,3 +1,8 @@
USEMODULE += msp430_common msp430_common_periph msp430_malloc
USEMODULE += msp430_common msp430_common_periph
DEFAULT_MODULE += oneway_malloc
# msp430 uses newlib by default
DEFAULT_MODULE += newlib
ifneq (,$(filter newlib,$(USEMODULE)))
USEMODULE += newlib_nano
endif

2
cpu/msp430_common/Makefile.include
View File

@ -1,5 +1,3 @@
PSEUDOMODULES += msp430_malloc
INCLUDES += -I$(RIOTCPU)/msp430_common/include/
CFLAGS += -DCPU_MODEL_$(call uppercase_and_underscore,$(CPU_MODEL))

13
cpu/msp430_common/cpu.c
View File

@ -117,19 +117,20 @@ char *thread_stack_init(thread_task_func_t task_func, void *arg, void *stack_sta
--stackptr;
/* initial value for SR */
*stackptr = GIE;
--stackptr;
/* set argument to task_func */
*stackptr = (unsigned short) arg;
--stackptr;
/* Space for registers. */
for (unsigned int i = 14; i > 4; i--) {
for (unsigned int i = 15; i > 4; i--) {
*stackptr = i;
--stackptr;
}
/* set arg to R12
this was R15 in mspgcc, see https://www.ti.com/lit/an/slaa664/slaa664.pdf
stackptr points to R3, so write arg 9 words after that.
*/
stackptr[8] = (intptr_t)arg;
return (char *) stackptr;
}

28
cpu/msp430_common/include/c11_atomics_compat_cpu.hpp
View File

@ -1,14 +1,14 @@
/* This file was automatically generated using ./dist/tools/generate_c11_atomics_cpp_compat_header/generate_c11_atomics_cpp_compat_header.sh */
#pragma once
#define ATOMIC_BOOL_SIZE (2U)
#define ATOMIC_BOOL_SAME_SIZED_TYPE uint16_t
#define ATOMIC_CHAR_SIZE (2U)
#define ATOMIC_CHAR_SAME_SIZED_TYPE uint16_t
#define ATOMIC_SCHAR_SIZE (2U)
#define ATOMIC_SCHAR_SAME_SIZED_TYPE uint16_t
#define ATOMIC_UCHAR_SIZE (2U)
#define ATOMIC_UCHAR_SAME_SIZED_TYPE uint16_t
#define ATOMIC_BOOL_SIZE (1U)
#define ATOMIC_BOOL_SAME_SIZED_TYPE uint8_t
#define ATOMIC_CHAR_SIZE (1U)
#define ATOMIC_CHAR_SAME_SIZED_TYPE uint8_t
#define ATOMIC_SCHAR_SIZE (1U)
#define ATOMIC_SCHAR_SAME_SIZED_TYPE uint8_t
#define ATOMIC_UCHAR_SIZE (1U)
#define ATOMIC_UCHAR_SAME_SIZED_TYPE uint8_t
#define ATOMIC_SHORT_SIZE (2U)
#define ATOMIC_SHORT_SAME_SIZED_TYPE uint16_t
#define ATOMIC_USHORT_SIZE (2U)
@ -25,10 +25,10 @@
#define ATOMIC_LLONG_SAME_SIZED_TYPE uint64_t
#define ATOMIC_ULLONG_SIZE (8U)
#define ATOMIC_ULLONG_SAME_SIZED_TYPE uint64_t
#define ATOMIC_INT_LEAST8_T_SIZE (2U)
#define ATOMIC_INT_LEAST8_T_SAME_SIZED_TYPE uint16_t
#define ATOMIC_UINT_LEAST8_T_SIZE (2U)
#define ATOMIC_UINT_LEAST8_T_SAME_SIZED_TYPE uint16_t
#define ATOMIC_INT_LEAST8_T_SIZE (1U)
#define ATOMIC_INT_LEAST8_T_SAME_SIZED_TYPE uint8_t
#define ATOMIC_UINT_LEAST8_T_SIZE (1U)
#define ATOMIC_UINT_LEAST8_T_SAME_SIZED_TYPE uint8_t
#define ATOMIC_INT_LEAST16_T_SIZE (2U)
#define ATOMIC_INT_LEAST16_T_SAME_SIZED_TYPE uint16_t
#define ATOMIC_UINT_LEAST16_T_SIZE (2U)
@ -63,8 +63,8 @@
#define ATOMIC_UINTPTR_T_SAME_SIZED_TYPE uint16_t
#define ATOMIC_SIZE_T_SIZE (2U)
#define ATOMIC_SIZE_T_SAME_SIZED_TYPE uint16_t
#define ATOMIC_PTRDIFF_T_SIZE (4U)
#define ATOMIC_PTRDIFF_T_SAME_SIZED_TYPE uint32_t
#define ATOMIC_PTRDIFF_T_SIZE (2U)
#define ATOMIC_PTRDIFF_T_SAME_SIZED_TYPE uint16_t
#define ATOMIC_INTMAX_T_SIZE (8U)
#define ATOMIC_INTMAX_T_SAME_SIZED_TYPE uint64_t
#define ATOMIC_UINTMAX_T_SIZE (8U)

9
cpu/msp430_common/include/cpu.h
View File

@ -28,7 +28,6 @@
#include "sched.h"
#include "thread.h"
#include "msp430_types.h"
#include "cpu_conf.h"
#ifdef __cplusplus
@ -50,11 +49,6 @@ extern "C" {
*/
extern volatile int __irq_is_in;
/**
* @brief Memory used as stack for the interrupt context
*/
extern char __isr_stack[ISR_STACKSIZE];
/**
* @brief Save the current thread context from inside an ISR
*/
@ -103,8 +97,9 @@ static inline void __attribute__((always_inline)) __restore_context(void)
*/
static inline void __attribute__((always_inline)) __enter_isr(void)
{
extern char __stack; /* defined by linker script to end of RAM */
__save_context();
__asm__("mov.w %0,r1" : : "i"(__isr_stack + ISR_STACKSIZE));
__asm__("mov.w %0,r1" : : "i"(&__stack));
__irq_is_in = 1;
}

7
cpu/msp430_common/include/cpu_conf.h
View File

@ -68,7 +68,7 @@ extern "C" {
#endif
#ifndef THREAD_STACKSIZE_DEFAULT
# define THREAD_STACKSIZE_DEFAULT (256)
# define THREAD_STACKSIZE_DEFAULT (384)
#endif
#ifndef THREAD_STACKSIZE_IDLE
@ -89,11 +89,6 @@ extern "C" {
#endif
/** @} */
/**
* @brief Declare the heap_stats function as available
*/
#define HAVE_HEAP_STATS
#ifdef __cplusplus
}
#endif

27
cpu/msp430_common/include/irq_arch.h
View File

@ -30,6 +30,13 @@
extern "C" {
#endif
/*
* gcc warns for missing NOPs before/after interrupt enable/disable.
* so I added the NOP instructions, even though they might not be necessary
* due to following AND. // Kaspar
*/
extern volatile int __irq_is_in;
__attribute__((always_inline)) static inline unsigned int irq_disable(void)
@ -38,13 +45,7 @@ __attribute__((always_inline)) static inline unsigned int irq_disable(void)
__asm__ volatile(
"mov.w r2, %[state]" "\n\t"
"bic %[gie], r2" "\n\t"
/*
* BEWARE: IRQs remain enabled for one instruction after clearing the
* GIE bit in the status register (r2). Thus, the next instruction is
* not only used to sanitize the IRQ state, but also delays the actual
* critical section by one CPU cycle, so that IRQs are indeed disabled
* by then.
*/
"nop" "\n\t"
"and %[gie], %[state]" "\n\t"
: [state] "=r"(state)
: [gie] "i"(GIE)
@ -59,13 +60,9 @@ __attribute__((always_inline)) static inline unsigned int irq_enable(void)
unsigned int state;
__asm__ volatile(
"mov.w r2, %[state]" "\n\t"
"nop" "\n\t"
"bis %[gie], r2" "\n\t"
/*
* BEWARE: IRQs remain disabled for one instruction after setting the
* GIE bit in the status register (r2). Thus, the next instruction is
* not only used to sanitize the IRQ state, but also ensures that the
* first instruction after this function is run with IRQs enabled.
*/
"nop" "\n\t"
"and %[gie], %[state]" "\n\t"
: [state] "=r"(state)
: [gie] "i"(GIE)
@ -79,13 +76,11 @@ __attribute__((always_inline)) static inline void irq_restore(unsigned int state
{
__asm__ volatile(
"bis %[state], r2" "\n\t"
"nop" "\n\t"
: /* no outputs */
: [state] "r"(state)
: "memory"
);
/* BEWARE: IRQs remain disabled for up to one CPU cycle after this function
* call. But that doesn't seem to be harmful.
*/
}
__attribute__((always_inline)) static inline int irq_is_in(void)

100
cpu/msp430_common/include/msp430_types.h
View File

@ -1,100 +0,0 @@
/*
* Copyright (C) 2014 INRIA
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_msp430_common
* @{
*
* @file
* @brief basic types for MSP430
*/
#ifndef MSP430_TYPES_H
#define MSP430_TYPES_H
#include <sys/_types.h>
#include <errno.h>
/** defining signed type for size_t */
#include "kernel_types.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifndef EINVAL
/**
* @brief defines EINVAL if MSP430 toolchain is too old to provide it itself
* via errno.h
*/
#define EINVAL (28)
#endif
#ifndef EOVERFLOW
/**
* @brief defines EOVERFLOW if MSP430 toolchain is too old to provide it itself
* via errno.h
*/
#define EOVERFLOW (65)
#endif
/**
* @brief Definition of `time_t` for the MSP430
*
* @todo Remove once msp430 libc supports `time_t`
*/
typedef unsigned long time_t;
/**
* @brief Definition of `struct timespec` for the MSP430
*
* @todo Remove once msp430 libc supports `struct timespec`
*/
struct timespec {
time_t tv_sec; /**< seconds */
long tv_nsec; /**< nanoseconds */
};
/**
* @brief Definition of `struct timeval` for the MSP430
*
* @todo Remove once msp430 libc supports struct timeval
*/
struct timeval {
time_t tv_sec; /**< seconds */
time_t tv_usec; /**< microseconds */
};
typedef int32_t blkcnt_t; /**< Used for file block counts */
typedef int32_t blksize_t; /**< Used for block sizes */
typedef uint32_t clock_t; /**< Used for system times in clock ticks */
typedef uint32_t clockid_t; /**< Used for clock ID type in the clock and timer functions */
typedef int16_t dev_t; /**< Used for device IDs */
typedef uint32_t fsblkcnt_t; /**< Used for file system block counts */
typedef uint32_t fsfilcnt_t; /**< Used for file system file counts */
typedef uint16_t gid_t; /**< Used for group IDs */
typedef uint16_t id_t; /**< Used as a general identifier */
typedef uint32_t ino_t; /**< Used for file serial numbers */
typedef uint32_t key_t; /**< Used for XSI interprocess communication */
typedef uint32_t mode_t; /**< Used for some file attributes */
typedef uint16_t nlink_t; /**< Used for link counts */
typedef int32_t off_t; /**< Used for file sizes and offsets */
typedef int pid_t; /**< Used for process IDs and process group IDs */
typedef unsigned int size_t; /**< Used for sizes of objects */
typedef signed int ssize_t; /**< Used for a count of bytes or an error indication */
typedef int32_t suseconds_t; /**< Used for time in microseconds */
typedef uint32_t timer_t; /**< Used for timer ID returned by timer_create() */
typedef uint16_t uid_t; /**< Used for user IDs */
typedef uint32_t useconds_t; /**< Used for time in microseconds */
#ifdef __cplusplus
}
#endif
#endif /* MSP430_TYPES_H */
/** @} */

427
cpu/msp430_common/include/stdatomic.h
View File

@ -1,427 +0,0 @@
/*-
* Copyright (c) 2011 Ed Schouten <ed@FreeBSD.org>
* David Chisnall <theraven@FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
/* This file was imported into RIOT from newlib 2.3.0 */
#ifndef STDATOMIC_H
#define STDATOMIC_H
#include <sys/cdefs.h>
#include <sys/_types.h>
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if __has_extension(c_atomic) || __has_extension(cxx_atomic)
#define __CLANG_ATOMICS
#elif __GNUC_PREREQ__(4, 7)
#define __GNUC_ATOMICS
#elif defined(__GNUC__)
#define __SYNC_ATOMICS
#else
#error "stdatomic.h does not support your compiler"
#endif
/*
* 7.17.1 Atomic lock-free macros.
*/
#ifdef __GCC_ATOMIC_BOOL_LOCK_FREE
#define ATOMIC_BOOL_LOCK_FREE __GCC_ATOMIC_BOOL_LOCK_FREE
#endif
#ifdef __GCC_ATOMIC_CHAR_LOCK_FREE
#define ATOMIC_CHAR_LOCK_FREE __GCC_ATOMIC_CHAR_LOCK_FREE
#endif
#ifdef __GCC_ATOMIC_CHAR16_T_LOCK_FREE
#define ATOMIC_CHAR16_T_LOCK_FREE __GCC_ATOMIC_CHAR16_T_LOCK_FREE
#endif
#ifdef __GCC_ATOMIC_CHAR32_T_LOCK_FREE
#define ATOMIC_CHAR32_T_LOCK_FREE __GCC_ATOMIC_CHAR32_T_LOCK_FREE
#endif
#ifdef __GCC_ATOMIC_WCHAR_T_LOCK_FREE
#define ATOMIC_WCHAR_T_LOCK_FREE __GCC_ATOMIC_WCHAR_T_LOCK_FREE
#endif
#ifdef __GCC_ATOMIC_SHORT_LOCK_FREE
#define ATOMIC_SHORT_LOCK_FREE __GCC_ATOMIC_SHORT_LOCK_FREE
#endif
#ifdef __GCC_ATOMIC_INT_LOCK_FREE
#define ATOMIC_INT_LOCK_FREE __GCC_ATOMIC_INT_LOCK_FREE
#endif
#ifdef __GCC_ATOMIC_LONG_LOCK_FREE
#define ATOMIC_LONG_LOCK_FREE __GCC_ATOMIC_LONG_LOCK_FREE
#endif
#ifdef __GCC_ATOMIC_LLONG_LOCK_FREE
#define ATOMIC_LLONG_LOCK_FREE __GCC_ATOMIC_LLONG_LOCK_FREE
#endif
#ifdef __GCC_ATOMIC_POINTER_LOCK_FREE
#define ATOMIC_POINTER_LOCK_FREE __GCC_ATOMIC_POINTER_LOCK_FREE
#endif
/*
* 7.17.2 Initialization.
*/
#if defined(__CLANG_ATOMICS)
#define ATOMIC_VAR_INIT(value) (value)
#define atomic_init(obj, value) __c11_atomic_init(obj, value)
#else
#define ATOMIC_VAR_INIT(value) { .__val = (value) }
#define atomic_init(obj, value) ((void)((obj)->__val = (value)))
#endif
/*
* Clang and recent GCC both provide predefined macros for the memory
* orderings. If we are using a compiler that doesn't define them, use the
* clang values - these will be ignored in the fallback path.
*/
#ifndef __ATOMIC_RELAXED
#define __ATOMIC_RELAXED 0
#endif
#ifndef __ATOMIC_CONSUME
#define __ATOMIC_CONSUME 1
#endif
#ifndef __ATOMIC_ACQUIRE
#define __ATOMIC_ACQUIRE 2
#endif
#ifndef __ATOMIC_RELEASE
#define __ATOMIC_RELEASE 3
#endif
#ifndef __ATOMIC_ACQ_REL
#define __ATOMIC_ACQ_REL 4
#endif
#ifndef __ATOMIC_SEQ_CST
#define __ATOMIC_SEQ_CST 5
#endif
/*
* 7.17.3 Order and consistency.
*
* The memory_order_* constants that denote the barrier behaviour of the
* atomic operations.
*/
typedef enum {
memory_order_relaxed = __ATOMIC_RELAXED,
memory_order_consume = __ATOMIC_CONSUME,
memory_order_acquire = __ATOMIC_ACQUIRE,
memory_order_release = __ATOMIC_RELEASE,
memory_order_acq_rel = __ATOMIC_ACQ_REL,
memory_order_seq_cst = __ATOMIC_SEQ_CST
} memory_order;
/*
* 7.17.4 Fences.
*/
static __inline void
atomic_thread_fence(memory_order __order)
{
#ifdef __CLANG_ATOMICS
__c11_atomic_thread_fence(__order);
#elif defined(__GNUC_ATOMICS)
__atomic_thread_fence(__order);
#else
(void) __order;
__sync_synchronize();
#endif
}
static __inline void
atomic_signal_fence(memory_order __order)
{
#ifdef __CLANG_ATOMICS
__c11_atomic_signal_fence(__order);
#elif defined(__GNUC_ATOMICS)
__atomic_signal_fence(__order);
#else
(void) __order;
__asm volatile ("" ::: "memory");
#endif
}
/*
* 7.17.5 Lock-free property.
*/
#if defined(_KERNEL)
/* Atomics in kernelspace are always lock-free. */
#define atomic_is_lock_free(obj) \
((void)(obj), (_Bool)1)
#elif defined(__CLANG_ATOMICS)
#define atomic_is_lock_free(obj) \
__atomic_is_lock_free(sizeof(*(obj)), obj)
#elif defined(__GNUC_ATOMICS)
#define atomic_is_lock_free(obj) \
__atomic_is_lock_free(sizeof((obj)->__val), &(obj)->__val)
#else
#define atomic_is_lock_free(obj) \
((void)(obj), sizeof((obj)->__val) <= sizeof(void *))
#endif
/*
* 7.17.6 Atomic integer types.
*/
typedef _Atomic(_Bool) atomic_bool;
typedef _Atomic(char) atomic_char;
typedef _Atomic(signed char) atomic_schar;
typedef _Atomic(unsigned char) atomic_uchar;
typedef _Atomic(short) atomic_short;
typedef _Atomic(unsigned short) atomic_ushort;
typedef _Atomic(int) atomic_int;
typedef _Atomic(unsigned int) atomic_uint;
typedef _Atomic(long) atomic_long;
typedef _Atomic(unsigned long) atomic_ulong;
typedef _Atomic(long long) atomic_llong;
typedef _Atomic(unsigned long long) atomic_ullong;
#if 0
typedef _Atomic(__char16_t) atomic_char16_t;
typedef _Atomic(__char32_t) atomic_char32_t;
#endif
typedef _Atomic(wchar_t) atomic_wchar_t;
typedef _Atomic(int_least8_t) atomic_int_least8_t;
typedef _Atomic(uint_least8_t) atomic_uint_least8_t;
typedef _Atomic(int_least16_t) atomic_int_least16_t;
typedef _Atomic(uint_least16_t) atomic_uint_least16_t;
typedef _Atomic(int_least32_t) atomic_int_least32_t;
typedef _Atomic(uint_least32_t) atomic_uint_least32_t;
typedef _Atomic(int_least64_t) atomic_int_least64_t;
typedef _Atomic(uint_least64_t) atomic_uint_least64_t;
typedef _Atomic(int_fast8_t) atomic_int_fast8_t;
typedef _Atomic(uint_fast8_t) atomic_uint_fast8_t;
typedef _Atomic(int_fast16_t) atomic_int_fast16_t;
typedef _Atomic(uint_fast16_t) atomic_uint_fast16_t;
typedef _Atomic(int_fast32_t) atomic_int_fast32_t;
typedef _Atomic(uint_fast32_t) atomic_uint_fast32_t;
typedef _Atomic(int_fast64_t) atomic_int_fast64_t;
typedef _Atomic(uint_fast64_t) atomic_uint_fast64_t;
typedef _Atomic(intptr_t) atomic_intptr_t;
typedef _Atomic(uintptr_t) atomic_uintptr_t;
typedef _Atomic(size_t) atomic_size_t;
typedef _Atomic(ptrdiff_t) atomic_ptrdiff_t;
typedef _Atomic(intmax_t) atomic_intmax_t;
typedef _Atomic(uintmax_t) atomic_uintmax_t;
/*
* 7.17.7 Operations on atomic types.
*/
/*
* Compiler-specific operations.
*/
#if defined(__CLANG_ATOMICS)
#define atomic_compare_exchange_strong_explicit(object, expected, \
desired, success, failure) \
__c11_atomic_compare_exchange_strong(object, expected, desired, \
success, failure)
#define atomic_compare_exchange_weak_explicit(object, expected, \
desired, success, failure) \
__c11_atomic_compare_exchange_weak(object, expected, desired, \
success, failure)
#define atomic_exchange_explicit(object, desired, order) \
__c11_atomic_exchange(object, desired, order)
#define atomic_fetch_add_explicit(object, operand, order) \
__c11_atomic_fetch_add(object, operand, order)
#define atomic_fetch_and_explicit(object, operand, order) \
__c11_atomic_fetch_and(object, operand, order)
#define atomic_fetch_or_explicit(object, operand, order) \
__c11_atomic_fetch_or(object, operand, order)
#define atomic_fetch_sub_explicit(object, operand, order) \
__c11_atomic_fetch_sub(object, operand, order)
#define atomic_fetch_xor_explicit(object, operand, order) \
__c11_atomic_fetch_xor(object, operand, order)
#define atomic_load_explicit(object, order) \
__c11_atomic_load(object, order)
#define atomic_store_explicit(object, desired, order) \
__c11_atomic_store(object, desired, order)
#elif defined(__GNUC_ATOMICS)
#define atomic_compare_exchange_strong_explicit(object, expected, \
desired, success, failure) \
__atomic_compare_exchange_n(&(object)->__val, expected, \
desired, 0, success, failure)
#define atomic_compare_exchange_weak_explicit(object, expected, \
desired, success, failure) \
__atomic_compare_exchange_n(&(object)->__val, expected, \
desired, 1, success, failure)
#define atomic_exchange_explicit(object, desired, order) \
__atomic_exchange_n(&(object)->__val, desired, order)
#define atomic_fetch_add_explicit(object, operand, order) \
__atomic_fetch_add(&(object)->__val, operand, order)
#define atomic_fetch_and_explicit(object, operand, order) \
__atomic_fetch_and(&(object)->__val, operand, order)
#define atomic_fetch_or_explicit(object, operand, order) \
__atomic_fetch_or(&(object)->__val, operand, order)
#define atomic_fetch_sub_explicit(object, operand, order) \
__atomic_fetch_sub(&(object)->__val, operand, order)
#define atomic_fetch_xor_explicit(object, operand, order) \
__atomic_fetch_xor(&(object)->__val, operand, order)
#define atomic_load_explicit(object, order) \
__atomic_load_n(&(object)->__val, order)
#define atomic_store_explicit(object, desired, order) \
__atomic_store_n(&(object)->__val, desired, order)
#else
#define __atomic_apply_stride(object, operand) \
(((__typeof__((object)->__val))0) + (operand))
#define atomic_compare_exchange_strong_explicit(object, expected, \
desired, success, failure) __extension__ ({ \
__typeof__(expected) __ep = (expected); \
__typeof__(*__ep) __e = *__ep; \
(void)(success); (void)(failure); \
(_Bool)((*__ep = __sync_val_compare_and_swap(&(object)->__val, \
__e, desired)) == __e); \
})
#define atomic_compare_exchange_weak_explicit(object, expected, \
desired, success, failure) \
atomic_compare_exchange_strong_explicit(object, expected, \
desired, success, failure)
#if __has_builtin(__sync_swap)
/* Clang provides a full-barrier atomic exchange - use it if available. */
#define atomic_exchange_explicit(object, desired, order) \
__sync_swap(&(object)->__val, desired)
#else
/*
* __sync_lock_test_and_set() is only an acquire barrier in theory (although in
* practice it is usually a full barrier) so we need an explicit barrier before
* it.
*/
#define atomic_exchange_explicit(object, desired, order) \
__extension__ ({ \
__typeof__(object) __o = (object); \
__typeof__(desired) __d = (desired); \
(void)(order); \
__sync_synchronize(); \
__sync_lock_test_and_set(&(__o)->__val, __d); \
})
#endif
/* Ignoring the order argument when using __sync builtins */
#define atomic_fetch_add_explicit(object, operand, order) \
__sync_fetch_and_add(&(object)->__val, \
__atomic_apply_stride(object, operand))
#define atomic_fetch_and_explicit(object, operand, order) \
__sync_fetch_and_and(&(object)->__val, operand)
#define atomic_fetch_or_explicit(object, operand, order) \
__sync_fetch_and_or(&(object)->__val, operand)
#define atomic_fetch_sub_explicit(object, operand, order) \
__sync_fetch_and_sub(&(object)->__val, \
__atomic_apply_stride(object, operand))
#define atomic_fetch_xor_explicit(object, operand, order) \
__sync_fetch_and_xor(&(object)->__val, operand)
#define atomic_load_explicit(object, order) \
__sync_fetch_and_add(&(object)->__val, 0)
#define atomic_store_explicit(object, desired, order) \
((void)atomic_exchange_explicit(object, desired, order))
#endif
/*
* Convenience functions.
*
* Don't provide these in kernel space. In kernel space, we should be
* disciplined enough to always provide explicit barriers.
*/
#ifndef _KERNEL
#define atomic_compare_exchange_strong(object, expected, desired) \
atomic_compare_exchange_strong_explicit(object, expected, \
desired, memory_order_seq_cst, memory_order_seq_cst)
#define atomic_compare_exchange_weak(object, expected, desired) \
atomic_compare_exchange_weak_explicit(object, expected, \
desired, memory_order_seq_cst, memory_order_seq_cst)
#define atomic_exchange(object, desired) \
atomic_exchange_explicit(object, desired, memory_order_seq_cst)
#define atomic_fetch_add(object, operand) \
atomic_fetch_add_explicit(object, operand, memory_order_seq_cst)
#define atomic_fetch_and(object, operand) \
atomic_fetch_and_explicit(object, operand, memory_order_seq_cst)
#define atomic_fetch_or(object, operand) \
atomic_fetch_or_explicit(object, operand, memory_order_seq_cst)
#define atomic_fetch_sub(object, operand) \
atomic_fetch_sub_explicit(object, operand, memory_order_seq_cst)
#define atomic_fetch_xor(object, operand) \
atomic_fetch_xor_explicit(object, operand, memory_order_seq_cst)
#define atomic_load(object) \
atomic_load_explicit(object, memory_order_seq_cst)
#define atomic_store(object, desired) \
atomic_store_explicit(object, desired, memory_order_seq_cst)
#endif /* !_KERNEL */
/*
* 7.17.8 Atomic flag type and operations.
*
* XXX: Assume atomic_bool can be used as an atomic_flag. Is there some
* kind of compiler built-in type we could use?
*/
typedef struct {
atomic_bool __flag;
} atomic_flag;
#define ATOMIC_FLAG_INIT { ATOMIC_VAR_INIT(0) }
static __inline _Bool
atomic_flag_test_and_set_explicit(volatile atomic_flag *__object,
memory_order __order)
{
return (atomic_exchange_explicit(&__object->__flag, 1, __order));
}
static __inline void
atomic_flag_clear_explicit(volatile atomic_flag *__object, memory_order __order)
{
atomic_store_explicit(&__object->__flag, 0, __order);
}
#ifndef _KERNEL
static __inline _Bool
atomic_flag_test_and_set(volatile atomic_flag *__object)
{
return (atomic_flag_test_and_set_explicit(__object,
memory_order_seq_cst));
}
static __inline void
atomic_flag_clear(volatile atomic_flag *__object)
{
atomic_flag_clear_explicit(__object, memory_order_seq_cst);
}
#endif /* !_KERNEL */
#ifdef __cplusplus
}
#endif
#endif /* STDATOMIC_H */

45
cpu/msp430_common/include/stdio.h
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@ -1,45 +0,0 @@
/*
* Copyright (C) 2015 Eistec AB
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_msp430_common
* @{
*
* @file
* @brief stdio.h wrapper for MSP430
* @see http://www.cplusplus.com/reference/cstdio/
*
* @author Joakim Nohlgård <joakim.nohlgard@eistec.se
*/
#ifndef STDIO_H
#define STDIO_H
/*
* The MSP430 toolchain does not provide getchar in stdio.h.
* As a workaround, we include the system stdio.h here and then add getchar.
*/
#include_next <stdio.h>
#ifdef __cplusplus
extern "C" {
#endif
#define SEEK_SET 0 /* Seek from beginning of file. */
#define SEEK_CUR 1 /* Seek from current position. */
#define SEEK_END 2 /* Seek from end of file. */
int getchar(void);
#ifdef __cplusplus
}
#endif
#endif /* STDIO_H */
/** @} */

41
cpu/msp430_common/include/stdlib.h
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@ -1,41 +0,0 @@
/*
* Copyright (C) 2015 Eistec AB
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_msp430_common
* @{
*
* @file
* @brief stdlib.h wrapper for MSP430
* @see http://www.cplusplus.com/reference/cstdlib/
*
* @author Joakim Nohlgård <joakim.nohlgard@eistec.se
*/
#ifndef STDLIB_H
#define STDLIB_H
/*
* The MSP430 toolchain does not provide malloc, free, calloc etc. in stdlib.h.
* As a workaround, we include the system stdlib.h here and then add malloc.
*/
#include_next <stdlib.h>
#include <malloc.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* STDLIB_H */
/** @} */

711
cpu/msp430_common/include/sys/cdefs.h
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@ -1,711 +0,0 @@
/* libc/sys/linux/sys/cdefs.h - Helper macros for K&R vs. ANSI C compat. */
/* Written 2000 by Werner Almesberger */
/*-
* Copyright (c) 1991, 1993
* The Regents of the University of California. All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* Berkeley Software Design, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)cdefs.h 8.8 (Berkeley) 1/9/95
* $FreeBSD$
*/
/* This file was imported into RIOT from newlib 2.3.0 */
#ifndef SYS_CDEFS_H
#define SYS_CDEFS_H
#include <sys/features.h>
#include <stddef.h>
#ifdef __cplusplus
extern "C" {
#endif
#define __PMT(args) args
#define __DOTS , ...
#define __THROW
#ifdef __GNUC__
# define __ASMNAME(cname) __XSTRING (__USER_LABEL_PREFIX__) cname
#endif
#define __ptr_t void *
#define __long_double_t long double
#define __attribute_malloc__
#define __attribute_pure__
#define __attribute_format_strfmon__(a,b)
#define __flexarr [0]
#ifndef __BOUNDED_POINTERS__
# define __bounded /* nothing */
# define __unbounded /* nothing */
# define __ptrvalue /* nothing */
#endif
/*
* Testing against Clang-specific extensions.
*/
#ifndef __has_attribute
#define __has_attribute(x) 0
#endif
#ifndef __has_extension
#define __has_extension __has_feature
#endif
#ifndef __has_feature
#define __has_feature(x) 0
#endif
#ifndef __has_include
#define __has_include(x) 0
#endif
#ifndef __has_builtin
#define __has_builtin(x) 0
#endif
#if defined(__cplusplus)
#define __BEGIN_DECLS extern "C" {
#define __END_DECLS }
#else
#define __BEGIN_DECLS
#define __END_DECLS
#endif
/*
* This code has been put in place to help reduce the addition of
* compiler specific defines in FreeBSD code. It helps to aid in
* having a compiler-agnostic source tree.
*/
#if defined(__GNUC__) || defined(__INTEL_COMPILER)
#if __GNUC__ >= 3 || defined(__INTEL_COMPILER)
#define __GNUCLIKE_ASM 3
#define __GNUCLIKE_MATH_BUILTIN_CONSTANTS
#else
#define __GNUCLIKE_ASM 2
#endif
#define __GNUCLIKE___TYPEOF 1
#define __GNUCLIKE___OFFSETOF 1
#define __GNUCLIKE___SECTION 1
#ifndef __INTEL_COMPILER
#define __GNUCLIKE_CTOR_SECTION_HANDLING 1
#endif
#define __GNUCLIKE_BUILTIN_CONSTANT_P 1
#if defined(__INTEL_COMPILER) && defined(__cplusplus) && \
__INTEL_COMPILER < 800
#undef __GNUCLIKE_BUILTIN_CONSTANT_P
#endif
#if (__GNUC_MINOR__ > 95 || __GNUC__ >= 3)
#define __GNUCLIKE_BUILTIN_VARARGS 1
#define __GNUCLIKE_BUILTIN_STDARG 1
#define __GNUCLIKE_BUILTIN_VAALIST 1
#endif
#if defined(__GNUC__)
#define __GNUC_VA_LIST_COMPATIBILITY 1
#endif
/*
* Compiler memory barriers, specific to gcc and clang.
*/
#if defined(__GNUC__)
#define __compiler_membar() __asm __volatile(" " : : : "memory")
#endif
#ifndef __INTEL_COMPILER
#define __GNUCLIKE_BUILTIN_NEXT_ARG 1
#define __GNUCLIKE_MATH_BUILTIN_RELOPS
#endif
#define __GNUCLIKE_BUILTIN_MEMCPY 1
/* XXX: if __GNUC__ >= 2: not tested everywhere originally, where replaced */
#define __CC_SUPPORTS_INLINE 1
#define __CC_SUPPORTS___INLINE 1
#define __CC_SUPPORTS___INLINE__ 1
#define __CC_SUPPORTS___FUNC__ 1
#define __CC_SUPPORTS_WARNING 1
#define __CC_SUPPORTS_VARADIC_XXX 1 /* see varargs.h */
#define __CC_SUPPORTS_DYNAMIC_ARRAY_INIT 1
#endif /* __GNUC__ || __INTEL_COMPILER */
/*
* The __CONCAT macro is used to concatenate parts of symbol names, e.g.
* with "#define OLD(foo) __CONCAT(old,foo)", OLD(foo) produces oldfoo.
* The __CONCAT macro is a bit tricky to use if it must work in non-ANSI
* mode -- there must be no spaces between its arguments, and for nested
* __CONCAT's, all the __CONCAT's must be at the left. __CONCAT can also
* concatenate double-quoted strings produced by the __STRING macro, but
* this only works with ANSI C.
*
* __XSTRING is like __STRING, but it expands any macros in its argument
* first. It is only available with ANSI C.
*/
#if defined(__STDC__) || defined(__cplusplus)
#define __P(protos) protos /* full-blown ANSI C */
#define __CONCAT1(x,y) x ## y
#define __CONCAT(x,y) __CONCAT1(x,y)
#define __STRING(x) #x /* stringify without expanding x */
#define __XSTRING(x) __STRING(x) /* expand x, then stringify */
#define __const const /* define reserved names to standard */
#define __signed signed
#define __volatile volatile
#if defined(__cplusplus)
#define __inline inline /* convert to C++ keyword */
#else
#if !(defined(__CC_SUPPORTS___INLINE))
#define __inline /* delete GCC keyword */
#endif /* ! __CC_SUPPORTS___INLINE */
#endif /* !__cplusplus */
#else /* !(__STDC__ || __cplusplus) */
#define __P(protos) () /* traditional C preprocessor */
#define __CONCAT(x,y) x/**/y
#define __STRING(x) "x"
#if !defined(__CC_SUPPORTS___INLINE)
#define __const /* delete pseudo-ANSI C keywords */
#define __inline
#define __signed
#define __volatile
/*
* In non-ANSI C environments, new programs will want ANSI-only C keywords
* deleted from the program and old programs will want them left alone.
* When using a compiler other than gcc, programs using the ANSI C keywords
* const, inline etc. as normal identifiers should define -DNO_ANSI_KEYWORDS.
* When using "gcc -traditional", we assume that this is the intent; if
* __GNUC__ is defined but __STDC__ is not, we leave the new keywords alone.
*/
#ifndef NO_ANSI_KEYWORDS
#define const /* delete ANSI C keywords */
#define inline
#define signed
#define volatile
#endif /* !NO_ANSI_KEYWORDS */
#endif /* !__CC_SUPPORTS___INLINE */
#endif /* !(__STDC__ || __cplusplus) */
/*
* Compiler-dependent macros to help declare dead (non-returning) and
* pure (no side effects) functions, and unused variables. They are
* null except for versions of gcc that are known to support the features
* properly (old versions of gcc-2 supported the dead and pure features
* in a different (wrong) way). If we do not provide an implementation
* for a given compiler, let the compile fail if it is told to use
* a feature that we cannot live without.
*/
#ifdef lint
#define __dead2
#define __pure2
#define __unused
#define __packed
#define __aligned(x)
#define __alloc_align(x)
#define __alloc_size(x)
#define __section(x)
#define __weak_symbol
#else
#define __weak_symbol __attribute__((__weak__))
#if !__GNUC_PREREQ__(2, 5) && !defined(__INTEL_COMPILER)
#define __dead2
#define __pure2
#define __unused
#endif
#if __GNUC__ == 2 && __GNUC_MINOR__ >= 5 && __GNUC_MINOR__ < 7 && !defined(__INTEL_COMPILER)
#define __dead2 __attribute__((__noreturn__))
#define __pure2 __attribute__((__const__))
#define __unused
/* XXX Find out what to do for __packed, __aligned and __section */
#endif
#if __GNUC_PREREQ__(2, 7) || defined(__INTEL_COMPILER)
#define __dead2 __attribute__((__noreturn__))
#define __pure2 __attribute__((__const__))
#define __unused __attribute__((__unused__))
#define __used __attribute__((__used__))
#define __packed __attribute__((__packed__))
#define __aligned(x) __attribute__((__aligned__(x)))
#define __section(x) __attribute__((__section__(x)))
#endif
#if __GNUC_PREREQ__(4, 3) || __has_attribute(__alloc_size__)
#define __alloc_size(x) __attribute__((__alloc_size__(x)))
#else
#define __alloc_size(x)
#endif
#if __GNUC_PREREQ__(4, 9) || __has_attribute(__alloc_align__)
#define __alloc_align(x) __attribute__((__alloc_align__(x)))
#else
#define __alloc_align(x)
#endif
#endif /* lint */
#if !__GNUC_PREREQ__(2, 95)
#define __alignof(x) __offsetof(struct { char __a; x __b; }, __b)
#endif
/*
* Keywords added in C11.
*/
#if !defined(__STDC_VERSION__) || __STDC_VERSION__ < 201112L || defined(lint)
#if !__has_extension(c_alignas)
#if (defined(__cplusplus) && __cplusplus >= 201103L) || \
__has_extension(cxx_alignas)
#define _Alignas(x) alignas(x)
#else
/* XXX: Only emulates _Alignas(constant-expression); not _Alignas(type-name). */
#define _Alignas(x) __aligned(x)
#endif
#endif
#if defined(__cplusplus) && __cplusplus >= 201103L
#define _Alignof(x) alignof(x)
#else
#define _Alignof(x) __alignof(x)
#endif
#if !__has_extension(c_atomic) && !__has_extension(cxx_atomic)
/*
* No native support for _Atomic(). Place object in structure to prevent
* most forms of direct non-atomic access.
*/
#define _Atomic(T) struct { T volatile __val; }
#endif
#if defined(__cplusplus) && __cplusplus >= 201103L
#define _Noreturn [[noreturn]]
#else
#define _Noreturn __dead2
#endif
#if !__has_extension(c_static_assert)
#if (defined(__cplusplus) && __cplusplus >= 201103L) || \
__has_extension(cxx_static_assert)
#define _Static_assert(x, y) static_assert(x, y)
#elif __GNUC_PREREQ__(4,6)
/* Nothing, gcc 4.6 and higher has _Static_assert built-in */
#elif defined(__COUNTER__)
#define _Static_assert(x, y) __Static_assert(x, __COUNTER__)
#define __Static_assert(x, y) ___Static_assert(x, y)
#define ___Static_assert(x, y) typedef char __assert_ ## y[(x) ? 1 : -1] \
__unused
#else
#define _Static_assert(x, y) struct __hack
#endif
#endif
#if !__has_extension(c_thread_local)
/*
* XXX: Some compilers (Clang 3.3, GCC 4.7) falsely announce C++11 mode
* without actually supporting the thread_local keyword. Don't check for
* the presence of C++11 when defining _Thread_local.
*/
#if /* (defined(__cplusplus) && __cplusplus >= 201103L) || */ \
__has_extension(cxx_thread_local)
#define _Thread_local thread_local
#else
#define _Thread_local __thread
#endif
#endif
#endif /* __STDC_VERSION__ || __STDC_VERSION__ < 201112L */
/*
* Emulation of C11 _Generic(). Unlike the previously defined C11
* keywords, it is not possible to implement this using exactly the same
* syntax. Therefore implement something similar under the name
* __generic(). Unlike _Generic(), this macro can only distinguish
* between a single type, so it requires nested invocations to
* distinguish multiple cases.
*/
#if (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L) || \
__has_extension(c_generic_selections)
#define __generic(expr, t, yes, no) \
_Generic(expr, t: yes, default: no)
#elif __GNUC_PREREQ__(3, 1) && !defined(__cplusplus)
#define __generic(expr, t, yes, no) \
__builtin_choose_expr( \
__builtin_types_compatible_p(__typeof(expr), t), yes, no)
#endif
#if __GNUC_PREREQ__(2, 96)
#define __malloc_like __attribute__((__malloc__))
#define __pure __attribute__((__pure__))
#else
#define __malloc_like
#define __pure
#endif
#if __GNUC_PREREQ__(3, 1) || (defined(__INTEL_COMPILER) && __INTEL_COMPILER >= 800)
#define __always_inline __attribute__((__always_inline__))
#else
#define __always_inline
#endif
#if __GNUC_PREREQ__(3, 1)
#define __noinline __attribute__ ((__noinline__))
#else
#define __noinline
#endif
#if __GNUC_PREREQ__(3, 3)
#define __nonnull(x) __attribute__((__nonnull__(x)))
#define __nonnull_all __attribute__((__nonnull__))
#else
#define __nonnull(x)
#define __nonnull_all
#endif
#if __GNUC_PREREQ__(3, 4)
#define __fastcall __attribute__((__fastcall__))
#define __result_use_check __attribute__((__warn_unused_result__))
#else
#define __fastcall
#define __result_use_check
#endif
#if __GNUC_PREREQ__(4, 1)
#define __returns_twice __attribute__((__returns_twice__))
#else
#define __returns_twice
#endif
#if __GNUC_PREREQ__(4, 6) || __has_builtin(__builtin_unreachable)
#define __unreachable() __builtin_unreachable()
#else
#define __unreachable() ((void)0)
#endif
/* XXX: should use `#if __STDC_VERSION__ < 199901'. */
#if !__GNUC_PREREQ__(2, 7) && !defined(__INTEL_COMPILER)
#define __func__ NULL
#endif
/*
* GCC 2.95 provides `__restrict' as an extension to C90 to support the
* C99-specific `restrict' type qualifier. We happen to use `__restrict' as
* a way to define the `restrict' type qualifier without disturbing older
* software that is unaware of C99 keywords.
*/
#if !(__GNUC__ == 2 && __GNUC_MINOR__ == 95)
#if !defined(__STDC_VERSION__) || __STDC_VERSION__ < 199901 || defined(lint)
#define __restrict
#else
#define __restrict restrict
#endif
#endif
/*
* GNU C version 2.96 adds explicit branch prediction so that
* the CPU back-end can hint the processor and also so that
* code blocks can be reordered such that the predicted path
* sees a more linear flow, thus improving cache behavior, etc.
*
* The following two macros provide us with a way to utilize this
* compiler feature. Use __predict_true() if you expect the expression
* to evaluate to true, and __predict_false() if you expect the
* expression to evaluate to false.
*
* A few notes about usage:
*
* * Generally, __predict_false() error condition checks (unless
* you have some _strong_ reason to do otherwise, in which case
* document it), and/or __predict_true() `no-error' condition
* checks, assuming you want to optimize for the no-error case.
*
* * Other than that, if you don't know the likelihood of a test
* succeeding from empirical or other `hard' evidence, don't
* make predictions.
*
* * These are meant to be used in places that are run `a lot'.
* It is wasteful to make predictions in code that is run
* seldom (e.g. at subsystem initialization time) as the
* basic block reordering that this affects can often generate
* larger code.
*/
#if __GNUC_PREREQ__(2, 96)
#define __predict_true(exp) __builtin_expect((exp), 1)
#define __predict_false(exp) __builtin_expect((exp), 0)
#else
#define __predict_true(exp) (exp)
#define __predict_false(exp) (exp)
#endif
#if __GNUC_PREREQ__(4, 0)
#define __sentinel __attribute__((__sentinel__))
#define __exported __attribute__((__visibility__("default")))
#define __hidden __attribute__((__visibility__("hidden")))
#else
#define __sentinel
#define __exported
#define __hidden
#endif
#define __offsetof(type, field) offsetof(type, field)
#define __rangeof(type, start, end) \
(__offsetof(type, end) - __offsetof(type, start))
/*
* Given the pointer x to the member m of the struct s, return
* a pointer to the containing structure. When using GCC, we first
* assign pointer x to a local variable, to check that its type is
* compatible with member m.
*/
#if __GNUC_PREREQ__(3, 1)
#define __containerof(x, s, m) ({ \
const volatile __typeof(((s *)0)->m) *__x = (x); \
__DEQUALIFY(s *, (const volatile char *)__x - __offsetof(s, m));\
})
#else
#define __containerof(x, s, m) \
__DEQUALIFY(s *, (const volatile char *)(x) - __offsetof(s, m))
#endif
/*
* Compiler-dependent macros to declare that functions take printf-like
* or scanf-like arguments. They are null except for versions of gcc
* that are known to support the features properly (old versions of gcc-2
* didn't permit keeping the keywords out of the application namespace).
*/
#if !__GNUC_PREREQ__(2, 7) && !defined(__INTEL_COMPILER)
#define __printflike(fmtarg, firstvararg)
#define __scanflike(fmtarg, firstvararg)
#define __format_arg(fmtarg)
#define __strfmonlike(fmtarg, firstvararg)
#define __strftimelike(fmtarg, firstvararg)
#else
#define __printflike(fmtarg, firstvararg) \
__attribute__((__format__ (__printf__, fmtarg, firstvararg)))
#define __scanflike(fmtarg, firstvararg) \
__attribute__((__format__ (__scanf__, fmtarg, firstvararg)))
#define __format_arg(fmtarg) __attribute__((__format_arg__ (fmtarg)))
#define __strfmonlike(fmtarg, firstvararg) \
__attribute__((__format__ (__strfmon__, fmtarg, firstvararg)))
#define __strftimelike(fmtarg, firstvararg) \
__attribute__((__format__ (__strftime__, fmtarg, firstvararg)))
#endif
/*
* FORTIFY_SOURCE, and perhaps other compiler-specific features, require
* the use of non-standard inlining. In general we should try to avoid
* using these but GCC-compatible compilers tend to support the extensions
* well enough to use them in limited cases.
*/
#if defined(__GNUC_GNU_INLINE__) || defined(__GNUC_STDC_INLINE__)
#if __GNUC_PREREQ__(4, 3) || __has_attribute(__artificial__)
#define __gnu_inline __attribute__((__gnu_inline__, __artificial__))
#else
#define __gnu_inline __attribute__((__gnu_inline__))
#endif /* artificial */
#else
#define __gnu_inline
#endif
/* Compiler-dependent macros that rely on FreeBSD-specific extensions. */
#if defined(__FreeBSD_cc_version) && __FreeBSD_cc_version >= 300001 && \
defined(__GNUC__) && !defined(__INTEL_COMPILER)
#define __printf0like(fmtarg, firstvararg) \
__attribute__((__format__ (__printf0__, fmtarg, firstvararg)))
#else
#define __printf0like(fmtarg, firstvararg)
#endif
#if defined(__GNUC__) || defined(__INTEL_COMPILER)
#ifndef __INTEL_COMPILER
#define __strong_reference(sym,aliassym) \
extern __typeof (sym) aliassym __attribute__ ((__alias__ (#sym)))
#endif
#ifdef __ELF__
#ifdef __STDC__
#define __weak_reference(sym,alias) \
__asm__(".weak " #alias); \
__asm__(".equ " #alias ", " #sym)
#define __warn_references(sym,msg) \
__asm__(".section .gnu.warning." #sym); \
__asm__(".asciz \"" msg "\""); \
__asm__(".previous")
#define __sym_compat(sym,impl,verid) \
__asm__(".symver " #impl ", " #sym "@" #verid)
#define __sym_default(sym,impl,verid) \
__asm__(".symver " #impl ", " #sym "@@" #verid)
#else
#define __weak_reference(sym,alias) \
__asm__(".weak alias"); \
__asm__(".equ alias, sym")
#define __warn_references(sym,msg) \
__asm__(".section .gnu.warning.sym"); \
__asm__(".asciz \"msg\""); \
__asm__(".previous")
#define __sym_compat(sym,impl,verid) \
__asm__(".symver impl, sym@verid")
#define __sym_default(impl,sym,verid) \
__asm__(".symver impl, sym@@verid")
#endif /* __STDC__ */
#else /* !__ELF__ */
#ifdef __STDC__
#define __weak_reference(sym,alias) \
__asm__(".stabs \"_" #alias "\",11,0,0,0"); \
__asm__(".stabs \"_" #sym "\",1,0,0,0")
#define __warn_references(sym,msg) \
__asm__(".stabs \"" msg "\",30,0,0,0"); \
__asm__(".stabs \"_" #sym "\",1,0,0,0")
#else
#define __weak_reference(sym,alias) \
__asm__(".stabs \"_/**/alias\",11,0,0,0"); \
__asm__(".stabs \"_/**/sym\",1,0,0,0")
#define __warn_references(sym,msg) \
__asm__(".stabs msg,30,0,0,0"); \
__asm__(".stabs \"_/**/sym\",1,0,0,0")
#endif /* __STDC__ */
#endif /* __ELF__ */
#endif /* __GNUC__ || __INTEL_COMPILER */
#ifndef __FBSDID
#define __FBSDID(s) struct __hack
#endif
#ifndef __RCSID
#define __RCSID(s) struct __hack
#endif
#ifndef __RCSID_SOURCE
#define __RCSID_SOURCE(s) struct __hack
#endif
#ifndef __SCCSID
#define __SCCSID(s) struct __hack
#endif
#ifndef __COPYRIGHT
#define __COPYRIGHT(s) struct __hack
#endif
#ifndef __DECONST
#define __DECONST(type, var) ((type)(__uintptr_t)(const void *)(var))
#endif
#ifndef __DEVOLATILE
#define __DEVOLATILE(type, var) ((type)(__uintptr_t)(volatile void *)(var))
#endif
#ifndef __DEQUALIFY
#define __DEQUALIFY(type, var) ((type)(__uintptr_t)(const volatile void *)(var))
#endif
/*
* Type Safety Checking
*
* Clang provides additional attributes to enable checking type safety
* properties that cannot be enforced by the C type system.
*/
#if __has_attribute(__argument_with_type_tag__) && \
__has_attribute(__type_tag_for_datatype__) && !defined(lint)
#define __arg_type_tag(arg_kind, arg_idx, type_tag_idx) \
__attribute__((__argument_with_type_tag__(arg_kind, arg_idx, type_tag_idx)))
#define __datatype_type_tag(kind, type) \
__attribute__((__type_tag_for_datatype__(kind, type)))
#else
#define __arg_type_tag(arg_kind, arg_idx, type_tag_idx)
#define __datatype_type_tag(kind, type)
#endif
/*
* Lock annotations.
*
* Clang provides support for doing basic thread-safety tests at
* compile-time, by marking which locks will/should be held when
* entering/leaving a functions.
*
* Furthermore, it is also possible to annotate variables and structure
* members to enforce that they are only accessed when certain locks are
* held.
*/
#if __has_extension(c_thread_safety_attributes)
#define __lock_annotate(x) __attribute__((x))
#else
#define __lock_annotate(x)
#endif
/* Structure implements a lock. */
#define __lockable __lock_annotate(lockable)
/* Function acquires an exclusive or shared lock. */
#define __locks_exclusive(...) \
__lock_annotate(exclusive_lock_function(__VA_ARGS__))
#define __locks_shared(...) \
__lock_annotate(shared_lock_function(__VA_ARGS__))
/* Function attempts to acquire an exclusive or shared lock. */
#define __trylocks_exclusive(...) \
__lock_annotate(exclusive_trylock_function(__VA_ARGS__))
#define __trylocks_shared(...) \
__lock_annotate(shared_trylock_function(__VA_ARGS__))
/* Function releases a lock. */
#define __unlocks(...) __lock_annotate(unlock_function(__VA_ARGS__))
/* Function asserts that an exclusive or shared lock is held. */
#define __asserts_exclusive(...) \
__lock_annotate(assert_exclusive_lock(__VA_ARGS__))
#define __asserts_shared(...) \
__lock_annotate(assert_shared_lock(__VA_ARGS__))
/* Function requires that an exclusive or shared lock is or is not held. */
#define __requires_exclusive(...) \
__lock_annotate(exclusive_locks_required(__VA_ARGS__))
#define __requires_shared(...) \
__lock_annotate(shared_locks_required(__VA_ARGS__))
#define __requires_unlocked(...) \
__lock_annotate(locks_excluded(__VA_ARGS__))
/* Function should not be analyzed. */
#define __no_lock_analysis __lock_annotate(no_thread_safety_analysis)
/* Guard variables and structure members by lock. */
#define __guarded_by(x) __lock_annotate(guarded_by(x))
#define __pt_guarded_by(x) __lock_annotate(pt_guarded_by(x))
#ifdef __cplusplus
}
#endif
#endif /* SYS_CDEFS_H */

514
cpu/msp430_common/include/sys/features.h
View File

@ -1,514 +0,0 @@
/*
* Written by Joel Sherrill <joel@OARcorp.com>.
*
* COPYRIGHT (c) 1989-2014.
*
* On-Line Applications Research Corporation (OAR).
*
* Permission to use, copy, modify, and distribute this software for any
* purpose without fee is hereby granted, provided that this entire notice
* is included in all copies of any software which is or includes a copy
* or modification of this software.
*
* THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY. IN PARTICULAR, THE AUTHOR MAKES NO REPRESENTATION
* OR WARRANTY OF ANY KIND CONCERNING THE MERCHANTABILITY OF THIS
* SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR PURPOSE.
*
* $Id$
*/
/* This file was imported into RIOT from newlib 2.3.0 */
#ifndef SYS_FEATURES_H
#define SYS_FEATURES_H
#ifdef __cplusplus
extern "C" {
#endif
/* Macro to test version of GCC. Returns 0 for non-GCC or too old GCC. */
#ifndef __GNUC_PREREQ
# if defined __GNUC__ && defined __GNUC_MINOR__
# define __GNUC_PREREQ(maj, min) \
((__GNUC__ << 16) + __GNUC_MINOR__ >= ((maj) << 16) + (min))
# else
# define __GNUC_PREREQ(maj, min) 0
# endif
#endif /* __GNUC_PREREQ */
/* Version with trailing underscores for BSD compatibility. */
#define __GNUC_PREREQ__(ma, mi) __GNUC_PREREQ(ma, mi)
/*
* Feature test macros control which symbols are exposed by the system
* headers. Any of these must be defined before including any headers.
*
* __STRICT_ANSI__ (defined by gcc -ansi, -std=c90, -std=c99, or -std=c11)
* ISO C
*
* _POSIX_SOURCE (deprecated by _POSIX_C_SOURCE=1)
* _POSIX_C_SOURCE >= 1
* POSIX.1-1990
*
* _POSIX_C_SOURCE >= 2
* POSIX.2-1992
*
* _POSIX_C_SOURCE >= 199309L
* POSIX.1b-1993 Real-time extensions
*
* _POSIX_C_SOURCE >= 199506L
* POSIX.1c-1995 Threads extensions
*
* _POSIX_C_SOURCE >= 200112L
* POSIX.1-2001 and C99
*
* _POSIX_C_SOURCE >= 200809L
* POSIX.1-2008
*
* _XOPEN_SOURCE
* POSIX.1-1990 and XPG4
*
* _XOPEN_SOURCE_EXTENDED
* SUSv1 (POSIX.2-1992 plus XPG4v2)
*
* _XOPEN_SOURCE >= 500
* SUSv2 (POSIX.1c-1995 plus XSI)
*
* _XOPEN_SOURCE >= 600
* SUSv3 (POSIX.1-2001 plus XSI) and C99
*
* _XOPEN_SOURCE >= 700
* SUSv4 (POSIX.1-2008 plus XSI)
*
* _ISOC99_SOURCE or gcc -std=c99 or g++
* ISO C99
*
* _ISOC11_SOURCE or gcc -std=c11 or g++ -std=c++11
* ISO C11
*
* _ATFILE_SOURCE (implied by _POSIX_C_SOURCE >= 200809L)
* "at" functions
*
* _LARGEFILE_SOURCE (deprecated by _XOPEN_SOURCE >= 500)
* fseeko, ftello
*
* _GNU_SOURCE
* All of the above plus GNU extensions
*
* _BSD_SOURCE (deprecated by _DEFAULT_SOURCE)
* _SVID_SOURCE (deprecated by _DEFAULT_SOURCE)
* _DEFAULT_SOURCE (or none of the above)
* POSIX-1.2008 with BSD and SVr4 extensions
*/
#ifdef _GNU_SOURCE
#undef _ATFILE_SOURCE
#define _ATFILE_SOURCE 1
#undef _DEFAULT_SOURCE
#define _DEFAULT_SOURCE 1
#undef _ISOC99_SOURCE
#define _ISOC99_SOURCE 1
#undef _ISOC11_SOURCE
#define _ISOC11_SOURCE 1
#undef _POSIX_SOURCE
#define _POSIX_SOURCE 1
#undef _POSIX_C_SOURCE
#define _POSIX_C_SOURCE 200809L
#undef _XOPEN_SOURCE
#define _XOPEN_SOURCE 700
#undef _XOPEN_SOURCE_EXTENDED
#define _XOPEN_SOURCE_EXTENDED 1
#endif /* _GNU_SOURCE */
#if defined(_BSD_SOURCE) || defined(_SVID_SOURCE) || \
(!defined(__STRICT_ANSI__) && !defined(_ANSI_SOURCE) && \
!defined(_ISOC99_SOURCE) && !defined(_POSIX_SOURCE) && \
!defined(_POSIX_C_SOURCE) && !defined(_XOPEN_SOURCE))
#undef _DEFAULT_SOURCE
#define _DEFAULT_SOURCE 1
#endif
#if defined(_DEFAULT_SOURCE)
#undef _POSIX_SOURCE
#define _POSIX_SOURCE 1
#undef _POSIX_C_SOURCE
#define _POSIX_C_SOURCE 200809L
#endif
#if !defined(_POSIX_SOURCE) && !defined(_POSIX_C_SOURCE) && \
((!defined(__STRICT_ANSI__) && !defined(_ANSI_SOURCE)) || \
(_XOPEN_SOURCE - 0) >= 500)
#define _POSIX_SOURCE 1
#if !defined(_XOPEN_SOURCE) || (_XOPEN_SOURCE - 0) >= 700
#define _POSIX_C_SOURCE 200809L
#elif (_XOPEN_SOURCE - 0) >= 600
#define _POSIX_C_SOURCE 200112L
#elif (_XOPEN_SOURCE - 0) >= 500
#define _POSIX_C_SOURCE 199506L
#elif (_XOPEN_SOURCE - 0) < 500
#define _POSIX_C_SOURCE 2
#endif
#endif
#if defined(_POSIX_C_SOURCE) && _POSIX_C_SOURCE >= 200809
#undef _ATFILE_SOURCE
#define _ATFILE_SOURCE 1
#endif
/*
* The following private macros are used throughout the headers to control
* which symbols should be exposed. They are for internal use only, as
* indicated by the leading double underscore, and must never be used outside
* of these headers.
*
* __POSIX_VISIBLE
* any version of POSIX.1; enabled by default, or with _POSIX_SOURCE,
* any value of _POSIX_C_SOURCE, or _XOPEN_SOURCE >= 500.
*
* __POSIX_VISIBLE >= 2
* POSIX.2-1992; enabled by default, with _POSIX_C_SOURCE >= 2,
* or _XOPEN_SOURCE >= 500.
*
* __POSIX_VISIBLE >= 199309
* POSIX.1b-1993; enabled by default, with _POSIX_C_SOURCE >= 199309L,
* or _XOPEN_SOURCE >= 500.
*
* __POSIX_VISIBLE >= 199506
* POSIX.1c-1995; enabled by default, with _POSIX_C_SOURCE >= 199506L,
* or _XOPEN_SOURCE >= 500.
*
* __POSIX_VISIBLE >= 200112
* POSIX.1-2001; enabled by default, with _POSIX_C_SOURCE >= 200112L,
* or _XOPEN_SOURCE >= 600.
*
* __POSIX_VISIBLE >= 200809
* POSIX.1-2008; enabled by default, with _POSIX_C_SOURCE >= 200809L,
* or _XOPEN_SOURCE >= 700.
*
* __XSI_VISIBLE
* XPG4 XSI extensions; enabled with any version of _XOPEN_SOURCE.
*
* __XSI_VISIBLE >= 4
* SUSv1 XSI extensions; enabled with both _XOPEN_SOURCE and
* _XOPEN_SOURCE_EXTENDED together.
*
* __XSI_VISIBLE >= 500
* SUSv2 XSI extensions; enabled with _XOPEN_SOURCE >= 500.
*
* __XSI_VISIBLE >= 600
* SUSv3 XSI extensions; enabled with _XOPEN_SOURCE >= 600.
*
* __XSI_VISIBLE >= 700
* SUSv4 XSI extensions; enabled with _XOPEN_SOURCE >= 700.
*
* __ISO_C_VISIBLE >= 1999
* ISO C99; enabled with gcc -std=c99 or newer (on by default since GCC 5),
* any version of C++, or with _ISOC99_SOURCE, _POSIX_C_SOURCE >= 200112L,
* or _XOPEN_SOURCE >= 600.
*
* __ISO_C_VISIBLE >= 2011
* ISO C11; enabled with gcc -std=c11 or newer (on by default since GCC 5),
* g++ -std=c++11 or newer (on by default since GCC 6), or with
* _ISOC11_SOURCE.
*
* __ATFILE_VISIBLE
* "at" functions; enabled by default, with _ATFILE_SOURCE,
* _POSIX_C_SOURCE >= 200809L, or _XOPEN_SOURCE >= 700.
*
* __LARGEFILE_VISIBLE
* fseeko, ftello; enabled with _LARGEFILE_SOURCE or _XOPEN_SOURCE >= 500.
*
* __BSD_VISIBLE
* BSD extensions; enabled by default, or with _BSD_SOURCE.
*
* __SVID_VISIBLE
* SVr4 extensions; enabled by default, or with _SVID_SOURCE.
*
* __MISC_VISIBLE
* Extensions found in both BSD and SVr4 (shorthand for
* (__BSD_VISIBLE || __SVID_VISIBLE)), or newlib-specific
* extensions; enabled by default.
*
* __GNU_VISIBLE
* GNU extensions; enabled with _GNU_SOURCE.
*
* In all cases above, "enabled by default" means either by defining
* _DEFAULT_SOURCE, or by not defining any of the public feature test macros.
* Defining _GNU_SOURCE makes all of the above available.
*/
#ifdef _ATFILE_SOURCE
#define __ATFILE_VISIBLE 1
#else
#define __ATFILE_VISIBLE 0
#endif
#ifdef _DEFAULT_SOURCE
#define __BSD_VISIBLE 1
#else
#define __BSD_VISIBLE 0
#endif
#ifdef _GNU_SOURCE
#define __GNU_VISIBLE 1
#else
#define __GNU_VISIBLE 0
#endif
#if defined(_ISOC11_SOURCE) || \
(__STDC_VERSION__ - 0) >= 201112L || (__cplusplus - 0) >= 201103L
#define __ISO_C_VISIBLE 2011
#elif defined(_ISOC99_SOURCE) || (_POSIX_C_SOURCE - 0) >= 200112L || \
(__STDC_VERSION__ - 0) >= 199901L || defined(__cplusplus)
#define __ISO_C_VISIBLE 1999
#else
#define __ISO_C_VISIBLE 1990
#endif
#if defined(_LARGEFILE_SOURCE) || (_XOPEN_SOURCE - 0) >= 500
#define __LARGEFILE_VISIBLE 1
#else
#define __LARGEFILE_VISIBLE 0
#endif
#ifdef _DEFAULT_SOURCE
#define __MISC_VISIBLE 1
#else
#define __MISC_VISIBLE 0
#endif
#if (_POSIX_C_SOURCE - 0) >= 200809L
#define __POSIX_VISIBLE 200809
#elif (_POSIX_C_SOURCE - 0) >= 200112L
#define __POSIX_VISIBLE 200112
#elif (_POSIX_C_SOURCE - 0) >= 199506L
#define __POSIX_VISIBLE 199506
#elif (_POSIX_C_SOURCE - 0) >= 199309L
#define __POSIX_VISIBLE 199309
#elif (_POSIX_C_SOURCE - 0) >= 2 || defined(_XOPEN_SOURCE)
#define __POSIX_VISIBLE 199209
#elif defined(_POSIX_SOURCE) || defined(_POSIX_C_SOURCE)
#define __POSIX_VISIBLE 199009
#else
#define __POSIX_VISIBLE 0
#endif
#ifdef _DEFAULT_SOURCE
#define __SVID_VISIBLE 1
#else
#define __SVID_VISIBLE 0
#endif
#if (_XOPEN_SOURCE - 0) >= 700
#define __XSI_VISIBLE 700
#elif (_XOPEN_SOURCE - 0) >= 600
#define __XSI_VISIBLE 600
#elif (_XOPEN_SOURCE - 0) >= 500
#define __XSI_VISIBLE 500
#elif defined(_XOPEN_SOURCE) && defined(_XOPEN_SOURCE_EXTENDED)
#define __XSI_VISIBLE 4
#elif defined(_XOPEN_SOURCE)
#define __XSI_VISIBLE 1
#else
#define __XSI_VISIBLE 0
#endif
/* RTEMS adheres to POSIX -- 1003.1b with some features from annexes. */
#ifdef __rtems__
#define _POSIX_JOB_CONTROL 1
#define _POSIX_SAVED_IDS 1
#define _POSIX_VERSION 199309L
#define _POSIX_ASYNCHRONOUS_IO 1
#define _POSIX_FSYNC 1
#define _POSIX_MAPPED_FILES 1
#define _POSIX_MEMLOCK 1
#define _POSIX_MEMLOCK_RANGE 1
#define _POSIX_MEMORY_PROTECTION 1
#define _POSIX_MESSAGE_PASSING 1
#define _POSIX_MONOTONIC_CLOCK 200112L
#define _POSIX_PRIORITIZED_IO 1
#define _POSIX_PRIORITY_SCHEDULING 1
#define _POSIX_REALTIME_SIGNALS 1
#define _POSIX_SEMAPHORES 1
/* #define _POSIX_SHARED_MEMORY_OBJECTS 1 */
#define _POSIX_SYNCHRONIZED_IO 1
#define _POSIX_TIMERS 1
#define _POSIX_BARRIERS 200112L
#define _POSIX_READER_WRITER_LOCKS 200112L
#define _POSIX_SPIN_LOCKS 200112L
/* In P1003.1b but defined by drafts at least as early as P1003.1c/D10 */
#define _POSIX_THREADS 1
#define _POSIX_THREAD_ATTR_STACKADDR 1
#define _POSIX_THREAD_ATTR_STACKSIZE 1
#define _POSIX_THREAD_PRIORITY_SCHEDULING 1
#define _POSIX_THREAD_PRIO_INHERIT 1
#define _POSIX_THREAD_PRIO_PROTECT 1
#define _POSIX_THREAD_PROCESS_SHARED 1
#define _POSIX_THREAD_SAFE_FUNCTIONS 1
/* P1003.4b/D8 defines the constants below this comment. */
#define _POSIX_SPAWN 1
#define _POSIX_TIMEOUTS 1
#define _POSIX_CPUTIME 1
#define _POSIX_THREAD_CPUTIME 1
#define _POSIX_SPORADIC_SERVER 1
#define _POSIX_THREAD_SPORADIC_SERVER 1
#define _POSIX_DEVICE_CONTROL 1
#define _POSIX_DEVCTL_DIRECTION 1
#define _POSIX_INTERRUPT_CONTROL 1
#define _POSIX_ADVISORY_INFO 1
/* UNIX98 added some new pthread mutex attributes */
#define _UNIX98_THREAD_MUTEX_ATTRIBUTES 1
#endif
/* XMK loosely adheres to POSIX -- 1003.1 */
#ifdef __XMK__
#define _POSIX_THREADS 1
#define _POSIX_THREAD_PRIORITY_SCHEDULING 1
#endif
#ifdef __svr4__
# define _POSIX_JOB_CONTROL 1
# define _POSIX_SAVED_IDS 1
# define _POSIX_VERSION 199009L
#endif
#ifdef __CYGWIN__
#if __POSIX_VISIBLE >= 200809
#define _POSIX_VERSION 200809L
#define _POSIX2_VERSION 200809L
#elif __POSIX_VISIBLE >= 200112
#define _POSIX_VERSION 200112L
#define _POSIX2_VERSION 200112L
#elif __POSIX_VISIBLE >= 199506
#define _POSIX_VERSION 199506L
#define _POSIX2_VERSION 199506L
#elif __POSIX_VISIBLE >= 199309
#define _POSIX_VERSION 199309L
#define _POSIX2_VERSION 199209L
#elif __POSIX_VISIBLE >= 199209
#define _POSIX_VERSION 199009L
#define _POSIX2_VERSION 199209L
#elif __POSIX_VISIBLE
#define _POSIX_VERSION 199009L
#endif
#if __XSI_VISIBLE >= 4
#define _XOPEN_VERSION __XSI_VISIBLE
#endif
#define _POSIX_ADVISORY_INFO 200809L
/* #define _POSIX_ASYNCHRONOUS_IO -1 */
#define _POSIX_BARRIERS 200809L
#define _POSIX_CHOWN_RESTRICTED 1
#define _POSIX_CLOCK_SELECTION 200809L
#define _POSIX_CPUTIME 200809L
#define _POSIX_FSYNC 200809L
#define _POSIX_IPV6 200809L
#define _POSIX_JOB_CONTROL 1
#define _POSIX_MAPPED_FILES 200809L
/* #define _POSIX_MEMLOCK -1 */
#define _POSIX_MEMLOCK_RANGE 200809L
#define _POSIX_MEMORY_PROTECTION 200809L
#define _POSIX_MESSAGE_PASSING 200809L
#define _POSIX_MONOTONIC_CLOCK 200809L
#define _POSIX_NO_TRUNC 1
/* #define _POSIX_PRIORITIZED_IO -1 */
#define _POSIX_PRIORITY_SCHEDULING 200809L
#define _POSIX_RAW_SOCKETS 200809L
#define _POSIX_READER_WRITER_LOCKS 200809L
#define _POSIX_REALTIME_SIGNALS 200809L
#define _POSIX_REGEXP 1
#define _POSIX_SAVED_IDS 1
#define _POSIX_SEMAPHORES 200809L
#define _POSIX_SHARED_MEMORY_OBJECTS 200809L
#define _POSIX_SHELL 1
#define _POSIX_SPAWN 200809L
#define _POSIX_SPIN_LOCKS 200809L
/* #define _POSIX_SPORADIC_SERVER -1 */
#define _POSIX_SYNCHRONIZED_IO 200809L
#define _POSIX_THREAD_ATTR_STACKADDR 200809L
#define _POSIX_THREAD_ATTR_STACKSIZE 200809L
#define _POSIX_THREAD_CPUTIME 200809L
/* #define _POSIX_THREAD_PRIO_INHERIT -1 */
/* #define _POSIX_THREAD_PRIO_PROTECT -1 */
#define _POSIX_THREAD_PRIORITY_SCHEDULING 200809L
#define _POSIX_THREAD_PROCESS_SHARED 200809L
#define _POSIX_THREAD_SAFE_FUNCTIONS 200809L
/* #define _POSIX_THREAD_SPORADIC_SERVER -1 */
#define _POSIX_THREADS 200809L
/* #define _POSIX_TIMEOUTS -1 */
#define _POSIX_TIMERS 200809L
/* #define _POSIX_TRACE -1 */
/* #define _POSIX_TRACE_EVENT_FILTER -1 */
/* #define _POSIX_TRACE_INHERIT -1 */
/* #define _POSIX_TRACE_LOG -1 */
/* #define _POSIX_TYPED_MEMORY_OBJECTS -1 */
#define _POSIX_VDISABLE '\0'
#if __POSIX_VISIBLE >= 2
#define _POSIX2_C_VERSION _POSIX2_VERSION
#define _POSIX2_C_BIND _POSIX2_VERSION
#define _POSIX2_C_DEV _POSIX2_VERSION
#define _POSIX2_CHAR_TERM _POSIX2_VERSION
/* #define _POSIX2_FORT_DEV -1 */
/* #define _POSIX2_FORT_RUN -1 */
/* #define _POSIX2_LOCALEDEF -1 */
/* #define _POSIX2_PBS -1 */
/* #define _POSIX2_PBS_ACCOUNTING -1 */
/* #define _POSIX2_PBS_CHECKPOINT -1 */
/* #define _POSIX2_PBS_LOCATE -1 */
/* #define _POSIX2_PBS_MESSAGE -1 */
/* #define _POSIX2_PBS_TRACK -1 */
#define _POSIX2_SW_DEV _POSIX2_VERSION
#define _POSIX2_UPE _POSIX2_VERSION
#endif /* __POSIX_VISIBLE >= 2 */
#define _POSIX_V6_ILP32_OFF32 -1
#ifdef __LP64__
#define _POSIX_V6_ILP32_OFFBIG -1
#define _POSIX_V6_LP64_OFF64 1
#define _POSIX_V6_LPBIG_OFFBIG 1
#else
#define _POSIX_V6_ILP32_OFFBIG 1
#define _POSIX_V6_LP64_OFF64 -1
#define _POSIX_V6_LPBIG_OFFBIG -1
#endif
#define _POSIX_V7_ILP32_OFF32 _POSIX_V6_ILP32_OFF32
#define _POSIX_V7_ILP32_OFFBIG _POSIX_V6_ILP32_OFFBIG
#define _POSIX_V7_LP64_OFF64 _POSIX_V6_LP64_OFF64
#define _POSIX_V7_LPBIG_OFFBIG _POSIX_V6_LPBIG_OFFBIG
#define _XBS5_ILP32_OFF32 _POSIX_V6_ILP32_OFF32
#define _XBS5_ILP32_OFFBIG _POSIX_V6_ILP32_OFFBIG
#define _XBS5_LP64_OFF64 _POSIX_V6_LP64_OFF64
#define _XBS5_LPBIG_OFFBIG _POSIX_V6_LPBIG_OFFBIG
#if __XSI_VISIBLE
#define _XOPEN_CRYPT 1
#define _XOPEN_ENH_I18N 1
/* #define _XOPEN_LEGACY -1 */
/* #define _XOPEN_REALTIME -1 */
/* #define _XOPEN_REALTIME_THREADS -1 */
#define _XOPEN_SHM 1
/* #define _XOPEN_STREAMS -1 */
/* #define _XOPEN_UNIX -1 */
#endif /* __XSI_VISIBLE */
/* The value corresponds to UNICODE version 4.0, which is the version
supported by XP. Newlib supports 5.2 (2011) but so far Cygwin needs
the MS conversions for double-byte charsets. */
#define __STDC_ISO_10646__ 200305L
#endif /* __CYGWIN__ */
#ifdef __cplusplus
}
#endif
#endif /* SYS_FEATURES_H */

131
cpu/msp430_common/include/sys/stat.h
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@ -1,131 +0,0 @@
/*
* Copyright (C) 2016 Eistec AB
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_msp430_common
*
* @{
* @file
* @brief POSIX compatible sys/stat.h definitions
* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
*/
/* If building on native we need to use the system libraries instead */
#ifdef CPU_NATIVE
#pragma GCC system_header
/* without the GCC pragma above #include_next will trigger a pedantic error */
#include_next <sys/stat.h>
#else
#ifndef SYS_STAT_H
#define SYS_STAT_H
#include <time.h> /* for struct timespec */
#include <sys/types.h> /* for fsblkcnt_t, fsfilcnt_t */
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief File information
*/
struct stat {
dev_t st_dev; /**< Device ID of device containing file. */
ino_t st_ino; /**< File serial number. */
mode_t st_mode; /**< Mode of file (see below). */
nlink_t st_nlink; /**< Number of hard links to the file. */
uid_t st_uid; /**< User ID of file. */
gid_t st_gid; /**< Group ID of file. */
dev_t st_rdev; /**< Device ID (if file is character or block special). */
/**
* For regular files, the file size in bytes.
* For symbolic links, the length in bytes of the pathname contained in the
* symbolic link.
* For a shared memory object, the length in bytes.
* For a typed memory object, the length in bytes.
* For other file types, the use of this field is unspecified.
*/
off_t st_size;
struct timespec st_atim; /**< Last data access timestamp. */
struct timespec st_mtim; /**< Last data modification timestamp. */
struct timespec st_ctim; /**< Last file status change timestamp. */
/**
* A file system-specific preferred I/O block size for this object. In some
* file system types, this may vary from file to file.
*/
blksize_t st_blksize;
blkcnt_t st_blocks; /**< Number of blocks allocated for this object. */
};
/* These bitmasks and numbers are the same as in newlib */
#define S_IFMT 0170000 /* type of file */
#define S_IFDIR 0040000 /* directory */
#define S_IFCHR 0020000 /* character special */
#define S_IFBLK 0060000 /* block special */
#define S_IFREG 0100000 /* regular */
#define S_IFLNK 0120000 /* symbolic link */
#define S_IFSOCK 0140000 /* socket */
#define S_IFIFO 0010000 /* fifo */
/* These numbers are well-known and can be found in the manual page for sys_stat.h */
#define S_IRWXU 0700 /**< Read, write, execute/search by owner. */
#define S_IRUSR 0400 /**< Read permission, owner. */
#define S_IWUSR 0200 /**< Write permission, owner. */
#define S_IXUSR 0100 /**< Execute/search permission, owner. */
#define S_IRWXG 070 /**< Read, write, execute/search by group. */
#define S_IRGRP 040 /**< Read permission, group. */
#define S_IWGRP 020 /**< Write permission, group. */
#define S_IXGRP 010 /**< Execute/search permission, group. */
#define S_IRWXO 07 /**< Read, write, execute/search by others. */
#define S_IROTH 04 /**< Read permission, others. */
#define S_IWOTH 02 /**< Write permission, others. */
#define S_IXOTH 01 /**< Execute/search permission, others. */
#define S_ISUID 04000 /**< Set-user-ID on execution. */
#define S_ISGID 02000 /**< Set-group-ID on execution. */
#define S_ISVTX 01000 /**< On directories, restricted deletion flag */
/* File type test macros, taken from newlib */
#define S_ISBLK(m) (((m) & S_IFMT) == S_IFBLK)
#define S_ISCHR(m) (((m) & S_IFMT) == S_IFCHR)
#define S_ISDIR(m) (((m) & S_IFMT) == S_IFDIR)
#define S_ISFIFO(m) (((m) & S_IFMT) == S_IFIFO)
#define S_ISREG(m) (((m) & S_IFMT) == S_IFREG)
#define S_ISLNK(m) (((m) & S_IFMT) == S_IFLNK)
#define S_ISSOCK(m) (((m) & S_IFMT) == S_IFSOCK)
/* These function prototypes are required by the standard */
int chmod(const char *, mode_t);
int fchmod(int, mode_t);
int fchmodat(int, const char *, mode_t, int);
int fstat(int, struct stat *);
int fstatat(int, const char *restrict, struct stat *restrict, int);
int futimens(int, const struct timespec [2]);
int lstat(const char *restrict, struct stat *restrict);
int mkdir(const char *, mode_t);
int mkdirat(int, const char *, mode_t);
int mkfifo(const char *, mode_t);
int mkfifoat(int, const char *, mode_t);
int mknod(const char *, mode_t, dev_t);
int mknodat(int, const char *, mode_t, dev_t);
int stat(const char *restrict, struct stat *restrict);
mode_t umask(mode_t);
int utimensat(int, const char *, const struct timespec [2], int);
/* Special tv_nsec values for futimens(2) and utimensat(2). */
#define UTIME_NOW (-2L)
#define UTIME_OMIT (-1L)
#ifdef __cplusplus
}
#endif
#endif /* SYS_STAT_H */
#endif /* CPU_NATIVE */
/** @} */

22
cpu/msp430_common/include/sys/time.h
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@ -1,22 +0,0 @@
/*
* Copyright (C) 2014 INRIA
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
#ifndef SYS_TIME_H
#define SYS_TIME_H
#include "msp430_types.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* SYS_TIME_H */

22
cpu/msp430_common/include/sys/types.h
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@ -1,22 +0,0 @@
/*
* Copyright (C) 2014 INRIA
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
#ifndef SYS_TYPES_H
#define SYS_TYPES_H
#include "msp430_types.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* SYS_TYPES_H */

51
cpu/msp430_common/include/time.h
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@ -1,51 +0,0 @@
/*
* Copyright (C) 2014 INRIA
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_msp430_common
* @{
*
* @file
* @brief time.h for msp430
* @see http://pubs.opengroup.org/onlinepubs/9699919799/basedefs/assert.h.html
*
* @author Martine Lenders <mlenders@inf.fu-berlin.de>
*/
#ifndef TIME_H
#define TIME_H
#include <sys/types.h>
#include "msp430_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Datatype to represent time.
*/
struct tm {
int tm_sec; /**< Seconds after the minute [0, 60] */
int tm_min; /**< Minutes after the hour [0, 59] */
int tm_hour; /**< Hours since midnight [0, 23] */
int tm_mday; /**< Day of the month [1, 31] */
int tm_mon; /**< Months since January [0, 11] */
int tm_year; /**< Years since 1900 */
int tm_wday; /**< Days since Sunday [0, 6] */
int tm_yday; /**< Days since January 1st [0, 365] */
int tm_isdst; /**< Daylight saving time is in effect
* (positive if true, 0 if not, negative if n/a) */
};
#ifdef __cplusplus
}
#endif
#endif /* TIME_H */
/** @} */

119
cpu/msp430_common/include/unistd.h
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@ -1,119 +0,0 @@
/*
* Copyright (C) 2016 Eistec AB
* Copyright (C) 2015 Kaspar Schleiser <kaspar@schleiser.de>
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_msp430_common
* @{
*
* @file
* @brief unistd.h wrapper for MSP430
*/
#ifndef UNISTD_H
#define UNISTD_H
#include <stddef.h>
#include <stdint.h>
#include <sys/types.h>
#ifdef __cplusplus
extern "C" {
#endif
#define STDIN_FILENO 0 /* standard input file descriptor */
#define STDOUT_FILENO 1 /* standard output file descriptor */
#define STDERR_FILENO 2 /* standard error file descriptor */
#define F_OK 0
#define R_OK 4
#define W_OK 2
#define X_OK 1
#define SEEK_SET 0
#define SEEK_CUR 1
#define SEEK_END 2
int access(const char *, int);
unsigned alarm(unsigned);
int chdir(const char *);
int chown(const char *, uid_t, gid_t);
int close(int);
size_t confstr(int, char *, size_t);
int dup(int);
int dup2(int, int);
void _exit(int);
int execl(const char *, const char *, ...);
int execle(const char *, const char *, ...);
int execlp(const char *, const char *, ...);
int execv(const char *, char *const []);
int execve(const char *, char *const [], char *const []);
int execvp(const char *, char *const []);
int faccessat(int, const char *, int, int);
int fchdir(int);
int fchown(int, uid_t, gid_t);
int fchownat(int, const char *, uid_t, gid_t, int);
int fexecve(int, char *const [], char *const []);
pid_t fork(void);
long fpathconf(int, int);
int ftruncate(int, off_t);
char *getcwd(char *, size_t);
gid_t getegid(void);
uid_t geteuid(void);
gid_t getgid(void);
int getgroups(int, gid_t []);
int gethostname(char *, size_t);
char *getlogin(void);
int getlogin_r(char *, size_t);
int getopt(int, char * const [], const char *);
pid_t getpgid(pid_t);
pid_t getpgrp(void);
pid_t getpid(void);
pid_t getppid(void);
pid_t getsid(pid_t);
uid_t getuid(void);
int isatty(int);
int lchown(const char *, uid_t, gid_t);
int link(const char *, const char *);
int linkat(int, const char *, int, const char *, int);
off_t lseek(int, off_t, int);
long pathconf(const char *, int);
int pause(void);
int pipe(int [2]);
ssize_t pread(int, void *, size_t, off_t);
ssize_t pwrite(int, const void *, size_t, off_t);
ssize_t read(int, void *, size_t);
ssize_t readlink(const char *restrict, char *restrict, size_t);
ssize_t readlinkat(int, const char *restrict, char *restrict, size_t);
int rmdir(const char *);
int setegid(gid_t);
int seteuid(uid_t);
int setgid(gid_t);
int setpgid(pid_t, pid_t);
pid_t setsid(void);
int setuid(uid_t);
unsigned sleep(unsigned);
int symlink(const char *, const char *);
int symlinkat(const char *, int, const char *);
long sysconf(int);
pid_t tcgetpgrp(int);
int tcsetpgrp(int, pid_t);
int truncate(const char *, off_t);
char *ttyname(int);
int ttyname_r(int, char *, size_t);
int unlink(const char *);
int unlinkat(int, const char *, int);
int usleep(useconds_t);
ssize_t write(int, const void *, size_t);
#ifdef __cplusplus
}
#endif
#endif /* UNISTD_H */
/** @} */

2
cpu/msp430_common/irq.c
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@ -23,5 +23,3 @@
#include "cpu.h"
volatile int __irq_is_in = 0;
char __isr_stack[ISR_STACKSIZE];

486
cpu/msp430_common/malloc.c
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@ -1,486 +0,0 @@
/*
* Copyright (c) 2002, 2004, 2010 Joerg Wunsch
* Copyright (c) 2010 Gerben van den Broeke
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* 3. Neither the name of the copyright holders nor the names of
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* Modified by Gunar Schorcht
*/
/**
* @ingroup cpu
* @{
*
* @file
* @brief MSP430 malloc/free memory management functions
*
* AVR libc functions adapted for MSP430 CPUs.
*
* @author Gunar Schorcht <gunar@schorcht.net>
*
* @}
*/
#include <stdio.h>
#include <stdlib.h>
#include "irq.h"
#ifdef MODULE_MSP430_MALLOC
#define asmv(arg) __asm__ __volatile__(arg)
#define STACK_EXTRA 32
#define __brkval cur_break
#define __malloc_heap_end __heap_end
/* May be changed by the user only before the first malloc() call. */
extern int _end; /* provided by linker script */
extern char *cur_break;
extern char *__heap_end;
struct __freelist {
size_t sz;
struct __freelist *nx;
};
size_t __malloc_margin = STACK_EXTRA;
char *__malloc_heap_start = (char*)&_end;
struct __freelist *__flp;
void *
malloc(size_t len)
{
struct __freelist *fp1, *fp2, *sfp1, *sfp2;
char *cp;
size_t s;
unsigned state;
state = irq_disable();
/*
* Our minimum chunk size is the size of a pointer (plus the
* size of the "sz" field, but we don't need to account for
* this), otherwise we could not possibly fit a freelist entry
* into the chunk later.
*/
if (len < sizeof(struct __freelist) - sizeof(size_t)) {
len = sizeof(struct __freelist) - sizeof(size_t);
}
/*
* First, walk the free list and try finding a chunk that
* would match exactly. If we found one, we are done. While
* walking, note down the smallest chunk we found that would
* still fit the request -- we need it for step 2.
*
*/
for (s = 0, fp1 = __flp, fp2 = 0; fp1; fp2 = fp1, fp1 = fp1->nx) {
if (fp1->sz < len) {
continue;
}
if (fp1->sz == len) {
/*
* Found it. Disconnect the chunk from the
* freelist, and return it.
*/
if (fp2) {
fp2->nx = fp1->nx;
}
else {
__flp = fp1->nx;
}
irq_restore(state);
return &(fp1->nx);
}
else {
if (s == 0 || fp1->sz < s) {
/* this is the smallest chunk found so far */
s = fp1->sz;
sfp1 = fp1;
sfp2 = fp2;
}
}
}
/*
* Step 2: If we found a chunk on the freelist that would fit
* (but was too large), look it up again and use it, since it
* is our closest match now. Since the freelist entry needs
* to be split into two entries then, watch out that the
* difference between the requested size and the size of the
* chunk found is large enough for another freelist entry; if
* not, just enlarge the request size to what we have found,
* and use the entire chunk.
*/
if (s) {
if (s - len < sizeof(struct __freelist)) {
/* Disconnect it from freelist and return it. */
if (sfp2) {
sfp2->nx = sfp1->nx;
}
else {
__flp = sfp1->nx;
}
irq_restore(state);
return &(sfp1->nx);
}
/*
* Split them up. Note that we leave the first part
* as the new (smaller) freelist entry, and return the
* upper portion to the caller. This saves us the
* work to fix up the freelist chain; we just need to
* fixup the size of the current entry, and note down
* the size of the new chunk before returning it to
* the caller.
*/
cp = (char *)sfp1;
s -= len;
cp += s;
sfp2 = (struct __freelist *)cp;
sfp2->sz = len;
sfp1->sz = s - sizeof(size_t);
irq_restore(state);
return &(sfp2->nx);
}
/*
* Step 3: If the request could not be satisfied from a
* freelist entry, just prepare a new chunk. This means we
* need to obtain more memory first. The largest address just
* not allocated so far is remembered in the brkval variable.
* Under Unix, the "break value" was the end of the data
* segment as dynamically requested from the operating system.
* Since we don't have an operating system, just make sure
* that we don't collide with the stack.
*/
size_t avail;
if (__brkval == NULL) {
__brkval = __malloc_heap_start;
}
cp = __malloc_heap_end;
if (cp == NULL) {
char *stack_pointer;
asmv("mov r1, %0" : "=r"(stack_pointer));
cp = stack_pointer - __malloc_margin;
}
if (cp <= __brkval) {
/*
* Memory exhausted.
*/
irq_restore(state);
return 0;
}
avail = cp - __brkval;
/*
* Both tests below are needed to catch the case len >= 0xfffe.
*/
if (avail >= len && avail >= len + sizeof(size_t)) {
fp1 = (struct __freelist *)__brkval;
__brkval += len + sizeof(size_t);
fp1->sz = len;
irq_restore(state);
return &(fp1->nx);
}
/*
* Step 4: There's no help, just fail. :-/
*/
irq_restore(state);
return 0;
}
void
free(void *p)
{
struct __freelist *fp1, *fp2, *fpnew;
char *cp1, *cp2, *cpnew;
unsigned state;
state = irq_disable();
if (__brkval == NULL) {
__brkval = __malloc_heap_start;
}
/* ISO C says free(NULL) must be a no-op */
if (p == NULL) {
irq_restore(state);
return;
}
cpnew = p;
cpnew -= sizeof(size_t);
fpnew = (struct __freelist *)cpnew;
fpnew->nx = 0;
/*
* Trivial case first: if there's no freelist yet, our entry
* will be the only one on it. If this is the last entry, we
* can reduce __brkval instead.
*/
if (__flp == NULL) {
if ((char *)p + fpnew->sz == __brkval) {
__brkval = cpnew;
}
else {
__flp = fpnew;
}
irq_restore(state);
return;
}
/*
* Now, find the position where our new entry belongs onto the
* freelist. Try to aggregate the chunk with adjacent chunks
* if possible.
*/
for (fp1 = __flp, fp2 = 0;
fp1;
fp2 = fp1, fp1 = fp1->nx) {
if (fp1 < fpnew) {
continue;
}
cp1 = (char *)fp1;
fpnew->nx = fp1;
if ((char *)&(fpnew->nx) + fpnew->sz == cp1) {
/* upper chunk adjacent, assimilate it */
fpnew->sz += fp1->sz + sizeof(size_t);
fpnew->nx = fp1->nx;
}
if (fp2 == NULL) {
/* new head of freelist */
__flp = fpnew;
irq_restore(state);
return;
}
break;
}
/*
* Note that we get here either if we hit the "break" above,
* or if we fell off the end of the loop. The latter means
* we've got a new topmost chunk. Either way, try aggregating
* with the lower chunk if possible.
*/
fp2->nx = fpnew;
cp2 = (char *)&(fp2->nx);
if (cp2 + fp2->sz == cpnew) {
/* lower junk adjacent, merge */
fp2->sz += fpnew->sz + sizeof(size_t);
fp2->nx = fpnew->nx;
}
/*
* If there's a new topmost chunk, lower __brkval instead.
*/
for (fp1 = __flp, fp2 = 0;
fp1->nx != NULL;
fp2 = fp1, fp1 = fp1->nx)
/* advance to entry just before end of list */;
cp2 = (char *)&(fp1->nx);
if (cp2 + fp1->sz == __brkval) {
if (fp2 == NULL) {
/* Freelist is empty now. */
__flp = NULL;
}
else {
fp2->nx = NULL;
}
__brkval = cp2 - sizeof(size_t);
}
irq_restore(state);
}
#include <string.h>
void *
realloc(void *ptr, size_t len)
{
struct __freelist *fp1, *fp2, *fp3, *ofp3;
char *cp, *cp1;
void *memp;
size_t s, incr;
unsigned state;
/* Trivial case, required by C standard. */
if (ptr == NULL) {
return malloc(len);
}
state = irq_disable();
cp1 = (char *)ptr;
cp1 -= sizeof(size_t);
fp1 = (struct __freelist *)cp1;
cp = (char *)ptr + len; /* new next pointer */
if (cp < cp1) {
/* Pointer wrapped across top of RAM, fail. */
irq_restore(state);
return 0;
}
/*
* See whether we are growing or shrinking. When shrinking,
* we split off a chunk for the released portion, and call
* free() on it. Therefore, we can only shrink if the new
* size is at least sizeof(struct __freelist) smaller than the
* previous size.
*/
if (len <= fp1->sz) {
/* The first test catches a possible unsigned int
* rollover condition. */
if (fp1->sz <= sizeof(struct __freelist) ||
len > fp1->sz - sizeof(struct __freelist)) {
irq_restore(state);
return ptr;
}
fp2 = (struct __freelist *)cp;
fp2->sz = fp1->sz - len - sizeof(size_t);
fp1->sz = len;
free(&(fp2->nx));
irq_restore(state);
return ptr;
}
/*
* If we get here, we are growing. First, see whether there
* is space in the free list on top of our current chunk.
*/
incr = len - fp1->sz;
cp = (char *)ptr + fp1->sz;
fp2 = (struct __freelist *)cp;
for (s = 0, ofp3 = 0, fp3 = __flp;
fp3;
ofp3 = fp3, fp3 = fp3->nx) {
if (fp3 == fp2 && fp3->sz + sizeof(size_t) >= incr) {
/* found something that fits */
if (fp3->sz + sizeof(size_t) - incr > sizeof(struct __freelist)) {
/* split off a new freelist entry */
cp = (char *)ptr + len;
fp2 = (struct __freelist *)cp;
fp2->nx = fp3->nx;
fp2->sz = fp3->sz - incr;
fp1->sz = len;
}
else {
/* it just fits, so use it entirely */
fp1->sz += fp3->sz + sizeof(size_t);
fp2 = fp3->nx;
}
if (ofp3) {
ofp3->nx = fp2;
}
else {
__flp = fp2;
}
irq_restore(state);
return ptr;
}
/*
* Find the largest chunk on the freelist while
* walking it.
*/
if (fp3->sz > s) {
s = fp3->sz;
}
}
/*
* If we are the topmost chunk in memory, and there was no
* large enough chunk on the freelist that could be re-used
* (by a call to malloc() below), quickly extend the
* allocation area if possible, without need to copy the old
* data.
*/
if (__brkval == (char *)ptr + fp1->sz && len > s) {
cp1 = __malloc_heap_end;
cp = (char *)ptr + len;
if (cp1 == NULL) {
char *stack_pointer;
asmv("mov r1, %0" : "=r"(stack_pointer));
cp1 = stack_pointer - __malloc_margin;
}
if (cp < cp1) {
__brkval = cp;
fp1->sz = len;
irq_restore(state);
return ptr;
}
/* If that failed, we are out of luck. */
irq_restore(state);
return 0;
}
/*
* Call malloc() for a new chunk, then copy over the data, and
* release the old region.
*/
if ((memp = malloc(len)) == NULL) {
irq_restore(state);
return 0;
}
memcpy(memp, ptr, fp1->sz);
free(ptr);
irq_restore(state);
return memp;
}
void *
calloc(size_t nele, size_t size)
{
void *p;
if ((p = malloc(nele * size)) == NULL) {
return 0;
}
memset(p, 0, nele * size);
return p;
}
void heap_stats(void)
{
if (__brkval == NULL) {
__brkval = __malloc_heap_start;
}
long int heap_size = __malloc_heap_end - __malloc_heap_start;
long int free = __malloc_heap_end - __brkval;
struct __freelist *fp;
for (fp = __flp; fp; fp = fp->nx) {
free += fp->sz;
}
printf("heap: %ld (used %ld, free %ld) [bytes]\n",
heap_size, heap_size - free, free);
}
#else
void heap_stats(void) {
puts("heap statistics are not supported");
}
#endif /* MODULE_MSP430_MALLOC */

55
cpu/msp430_common/msp430-main.c
View File

@ -104,59 +104,16 @@ init_ports(void)
P2IE = 0;
}
/*---------------------------------------------------------------------------*/
/* msp430-ld may align _end incorrectly. Workaround in cpu_init. */
extern int _end; /* Not in sys/unistd.h */
char *cur_break = (char *) &_end;
void msp430_cpu_init(void)
{
irq_disable();
init_ports();
irq_enable();
periph_init();
if ((uintptr_t)cur_break & 1) { /* Workaround for msp430-ld bug!*/
cur_break++;
}
}
/*---------------------------------------------------------------------------*/
#define asmv(arg) __asm__ __volatile__(arg)
#define STACK_EXTRA 32
extern char __stack; /* provided by linker script */
char *__heap_end = NULL; /* top of heap */
/*
* Allocate memory from the heap. Check that we don't collide with the
* stack right now (some other routine might later). A watchdog might
* be used to check if cur_break and the stack pointer meet during
* runtime.
*/
void *sbrk(int incr)
{
char *__heap_top = __heap_end;
if (!__heap_top) {
/* set __heap_top to stack pointer if we are not in thread mode */
asmv("mov r1, %0" : "=r"(__heap_top));
__heap_top -= STACK_EXTRA;
}
if (incr > (__heap_top - cur_break)) {
return (void *) - 1; /* ENOMEM */
}
void *old_break = cur_break;
cur_break += incr;
/*
* If the stack was never here then [old_break .. cur_break] should
* be filled with zeros.
*/
return old_break;
}
/*---------------------------------------------------------------------------*/
/*
* Mask all interrupts that can be masked.
@ -183,17 +140,5 @@ splx_(int sr)
asmv("bis %0, r2" : : "r"(sr));
asmv("nop");
}
/*---------------------------------------------------------------------------*/
size_t strnlen(const char *s, size_t maxlen)
{
size_t len;
for (len = 0; len < maxlen; len++, s++) {
if (!*s)
break;
}
return (len);
}
extern void board_init(void);

31
cpu/msp430_common/startup.c
View File

@ -20,32 +20,31 @@
*/
#include <stdio.h>
#include "periph_conf.h"
#include "periph/init.h"
#include "kernel_init.h"
#include "stdio_base.h"
#include "irq.h"
#include "log.h"
extern void board_init(void);
/**
* Leave some extra space in the stack to allows us to finish the kernel
* initialization procedure. __heap_end is set the current stack, minus
* STACK_EXTRA since there is still code to execute.
*/
#define STACK_EXTRA 32
__attribute__((constructor)) static void startup(void)
{
/* use putchar so the linker links it in: */
putchar('\n');
board_init();
LOG_INFO("RIOT MSP430 hardware initialization complete.\n");
/* save current stack pointer as top of heap before enter the thread mode */
extern char *__heap_end;
__asm__ __volatile__("mov r1, %0" : "=r"(__heap_end));
__heap_end -= STACK_EXTRA;
#ifdef MODULE_NEWLIB
void _init(void);
_init();
#endif
/* initialize stdio prior to periph_init() to allow use of DEBUG() there */
stdio_init();
/* trigger static peripheral initialization */
periph_init();
/* continue with kernel initialization */
kernel_init();
__builtin_unreachable();
}

17
cpu/msp430_common/vendor/README.md vendored Normal file
View File

@ -0,0 +1,17 @@
# Introduction
The folder "msp430-gcc-support-files" has been imported from this URL:
# Source
https://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/latest/exports/msp430-gcc-support-files-${VERSION}.zip
Check msp430-gcc-support-files/Revisions_Header.txt for the actual version.
# How to update
The script `update.sh` can be used to update to the newest version.
The steps would be:
1. figure out newest version, update URL in `update.sh`
2. run update.sh
3. create a commit with the changes, PR that

700
cpu/msp430_common/vendor/msp430-gcc-support-files/Revisions_Header.txt vendored Normal file
View File

@ -0,0 +1,700 @@
Build 1.210 (GCC)
=================
05/14/2020
New device support:
------------------
- None
New features / changes:
-----------------------
- Adjusted high-memory boundaries in default linker command files to fix CPU47
- Changed lower (<0x10000) memory name from 'ROM' to 'FRAM' in applicable linker
command files
- Removed redundant TLV #defines from header files
Bug fixes:
----------
- Removed invalid IO ports from several MSP430FRxx devices
- Added missing HSPLL #defines for MSP430FR6043 family
- Fixed FR2XX/4XX family include guard in legacy.h
Build 1.209 (GCC)
=================
02/03/2020
New device support:
------------------
- MSP430FR2673, MSP430FR2672
- MSP430FR6005, MSP430FR6007
New features / changes:
-----------------------
- None
Bug fixes:
----------
- None
Build 1.208 (GCC)
=================
08/29/2019
New device support:
------------------
- None
New features / changes:
-----------------------
- Added support for blinking LED example
Bug fixes:
----------
- Fixed GNU compiler build options
- Added missing ALIGN directives for .preinit/init/fini_array sections in GCC
linker command files
Build 1.207 (GCC)
=================
02/14/2019
New device support:
------------------
- MSP430FR2676, MSP430FR2675, MSP430FR2476, MSP430FR2475
New features / changes:
-----------------------
- Updated definition of "__no_init" in in430.h
Bug fixes:
----------
- Corrected usage of NOPs in enable/disable interrupt macros in in430.h
- Removed invalid byte-access #defines (*_L/*_H) for DMA registers which only
allow word access from applicable device header files
Build 1.206 (GCC)
=================
07/26/2018
New device support:
------------------
- None
New features / changes:
-----------------------
- None
Bug fixes:
----------
- Added missing CPU errata compiler switches for MSP430FR2522, FR2512, FR2422
- Removed invalid SYSRSTIV_FLLUL #define from MSP430F5/F6 device header files
Build 1.205 (GCC)
=================
04/23/2018
New device support:
------------------
- MSP430FR2355, MSP430FR2353, MSP430FR2155, MSP430FR2153
New features / changes:
-----------------------
- None
Bug fixes:
----------
- Fixed another issue with .tinyram sections
Build 1.204 (GCC)
=================
12/21/2017
New device support:
------------------
- MSP430FR6043, MSP430FR6041, MSP430FR5043, MSP430FR5041,
MSP430FR60431, MSP430FR50431
New features / changes:
-----------------------
- Separated release notes by toolchain (CCS, IAR, GCC)
- Added build version number to device XML and GNU compiler options file
- Minor update in legacy.h
Bug fixes:
----------
- Added missing .tinyram assignments in applicable linker command files
Build 1.203
===========
10/05/2017
New device support:
------------------
- MSP430FR2522, MSP430FR2512, MSP430FR2422
New features / changes:
-----------------------
- Added -minrt option for GCC builds on devices with .5K of MAIN memory
Bug fixes:
----------
- Fixed name conflict in GCC linker files for FR2xx devices (INFO vs. INFOMEM)
Build 1.201
===========
06/28/2017
New device support:
------------------
- MSP430FR2100, MSP430FR2000
New features / changes:
-----------------------
- Enabled MPU by default for FR57xx family devices
- Moved toolchain specific CCS device XML files to separate folder (targetdb/options)
- Changed GCC linker files to place .persistent section into lower FRAM
- Changed GCC linker files to properly split rodata, data, bss and text sections for
devices with large memory
- Added a workaround to enable GCC project builds for FR6047 family in CCS
Bug fixes:
----------
- Fixed offset definitions for port registers in header files for newer devices
- Fixed linker options in *_TI CCS device XML files using -D instead of --define
- Fixed CCS linker files using __LARGE_DATA_MODEL__ instead of __LARGE_CODE_MODEL__
- Fixed inconsistencies in IAR SFR files for newer devices
Build 1.200
===========
05/31/2017
New device support:
------------------
- MSP430FR6047, MSP430FR60471, MSP4306045, MSP430FR6037, MSP430FR60371, MSP430FR6035
New features / changes:
-----------------------
- Moved toolchain specific data from CCS device XMLs to separate _TI/_GNU XMLs
- Added list of memory boundary defines to header files for newer devices
- Changed CCS device XMLs to activate MPU by default for applicable devices
Bug fixes:
----------
- Removed invalid linker- and IDE integration files for "generic" devices
- Fixed RAM boundaries for MSP430F67641 and MSP430F67641A
- As of last support files release 7.2.4: Fixed wrong -mmcu flags in GCC specific device
XML files
Known Limitations:
------------------
- MPU is not enabled by default on FR57xx family devices
==========================================================================================
Build 1.199 - 27.02.2017
==========================================================================================
15.02.2017 Several updates in legacy.h
10.02.2017 Minor change for calculated interrupt vector definitions in IAR header files
07.02.2017 Added --near_data=none option for devices with RAM in memory > 0x10000
06.02.2017 Fixed WDT base address and WDTCTL offset for FR4xx/FR2xx family devices
02.02.2017 Fixed an issue with INFO memory of FRAM devices being initialized on reset
02.02.2017 Fixed RAM boundaries for FR596x devices
02.02.2017 Changed I/O offset definitions to be relative to PORTx base for newer devices
13.12.2016 Enabled --gc-section compiler option for GCC builds
08.12.2016 Added mirrored RAM ranges to IAR menu files for applicable devices
==========================================================================================
Build 1.198 - 22.11.2016
==========================================================================================
18.11.2016 Added missing ADCRES control bits for FR4xx/FR2xx devices
04.10.2016 Fixed offset definitions for certain registers in modules DIO and RTC
04.10.2016 Removed duplicate and invalid defines in header files for newer devices
04.10.2016 Fixed comment format in all header files for newer devices
26.09.2016 Moved CPU architecture define in header to account for in430.h dependencies
==========================================================================================
Build 1.194 - 27.09.2016
==========================================================================================
26.09.2016 Updated in430.h for GCC and changed include order in GCC headers accordingly
==========================================================================================
release Package 19.09.2016
==========================================================================================
06.09.2016 Removed invalid INFOMEM definitions in GCC linker files for fr2xx devices
06.09.2016 Updated legacy.h with old LEA_SC definitions
06.09.2016 Renamed LEA_SC module to LEA (including all registers and other definitions)
==========================================================================================
release Package 10.06.2016
==========================================================================================
10.06.2016 Fixed typo in TI_COMPILER_VERSION check in CCS linker command files
01.06.2016 Corrected TLV address offsets in header files for G2xx/F2xx devices
==========================================================================================
release Package 20.05.2016
==========================================================================================
19.05.2016 Added SIGNATURE sections in GCC linker command files
19.05.2016 Removed invalid code from generic GCC symbol files
18.05.2016 Added silicon errata switches to GCC compiler options in CCS device XMLs
02.05.2016 Added missing register separator comments in header files for newer MSP430s
28.04.2016 Changed format of multi-JSTATE bit modules in IAR menu files
12.04.2016 Added missing alternate register definitions (RTCCNT) for devices with RTC_C
==========================================================================================
release Package 11.04.2016
==========================================================================================
11.04.2016 Added missing register definition macros to iomacros.h for GCC
08.04.2016 Added missing __MSP430_HAS_P*SEL__ definitions in F1xx/F2xx/F4xx headers
08.04.2016 Fixed typo in GCC linker files
05.04.2016 Fixed debug_line option in GCC linker files for smaller memory devices
==========================================================================================
release Package 31.03.2016
==========================================================================================
31.03.2016 Fixed register definitions in GCC header files for FR5994 and FR2311 family
31.03.2016 Removed invalid header and support files for FR5994 family devices
==========================================================================================
release Package 30.03.2016
==========================================================================================
30.03.2016 Changed 16bit access definitions for 32bit registers in GCC headers
29.03.2016 Enhanced DEFWL macro in IAR header files
29.03.2016 Corrected family definition for several FR2xx devices
29.03.2016 Removed unnecessary memory allocation in GCC linker files
29.03.2016 Added legacy definitions for FR413x BKMEM module
==========================================================================================
release Package 24.03.2016
==========================================================================================
24.03.2016 Added ADC10PDIV_3 definition to resolve backwards compatibility issues
==========================================================================================
release Package 02.03.2016
==========================================================================================
02.03.2016 Updated compiler workaround switches in CCS xml files
==========================================================================================
release Package 03.02.2016
==========================================================================================
27.01.2016 Added: MSP430FR5994, MSP430FR5992, MSP430FR5964, MSP430FR5962, MSP430FR5894,
MSP430FR5892, MSP430FR5864, MSP430FR5862
Added: MSP430FR2311, MSP430FR2310
==========================================================================================
release Package 22.12.2015
==========================================================================================
21.12.2015 Revised TAG_ADC10_1 values for applicable devices
16.12.2015 Added upper bss section in GCC linker files
15.12.2015 Removed invalid LCD definitions in CC430F514x header and support files
02.12.2015 Removed invalid ADC10PDIV_3 definitions for MSP430F5247 and related devices
02.12.2015 Added CAPTIVATE registers
16.11.2015 Added mhwmult option in the GNU Compiler option with the CCS device.xml files
09.11.2015 Fixed AESOP_2 and AESOP_3 comments mismatch and typo
09.11.2015 Added new GCC linker symbols files
09.11.2015 Added missing GCC linker option in CCS xml files
04.11.2015 CCS linker file memory regions split
==========================================================================================
release Package 29.10.2015
==========================================================================================
28.10.2015 Added GCC linker heap memory support
==========================================================================================
release Package 27.10.2015
==========================================================================================
20.10.2015 Updated CCS cmd file for IPE signature
14.10.2015 CCS linker file: fixed mapping of manual IPE configuration to right memory range
13.10.2015 updated a comment in the GCC linker file (.noinit)
13.10.2015 Restructured memory segment output for GCC linker files
13.10.2015 Added: MSP430FR2532, MSP430FR2533, MSP430FR2632, MSP430FR2633
06.10.2015 Added INFO memory tag in IAR menu files
28.09.2015 Added BSL memory tag in IAR menu files
24.09.2015 Fixed mirrored RAM section for F6659
15.09.2015 Changed IAR linker files to support MPU + IPE enabled together
15.09.2015 Corrected RAM memory range in lnk430f5359.xcl
14.09.2015 Removed 0x400 offset for IPEEND
14.09.2015 Add a .ipe_const section for constants in the IPE area in CCS linker files
14.09.2015 Added new IAR menu file features requested by IAR
14.09.2015 Added ram func feature for CCS
==========================================================================================
release Package 10.08.2015
==========================================================================================
29.07.2015 Updated comments for USCI IV Bit definitions
==========================================================================================
release Package 17.07.2015
==========================================================================================
17.07.2015 Fixed issue with BSL signature overlapping with interrupt vectors
16.07.2015 Fixed DMA issue in msp430frxx_6xxgeneric.h
14.07.2015 Add new definitions for Driverlib to differentiate SYSCFG2 bits
09.07.2015 F673xA: added missing 3rd SD24 Channel definition
29.06.2015 FR59xx and FR69xx: removed not available defines for SYSSNIV_SVS and SYSSNIV_ACCTEIFG
09.06.2015 F677x: fixed wrong define DMAxTSEL__USCIB3TX to DMAxTSEL__USCIA3TX
16.04.2015 added: RF430F5175 RF430F5155 RF430F5144
added: MSP430FR5922 MSP430FR59221
02.04.2015 Updated Segment size and calculation for FR57xx devices
==========================================================================================
release Package 25.03.2015
==========================================================================================
13.03.2015 updated IAR xcl file format
18.02.2015 added Port 7 for MSP430F5239
==========================================================================================
release Package 04.02.2015
==========================================================================================
31.07.2014 LCD_B and LCD_C: added missing LCDBLKPRE_x and LCDDIV_x definitions
25.07.2014 G2xx1,G2xx2,G2xx3: added dummy TRAPINT_VECTOR interrupt vector as bugfix for USCI29
16.07.2014 FR5xx/FR6xx: added define SYSRSTIV_ACCTEIFG
04.07.2014 ESI: Renamed bit ESIVCC2 to ESIVMIDEN, renamed bit ESIVSS to ESISHTSM
==========================================================================================
release Package 29.06.2014
==========================================================================================
25.06.2014 Updated MPU inplementation into CCS Linker Command files
==========================================================================================
release Package 29.04.2014
==========================================================================================
==========================================================================================
release Package 21.01.2014
==========================================================================================
20.01.2014 Added Version Tag to Linker command files (identical to header files)
updated Signature defintion for CCS in linker command files
replaced MirrowRAMEnd with MirrowedRAMEnd
added MSP430F677xA devices
21.11.2013 MSP430F665x: Added USCI_A2 and USCI_B2 to DMA Trigger Table
20.11.2013 CCS: updated path for mathlib (4xx/5xx version)
11.11.2013 MSP430i20xx: fixed TAxIV_TAIFG definition
31.10.2013 MSP430G25xx: updated tags for TLV data
24.07.2013 MSP430FR59xx: Replaced NACCESSx with NWAITSx
23.07.2013 Module LDOPWR: fixed wrong define of LDOEN (from LDOOEN)
==========================================================================================
release Package 18.07.2013
==========================================================================================
18.07.2013 CCS: added code template support
11.07.2013 removed not available PxDS Register definitions
==========================================================================================
release Package 09.07.2013
==========================================================================================
09.07.2013 fixed identifier for debugger for MSP430i devices
added base address define for MSP430i devices
==========================================================================================
release Package 28.06.2013
==========================================================================================
28.06.2013 added P7 to MSP430F5237
10.06.2013 updated CCS linker command file for devices with MPU
10.06.2013 added MSP430I20xx and MSP430F525x devices
10.05.2013 MSP430F51x2 Fixed Typo PM_UCB0SOMO -> PM_UCB0SOMI
==========================================================================================
release Package 08.05.2013
==========================================================================================
25.04.2013 fixed RAM size for MSP430G2102 and MSP430G2132
==========================================================================================
release Package 19.03.2013
==========================================================================================
15.03.2013 added RTCAE bits to RTC Module
11.03.2013 added DCOR to MSP430G2x55 devices
added 5xx style defintions for 2xx/4xx devices for TA0IV Register
fixed some typos in 5xx/6xx device with TimerA/B Interrupt vector definitions
10.02.2013 fixed size of Signature in FRAM Devices
==========================================================================================
release Package 31.01.2013
==========================================================================================
31.01.2013 added MSP430G2755, MSP430G2855, MSP430G2955
15.01.2013 changed defines to CapTouchIO from CapSenseIO to align with Users Guide
13.12.2012 Module name changed from RTC_CE to RTC_C
13.12.2012 CCS: Removed Legacy CCE V2 defines for Interrupt Vectors
14.11.2012 fixed missing UCA1 in FR57x3/7
14.11.2012 FR56xx: fixed typo in SYSRSTIV_MPUSEG defintions
replaced COMP_B with COMP_E
==========================================================================================
release Package 13.11.2012
==========================================================================================
24.10.2012 replaced define TBSSEL__TACLK with TBSSEL__TBCLK
ADC12B: fixed some Typos in ADC12 definitions (ADC10 was used before)
28.09.2012 USB devices: removed UPCS0 definition
==========================================================================================
release Package 25.09.2012
==========================================================================================
25.09.2012 F677x: added Comp B to Interrupt Vector Table
21.09.2012 CCS: fixed issue with Board files under Linux
18.09.2012 added Signature Memory Segments to linker command file
12.09.2012 CCS: added USB RAM segment to linker command file
16.08.2012 added MSP430F6x5x and MSP430F5x5x devices
added MSP430F677x devices
17.07.2012 Updated PxSELC register address to offset 0x16 (instead of 0x10)
MSP430FR58xx/MSP430FR59xx replaced Comperator B with Comperator E
28.06.2012 Added TimerD Cal Tag for TLV Table (Devices with TimerD only)
13.06.2012 Fixed definitions for LCD: VLCD_13, VLCD_14, VLCD_3_26, VLCD_3_32
13.06.2012 F67xx: Removed not available Bits SD24BINCHx
==========================================================================================
release Package 12.06.2012
==========================================================================================
31.05.2012 added MSP430SL5438A
31.05.2012 CC430: removed not available Definitions: RF1AIFIV_RFRXIFG and RF1AIFIV_TFRXIFG
29.05.2012 FR596x devices
03.05.2012 MSP430FR57xx: removed not available PxDS Registers
==========================================================================================
release Package 30.03.2012
==========================================================================================
30.03.2012 MSP430F53xx, MSP430F52xx and MSP430F67xx: removed RCRS7OFF
29.03.2012 MSP430F66xx: Added for defines for SYSSNIV_SVMLVLRIFG and SYSSNIV_SVMHVLRIFG
==========================================================================================
release Package 19.03.2012
==========================================================================================
13.03.2012 added MSP430FR5969
22.02.2012 CCS: removed --advice:power=all and --advice:power_severity=remark from XML file
changed default output format from coff to elf
added addtional data segments to linker command file
17.02.2012 Fixed UCBxSTAT display size in Debugger
15.02.2012 CCS: Moved Modules to msp430 sub folder
08.02.2012 CCS: updated MPU section:__mpusam = 0x7513;
updated MPU section:__mpuseg incremented by one if MemSize = x.5;
18.01.2012 CCS: added .data Section (required for SYSBIOS)
18.01.2012 CCS: changed pathes to use / instead of \ within XML files
CCS: package with unix style linefeeds added
13.01.2012 ADC12B removed ADC12DIF for odd Registers
added defines for TimerA Interrrupt vectors to Timer0_A
11.01.2012 Updated Comment for UC7BIT
Fixed Typo for MC__CONTINOUS (legacy definition for old define added)
==========================================================================================
release Package 14.12.2011
==========================================================================================
13.12.2011 Updated all FR57xx device to have 1k RAM
28.11.2011 Fixed the G2230 and G2210 Menu file, leading to the device being reported as incorrect.
28.11.2011 Changed format of Interrupt Table in CCS V5 for ULP Advisor check
added Tag to CCS V5 XML files to enalbe ULP Advisor
removed -o0 option in CCS V4
02.11.2011 updated FRAM error flag names for FR57xx
removed MPULOCK bit
20.10.2011 added More memory information (RAM2/ USB RAM / Mirrowed RAM)
14.10.2011 added TLV do MSP430XGenergic
==========================================================================================
release Package 01.10.2011
==========================================================================================
29.09.2011 fixed Typo in comment of TASSEL0/1
==========================================================================================
release Package 30.09.2011
==========================================================================================
29.09.2011 added G2230 and the G2210
==========================================================================================
15.09.2011 CCS: added Board Files
15.09.2011 IAR: added Tag if INFOA can be locked
==========================================================================================
release Package 10.08.2011
==========================================================================================
03.08.2011 CCS: changed Stack and BSS location for FRAM devices to RAM
02.08.2011 added Devices: F522x, F643x. F533x, FR57xx; F67xx, CC430F614x, CC430F51xx
02.08.2011 added Devices: GenericX Device
03.08.2011 Fixed definition of RTCTEV__0000 and RTCTEV__1200
==========================================================================================
release Package 24.06.2011
==========================================================================================
09.06.2011 F663x: fixed wrong definitions in DMA Trigger 7 and 8
==========================================================================================
release Package 09.06.2011
==========================================================================================
09.06.2011 CPU BUG30 added for IAR
fixed comment of Peripheral section in IAR XCL files (5xx devices only)
added bit defintions for PAIN, PBIN,.. in XML and sfr files
25.05.2011 F663x and FR573: Fixed definition of RTCTEV__0000 and RTCTEV__1200
Removed not availabe bits RTCMODE and RTCSSELx
12.05.2011 Fixed SD24 Tag for AFE253 (3 SD) devices
19.04.2011 Added base address of 5xx modules
added PxSELC registers for FRAM devices
07.04.2011 Fixed typo LCD_C (VLCD) definitions
29.03.2011 Fixed Memory (RAM) for Fg477 and F477
16.03.2011 Fixed typo in comment of AFE devices
Removed SD24CONF0 in AFE devices
Removed caldata for 1MHZ and 16MHZ in AFE devices
==========================================================================================
release Package 08.03.2011
==========================================================================================
07.03.2011 Set some FR57xx devices and all AFE device to released
07.03.2011 Updated FR57xx devices
04.03.2011 Added P3SEL for G2x53
28.02.2011 IAR: added LPM5 Tag
09.12.2010 F530x: added PU (USB LDO)
08.12.2010 CCS: SD16: removed wrong entries in SD16 xml file
06.12.2010 USB: added alternate define USBIV - USBVECINT
16.11.2010 F51x2: Fixed PortMapper Definitons
==========================================================================================
release Package 11.11.2010
==========================================================================================
11.11.2010 Removed Port4 in CC430F51xx devices
09.11.2010 Added Devices to release package: Kryton, AFE253, F532x, F532x, F534x, BT5xxx
updated PortU and USB defintions according to UG
changed access type to Timer A/B/D to word only
15.10.2010 Added FW428/FW429
15.10.2010 A-Pool: added LCMP : A-POOL Latch comparator
==========================================================================================
release Package 23.09.2010
==========================================================================================
14.09.2010 Fixed ADC12 (2xx/4xx) sfr file for ADC12MCTL
Removed DCOR bit in 5xx devices according UG
==========================================================================================
release Package 09.08.2010
==========================================================================================
==========================================================================================
release Package 06.08.2010
==========================================================================================
03.08.2010 Replaced PSSKEY with PMMKEY on some older 5xx devices
removed archiving of old Modules
added Device Prefix for Modules on non-released devices
==========================================================================================
release Package 28.07.2010
==========================================================================================
27.07.2010 CCS-XML: added FilterString
26.07.2010 removed P7/P8/PA from F24x
26.07.2010 removed USCI 2/3 from 5418/5435/5437
released device for Aug 2010 update
10.07.2010 set L092 to normal CPU instead of CPUX
05.07.2010 F471x3 Fixed Definition SD16MEMx, SD16IV
05.07.2010 F5xx: added missing & for ADC12MEM
05.07.2010 F663x removed EDI
==========================================================================================
release Package 17.06.2010
==========================================================================================
16.06.2010 CCS: removed for inbetween release: Family Tag to XML files
11.06.2010 added support for GCC
10.06.2010 Updated some OSCCAP settings for the F47xx devices
09.06.2010 CCS: added Family Tag to XML files
07.06.2010 Updated F47126/F47127 source files (fixed missing DMA and RTC)
==========================================================================================
release Package 27.05.2010
==========================================================================================
17.05.2010 CCS: added support Large/Small Memory Model in CCS cmd files
17.05.2010 added support for F438/F438 spins
==========================================================================================
release Package 17.05.2010
==========================================================================================
17.05.2010 Removed L092EMU device
04.05.2010 released L092 devices
27.04.2010 added missing CG461x devices
15.03.2010 FE42x2: Fixed swapped IRMS and IRMS_2 definitions
==========================================================================================
release Package 16.03.2010
==========================================================================================
15.03.2010 changed FETSTRING for F20x1 and F20x2 due to Argon Devices
added F6638 and F5510 to release package
updated EEM info for 5xx
09.03.2010 updated EEM info for many devices (F5xx with 3 BKPT , F4719x)
08.03.2010 IAR: replaced <In430.h> with "in430.h" as requested by A.Dannenberg /SDO
05.03.2010 5xx: Changed access type of DMAxSZ registers to word only
26.02.2010 removed XT2 from F5172 (int)
26.02.2010 updated PM on F5510 (int)
16.02.2010 updated comment in F41x2
09.02.2010 CCS: replaced <In430.h> with "in430.h" as requested by A.Dannenberg /SDO
==========================================================================================
release Package 25.01.2010 (new update and with label applied)
==========================================================================================
25.01.2010 released F51x2
25.01.2010 CCS: fixed bug in generation of XML files
==========================================================================================
release Package 16.12.2009 (new update and with label applied)
==========================================================================================
16.12.2009 updated defintions for KEY and PW (Password) as requested by system
PW register will cause PUC on wrong access / Key just ignores
08.12.2009 CCS: added support of ENUM generation in XML files
08.12.2009 Fixed typo in ADC10: SREF3 -> SREF2
02.12.2009 CCS: fixed definitin of RESET_VECTOR for ASM
01.12.2009 added u-type castings for #defines into IAR header file
01.12.2009 some comment cleanup in ADC12/ADC10 done
26.11.2009 fixed typo WDTSSEL__SCMLK -> WDTSSEL__SMCLK
20.11.2009 Removed support for old TI ASM
16.11.2009 CC430: removed XT2DRIVE_x definitions
==========================================================================================
release Package 11.11.2009 (new update and with label applied)
==========================================================================================
10.11.2009 activated description field for CCS
==========================================================================================
release Package 10.11.2009 (new update and with label applied)
==========================================================================================
10.11.2009 F23x0: added dummy TRAPINT_VECTOR interrupt vector as bugfix for USCI29
10.11.2009 implemented description field for CCS
10.11.2009 fixed type enalbe in several modules
==========================================================================================
release Package 04.11.2009 (new update and with label applied)
==========================================================================================
05.11.2009 changed grouping of Port Mapping
04.11.2009 updated TAG_ADC12_1 and TAG_ADC10_1 to 0x08
03.11.2009 Fixed error in Port Mapping
29.10.2009 Added several new device spins
26.10.2009 MSP430FE42x2: Fixed swapped IRMS_2 definitions
30.09.2009 L092/C092: set CPU type to CPUX (pre request from Team)
29.09.2009 PMM: updated LOCKBAK to LOCKIO as shown in the UG LOCKBAK is used by RTC, added LOCKLPM5
27.08.2009 IAR: added CPU Tag for menu files (BTT556)
24.08.2009 CCS: fixed error in ASM int generation for numbers below 10
19.08.2009 fixed wrong Ram size for F5527 -> 0x3BFF
19.08.2009 removed Port D on F55xx devcie with 64 pin package
12.08.2009 added 51x1 to internal devices
==========================================================================================
release Package 20.07.2009
==========================================================================================
10.08.2009 updated RAM sizes of CC430F6137/CC430F5137
07.08.2009 updated header of CCS cmd files according to Andreas D. recommendations
05.08.2009 F55xx fixed type in DMA Trigger Defs
04.08.2009 implemented generation of dedicated header files
16.06.2009 implemented splitt of USCI modules
06.06.2009 made TAxIV and TBxIV registers for 5xx devices writeable
removed SYSARB register in 5xx SYS module
==========================================================================================
release Package 03.06.2009 / 07.06.2009
==========================================================================================
03.06.2009 added CHECKSUM to IAR xcl files
23.06.2009 F5xx: xml files: USCI - I2C added missing bits
23.06.2009 F5xx: sfr files: MPY - added missing bits for MPYCTL and SUMEXT
05.05.2009 F5xx: Flash - removed some bits according to UG (EEI / EEIEX)
05.05.2009 CC430 devices: changed RTC_A_VECTOR to RTC_VECTOR
05.05.2009 CCS4: implemented ISR definition for ASM header files
05.05.2009 CCS4: split of CMD files implemented
04.05.2009 updated USB related header files
04.05.2009 updated MSP430.h files + special file for IAR
04.05.2009 IAR: replaced __IAR_SYSTEMS_ICC with __IAR_SYSTEMS_ICC__
17.04.2009 IAR: replace 20 Bit register access with short access (only allowed in small memory model)
16.04.2009 Updated Comments for Comp.B (Ref Resitor divider and COMP_B_ISR Vector)
Removed XT1OFIFG from F552x and F551x
14.04.2009 added Target VCC to menu and xml files
==========================================================================================
release Package 25.03.2009
==========================================================================================
23.03.2009 fixed error in Imagecraft files for 5xx devices
23.03.2009 replaced label for RSTWU/PORTWU to LPM5WU
23.03.2009 F41x2 removed LFXT1DIG
23.03.2009 Added TLV and DMA definitions for 5xx devices
16.03.2009 fixed wrong LCDMEM usage
26.02.2009 updated MSP430L092
24.02.2009 removed SD16CONFx registers from SFR files
==========================================================================================
release Package 11.02.2009
==========================================================================================
11.02.2009 released CC430 devices
09.02.2009 removed some XT2 bits from F41x2,
added comment to new release files F41x2, F471x6, F471x7, F47x, FG47x
04.02.2009 released F41x2
30.01.2009 released F471x6, F471x7, F47x, FG47x
29.01.2009 fixed error in LCDB
20.01.2009 added byte alarm Register definitions for RTC in 5xx family
20.01.2009 F41x2 replaced LCD with LCDA
15.01.2009 5xx LCD_B fixed wrong alignment in #define LCDDIV__1
18.12.2008 Added PMMLPM5xxx def to PMM
20.11.2008 Added <cyclecounter> and <iv_base> Tags
17.11.2008 Added msp430x241x.h
14.11.2008 Added RTxPS to F5xx devices
Added missing USCI registers F5xx devices
removed wrong byte definitions on *.cmd files (5xx)
06.11.2008 FE42x2 do not have HWMPY
05.11.2008 reduce RAM for CC430 by 2 to avoid bug with Stackpointer
30.10.2008 added additional FLL bits for F42x2
moved INTVEC legacy defs of TB0 to module
added LFXT1DIG to some devices
27.10.2008 changed name for TB to TB0 in F5xx/F6xx devices
23.10.2008 removed LCDB size bits
changed VLCDx bits from 8 to 9
changed CCE printf default to minimal
15.10.2008 added CCS 4.0 package
13.10.2008 updated RAM config for F552x/F551x
10.10.2008 change style for V2 style interrupts defintion in CCE
removed unused defintions in PMM
updated RF defintions for CC1101
04.09.2008 increased Stack/Heap size for large Ram Devices
03.09.2008 removed P10 from TC0701
added USBPLL definitions
26.08.2008 stopped support for IAR_V1 and CCE V1, CCE V2 (files now longer will be updated)
26.08.2008 fixed wrong bit in UCS UCSUNLOCKHIST1
added SD16XDIV2 to sfr files
25.08.2008 added Missing FCTL2 bits in sfr files. Updated FX47x files added Missing FCTL2 bits in sfr files. Updated FX47x files
20.08.2008 updated FG47x files with some OA bits updated FG47x files with some OA bits
19.08.2008 added F471x6 added F471x6
31.07.2008 updated FG47x and F47x with SD16BUF updated FG47x and F47x with SD16BUF

693
cpu/msp430_common/vendor/msp430-gcc-support-files/include/devices.csv vendored Normal file
View File

@ -0,0 +1,693 @@
# /* ============================================================================ */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
# /* Copyright (c) 2016, Texas Instruments Incorporated */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
# /* All rights reserved. */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
# /* */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
# /* Redistribution and use in source and binary forms, with or without */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
# /* modification, are permitted provided that the following conditions */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
# /* are met: */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
# /* */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
# /* * Redistributions of source code must retain the above copyright */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
# /* notice, this list of conditions and the following disclaimer. */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
# /* */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
# /* * Redistributions in binary form must reproduce the above copyright */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
# /* notice, this list of conditions and the following disclaimer in the */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
# /* documentation and/or other materials provided with the distribution. */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
# /* */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
# /* * Neither the name of Texas Instruments Incorporated nor the names of */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
# /* its contributors may be used to endorse or promote products derived */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
# /* from this software without specific prior written permission. */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
# /* */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
"# /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" */",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
# /* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
# /* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
# /* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
# /* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
# /* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
# /* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
# /* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
# /* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
# /* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
# /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
# /* ============================================================================ */,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Version:,1.21,,,,Date:,5/14/2020,14:14:02,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
# ============================================================================,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
# CPU,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
"# 0 STD MSP430 CPU",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
"# 1 MSP430X CPU",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
"# 2 MSP430XV2 CPU",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
#,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
#,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
# HWMPY,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
"# 0 No Hardware Multiplier",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
"# 1 16 Bit Hardware Multiplier",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
"# 2 16 Bit Hardware Multiplier with sign Extension (2xx Devices)",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
#,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
"# 4 32 Bit Hardware Multiplier",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
"# 8 32 Bit Hardware Multiplier (5xx)",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
#,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
#,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
# SPI2Wire,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
"# 0 JTAG only - no scan",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
"# 1 SBW (default) - scan allowed",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
"# 2 JTAG (Default) - scan allowed",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
"# 3 SBW only - no scan",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
# ============================================================================,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
# Device Name,CPU_TYPE,CPU_Bugs,MPY_TYPE,SBW,EEM,BREAKPOINTS,CLOCKCONTROL,CYCLECOUNTER,STACKSIZE,RAMStart,RAMEnd,RAMStart2,RAMEnd2,TINYRAMStart,TINYRAMEnd,USBRAMStart,USBRAMEnd,LEARAMStart,LEARAMEnd,MirrowedRAMSource,MirrowedRAMStart,MirrowedRAMEnd,BSLStart,BSLSize,BSLEnd,INFOStart,INFOSize,INFOEnd,INFOA,INFOB,INFOC,INFOD,FStart,FEnd,FStart2,FEnd2,Signature_Start,Signature_Size,INTStart,INTEnd
msp430c111,0,0,0,0,NONE,0,NONE,0,50,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,F800,FFDF,0,0,,,FFE0,FFFF
msp430c1111,0,0,0,0,NONE,0,NONE,0,50,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,F800,FFDF,0,0,,,FFE0,FFFF
msp430c112,0,0,0,0,NONE,0,NONE,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,F000,FFDF,0,0,,,FFE0,FFFF
msp430c1121,0,0,0,0,NONE,0,NONE,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,F000,FFDF,0,0,,,FFE0,FFFF
msp430c1331,0,0,0,0,NONE,0,NONE,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,E000,FFDF,0,0,,,FFE0,FFFF
msp430c1351,0,0,0,0,NONE,0,NONE,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,C000,FFDF,0,0,,,FFE0,FFFF
msp430c311s,0,0,0,0,NONE,0,NONE,0,50,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,F800,FFDF,0,0,,,FFE0,FFFF
msp430c312,0,0,0,0,NONE,0,NONE,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,F000,FFDF,0,0,,,FFE0,FFFF
msp430c313,0,0,0,0,NONE,0,NONE,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,E000,FFDF,0,0,,,FFE0,FFFF
msp430c314,0,0,0,0,NONE,0,NONE,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,D000,FFDF,0,0,,,FFE0,FFFF
msp430c315,0,0,0,0,NONE,0,NONE,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,C000,FFDF,0,0,,,FFE0,FFFF
msp430c323,0,0,0,0,NONE,0,NONE,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,E000,FFDF,0,0,,,FFE0,FFFF
msp430c325,0,0,0,0,NONE,0,NONE,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,C000,FFDF,0,0,,,FFE0,FFFF
msp430c336,0,0,1,0,NONE,0,NONE,0,80,200,05FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,A000,FFDF,0,0,,,FFE0,FFFF
msp430c337,0,0,1,0,NONE,0,NONE,0,80,200,05FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,8000,FFDF,0,0,,,FFE0,FFFF
msp430c412,0,0,0,0,NONE,0,NONE,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,F000,FFDF,0,0,,,FFE0,FFFF
msp430c413,0,0,0,0,NONE,0,NONE,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,E000,FFDF,0,0,,,FFE0,FFFF
msp430cg4616,1,CPU16; CPU19,1,0,NONE,0,NONE,0,80,1100,20FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,80,10FF,1080,1000,0,0,2100,FFBF,10000,18FFF,,,FFC0,FFFF
msp430cg4617,1,CPU16; CPU19,1,0,NONE,0,NONE,0,80,1100,30FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,80,10FF,1080,1000,0,0,3100,FFBF,10000,19FFF,,,FFC0,FFFF
msp430cg4618,1,CPU16; CPU19,1,0,NONE,0,NONE,0,80,1100,30FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,80,10FF,1080,1000,0,0,3100,FFBF,10000,1FFFF,,,FFC0,FFFF
msp430cg4619,1,CPU16; CPU19,1,0,NONE,0,NONE,0,80,1100,20FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,80,10FF,1080,1000,0,0,2100,FFBF,10000,1FFFF,,,FFC0,FFFF
msp430e112,0,0,0,0,NONE,0,NONE,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,F000,FFDF,0,0,,,FFE0,FFFF
msp430e313,0,0,0,0,NONE,0,NONE,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,E000,FFDF,0,0,,,FFE0,FFFF
msp430e315,0,0,0,0,NONE,0,NONE,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,C000,FFDF,0,0,,,FFE0,FFFF
msp430e325,0,0,0,0,NONE,0,NONE,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,C000,FFDF,0,0,,,FFE0,FFFF
msp430e337,0,0,1,0,NONE,0,NONE,0,80,200,05FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,8000,FFDF,0,0,,,FFE0,FFFF
msp430f110,0,0,0,0,EMEX_LOW,2,NONE,0,50,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1080,80,10FF,1080,0,0,0,FC00,FFDF,0,0,,,FFE0,FFFF
msp430f1101,0,0,0,0,EMEX_LOW,2,NONE,0,50,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1080,80,10FF,1080,0,0,0,FC00,FFDF,0,0,,,FFE0,FFFF
msp430f1101a,0,0,0,0,EMEX_LOW,2,NONE,0,50,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1080,80,10FF,1080,0,0,0,FC00,FFDF,0,0,,,FFE0,FFFF
msp430f1111,0,0,0,0,EMEX_LOW,2,NONE,0,50,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,F800,FFDF,0,0,,,FFE0,FFFF
msp430f1111a,0,0,0,0,EMEX_LOW,2,NONE,0,50,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,F800,FFDF,0,0,,,FFE0,FFFF
msp430f112,0,0,0,0,EMEX_LOW,2,NONE,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,F000,FFDF,0,0,,,FFE0,FFFF
msp430f1121,0,0,0,0,EMEX_LOW,2,NONE,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,F000,FFDF,0,0,,,FFE0,FFFF
msp430f1121a,0,0,0,0,EMEX_LOW,2,NONE,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,F000,FFDF,0,0,,,FFE0,FFFF
msp430f1122,0,0,0,0,EMEX_LOW,2,NONE,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,F000,FFDF,0,0,,,FFE0,FFFF
msp430f1132,0,0,0,0,EMEX_LOW,2,NONE,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,E000,FFDF,0,0,,,FFE0,FFFF
msp430f122,0,0,0,0,EMEX_LOW,2,NONE,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,F000,FFDF,0,0,,,FFE0,FFFF
msp430f1222,0,0,0,0,EMEX_LOW,2,NONE,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,F000,FFDF,0,0,,,FFE0,FFFF
msp430f123,0,0,0,0,EMEX_LOW,2,NONE,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,E000,FFDF,0,0,,,FFE0,FFFF
msp430f1232,0,0,0,0,EMEX_LOW,2,NONE,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,E000,FFDF,0,0,,,FFE0,FFFF
msp430f133,0,0,0,0,EMEX_MEDIUM,3,NONE,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,E000,FFDF,0,0,,,FFE0,FFFF
msp430f135,0,0,0,0,EMEX_MEDIUM,3,NONE,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,C000,FFDF,0,0,,,FFE0,FFFF
msp430f147,0,0,1,0,EMEX_MEDIUM,3,NONE,0,80,200,05FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,8000,FFDF,0,0,,,FFE0,FFFF
msp430f148,0,0,1,0,EMEX_MEDIUM,3,NONE,0,80,200,09FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,4000,FFDF,0,0,,,FFE0,FFFF
msp430f149,0,0,1,0,EMEX_MEDIUM,3,NONE,0,80,200,09FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,1100,FFDF,0,0,,,FFE0,FFFF
msp430f1471,0,0,1,0,EMEX_MEDIUM,3,NONE,0,80,200,05FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,8000,FFDF,0,0,,,FFE0,FFFF
msp430f1481,0,0,1,0,EMEX_MEDIUM,3,NONE,0,80,200,09FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,4000,FFDF,0,0,,,FFE0,FFFF
msp430f1491,0,0,1,0,EMEX_MEDIUM,3,NONE,0,80,200,09FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,1100,FFDF,0,0,,,FFE0,FFFF
msp430f155,0,0,0,0,EMEX_HIGH,8,EXTENDED,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,C000,FFDF,0,0,,,FFE0,FFFF
msp430f156,0,0,0,0,EMEX_HIGH,8,EXTENDED,0,80,200,05FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,A000,FFDF,0,0,,,FFE0,FFFF
msp430f157,0,0,0,0,EMEX_HIGH,8,EXTENDED,0,80,200,05FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,8000,FFDF,0,0,,,FFE0,FFFF
msp430f167,0,0,1,0,EMEX_HIGH,8,EXTENDED,0,80,200,05FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,8000,FFDF,0,0,,,FFE0,FFFF
msp430f168,0,0,1,0,EMEX_HIGH,8,EXTENDED,0,80,200,09FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,4000,FFDF,0,0,,,FFE0,FFFF
msp430f169,0,0,1,0,EMEX_HIGH,8,EXTENDED,0,80,200,09FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,1100,FFDF,0,0,,,FFE0,FFFF
msp430f1610,0,0,1,0,EMEX_HIGH,8,EXTENDED,0,80,1100,24FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,80,10FF,1080,1000,0,0,8000,FFDF,0,0,,,FFE0,FFFF
msp430f1611,0,0,1,0,EMEX_HIGH,8,EXTENDED,0,80,1100,38FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,80,10FF,1080,1000,0,0,4000,FFDF,0,0,,,FFE0,FFFF
msp430f1612,0,0,1,0,EMEX_HIGH,8,EXTENDED,0,80,1100,24FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,80,10FF,1080,1000,0,0,2500,FFDF,0,0,,,FFE0,FFFF
msp430f2001,0,0,0,1,EMEX_LOW,2,STANDARD,0,50,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,FC00,FFDF,0,0,,,FFE0,FFFF
msp430f2011,0,0,0,1,EMEX_LOW,2,STANDARD,0,50,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F800,FFDF,0,0,,,FFE0,FFFF
msp430f2002,0,0,0,1,EMEX_LOW,2,STANDARD,0,50,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,FC00,FFDF,0,0,,,FFE0,FFFF
msp430f2012,0,0,0,1,EMEX_LOW,2,STANDARD,0,50,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F800,FFDF,0,0,,,FFE0,FFFF
msp430f2003,0,0,0,1,EMEX_LOW,2,STANDARD,0,50,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,FC00,FFDF,0,0,,,FFE0,FFFF
msp430f2013,0,0,0,1,EMEX_LOW,2,STANDARD,0,50,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F800,FFDF,0,0,,,FFE0,FFFF
msp430f2101,0,CPU19,0,0,EMEX_LOW,2,STANDARD,0,50,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,FC00,FFDD,0,0,FFDE,2,FFE0,FFFF
msp430f2111,0,CPU19,0,0,EMEX_LOW,2,STANDARD,0,50,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F800,FFDD,0,0,FFDE,2,FFE0,FFFF
msp430f2121,0,CPU19,0,0,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F000,FFDD,0,0,FFDE,2,FFE0,FFFF
msp430f2131,0,CPU19,0,0,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,E000,FFDD,0,0,FFDE,2,FFE0,FFFF
msp430f2112,0,CPU19,0,1,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F800,FFDD,0,0,FFDE,2,FFE0,FFFF
msp430f2122,0,CPU19,0,1,EMEX_LOW,2,STANDARD,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F000,FFDD,0,0,FFDE,2,FFE0,FFFF
msp430f2132,0,CPU19,0,1,EMEX_LOW,2,STANDARD,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,E000,FFDD,0,0,FFDE,2,FFE0,FFFF
msp430f2232,0,CPU19,0,1,EMEX_LOW,2,STANDARD,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,E000,FFDD,0,0,FFDE,2,FFE0,FFFF
msp430f2252,0,CPU19,0,1,EMEX_LOW,2,STANDARD,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,C000,FFDD,0,0,FFDE,2,FFE0,FFFF
msp430f2272,0,CPU19,0,1,EMEX_LOW,2,STANDARD,0,80,200,05FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,8000,FFDD,0,0,FFDE,2,FFE0,FFFF
msp430f2234,0,CPU19,0,1,EMEX_LOW,2,STANDARD,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,E000,FFDD,0,0,FFDE,2,FFE0,FFFF
msp430f2254,0,CPU19,0,1,EMEX_LOW,2,STANDARD,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,C000,FFDD,0,0,FFDE,2,FFE0,FFFF
msp430f2274,0,CPU19,0,1,EMEX_LOW,2,STANDARD,0,80,200,05FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,8000,FFDD,0,0,FFDE,2,FFE0,FFFF
msp430f2330,0,CPU19,2,0,EMEX_LOW,2,STANDARD,0,80,200,05FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,E000,FFDD,0,0,FFDE,2,FFE0,FFFF
msp430f2350,0,CPU19,2,0,EMEX_LOW,2,STANDARD,0,80,200,09FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,C000,FFDD,0,0,FFDE,2,FFE0,FFFF
msp430f2370,0,CPU19,2,0,EMEX_LOW,2,STANDARD,0,80,200,09FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,8000,FFDD,0,0,FFDE,2,FFE0,FFFF
msp430f233,0,CPU19,2,0,EMEX_MEDIUM,3,EXTENDED,0,80,200,05FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,E000,FFDD,0,0,FFDE,2,FFE0,FFFF
msp430f235,0,CPU19,2,0,EMEX_MEDIUM,3,EXTENDED,0,80,200,09FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,C000,FFDD,0,0,FFDE,2,FFE0,FFFF
msp430f247,0,CPU19,2,0,EMEX_MEDIUM,3,EXTENDED,0,80,1100,20FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,40,10FF,10C0,1080,1040,1000,8000,FFBF,0,0,FFDE,2,FFC0,FFFF
msp430f248,0,CPU19,2,0,EMEX_MEDIUM,3,EXTENDED,0,80,1100,20FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,40,10FF,10C0,1080,1040,1000,4000,FFBF,0,0,FFDE,2,FFC0,FFFF
msp430f249,0,CPU19,2,0,EMEX_MEDIUM,3,EXTENDED,0,80,200,09FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,1100,FFBF,0,0,FFDE,2,FFC0,FFFF
msp430f2410,0,CPU19,2,0,EMEX_MEDIUM,3,EXTENDED,0,80,1100,20FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,40,10FF,10C0,1080,1040,1000,2100,FFBF,0,0,FFDE,2,FFC0,FFFF
msp430f2471,0,CPU19,2,0,EMEX_MEDIUM,3,EXTENDED,0,80,1100,20FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,40,10FF,10C0,1080,1040,1000,8000,FFBF,0,0,FFDE,2,FFC0,FFFF
msp430f2481,0,CPU19,2,0,EMEX_MEDIUM,3,EXTENDED,0,80,1100,20FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,40,10FF,10C0,1080,1040,1000,4000,FFBF,0,0,FFDE,2,FFC0,FFFF
msp430f2491,0,CPU19,2,0,EMEX_MEDIUM,3,EXTENDED,0,80,200,09FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,1100,FFBF,0,0,FFDE,2,FFC0,FFFF
msp430f2416,1,CPU16; CPU19,2,0,EMEX_HIGH,8,EXTENDED,0,80,1100,20FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,40,10FF,10C0,1080,1040,1000,2100,FFBD,10000,18FFF,FFBE,2,FFC0,FFFF
msp430f2417,1,CPU16; CPU19,2,0,EMEX_HIGH,8,EXTENDED,0,80,1100,30FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,40,10FF,10C0,1080,1040,1000,3100,FFBD,10000,19FFF,FFBE,2,FFC0,FFFF
msp430f2418,1,CPU16; CPU19,2,0,EMEX_HIGH,8,EXTENDED,0,80,1100,30FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,40,10FF,10C0,1080,1040,1000,3100,FFBD,10000,1FFFF,FFBE,2,FFC0,FFFF
msp430f2419,1,CPU16; CPU19,2,0,EMEX_HIGH,8,EXTENDED,0,80,1100,20FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,40,10FF,10C0,1080,1040,1000,2100,FFBD,10000,1FFFF,FFBE,2,FFC0,FFFF
msp430f2616,1,CPU16; CPU19,2,0,EMEX_HIGH,8,EXTENDED,0,80,1100,20FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,40,10FF,10C0,1080,1040,1000,2100,FFBD,10000,18FFF,FFBE,2,FFC0,FFFF
msp430f2617,1,CPU16; CPU19,2,0,EMEX_HIGH,8,EXTENDED,0,80,1100,30FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,40,10FF,10C0,1080,1040,1000,3100,FFBD,10000,19FFF,FFBE,2,FFC0,FFFF
msp430f2618,1,CPU16; CPU19,2,0,EMEX_HIGH,8,EXTENDED,0,80,1100,30FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,40,10FF,10C0,1080,1040,1000,3100,FFBD,10000,1FFFF,FFBE,2,FFC0,FFFF
msp430f2619,1,CPU16; CPU19,2,0,EMEX_HIGH,8,EXTENDED,0,80,1100,20FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,40,10FF,10C0,1080,1040,1000,2100,FFBD,10000,1FFFF,FFBE,2,FFC0,FFFF
msp430f412,0,0,0,0,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,F000,FFBD,0,0,,,FFE0,FFFF
msp430f413,0,0,0,0,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,E000,FFDF,0,0,,,FFE0,FFFF
msp430f415,0,0,0,0,EMEX_LOW,2,STANDARD,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,C000,FFDF,0,0,,,FFE0,FFFF
msp430f417,0,0,0,0,EMEX_LOW,2,STANDARD,0,80,200,05FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,8000,FFDF,0,0,,,FFE0,FFFF
msp430f4132,0,CPU19,0,1,EMEX_LOW,2,EXTENDED,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,E000,FFDF,0,0,,,FFE0,FFFF
msp430f4152,0,CPU19,0,1,EMEX_LOW,2,EXTENDED,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,C000,FFDF,0,0,,,FFE0,FFFF
msp430f423,0,0,1,0,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,E000,FFDF,0,0,,,FFE0,FFFF
msp430f425,0,0,1,0,EMEX_LOW,2,STANDARD,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,C000,FFDF,0,0,,,FFE0,FFFF
msp430f427,0,0,1,0,EMEX_LOW,2,STANDARD,0,80,200,05FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,8000,FFDF,0,0,,,FFE0,FFFF
msp430f423a,0,0,1,0,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,E000,FFDF,0,0,,,FFE0,FFFF
msp430f425a,0,0,1,0,EMEX_LOW,2,STANDARD,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,C000,FFDF,0,0,,,FFE0,FFFF
msp430f427a,0,0,1,0,EMEX_LOW,2,STANDARD,0,80,200,05FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,8000,FFDF,0,0,,,FFE0,FFFF
msp430f435,0,0,0,0,EMEX_HIGH,8,EXTENDED,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,C000,FFDF,0,0,,,FFE0,FFFF
msp430f436,0,0,0,0,EMEX_HIGH,8,EXTENDED,0,80,200,05FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,A000,FFDF,0,0,,,FFE0,FFFF
msp430f437,0,0,0,0,EMEX_HIGH,8,EXTENDED,0,80,200,05FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,8000,FFDF,0,0,,,FFE0,FFFF
msp430f4351,0,0,0,0,EMEX_HIGH,8,EXTENDED,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,C000,FFDF,0,0,,,FFE0,FFFF
msp430f4361,0,0,0,0,EMEX_HIGH,8,EXTENDED,0,80,200,05FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,A000,FFDF,0,0,,,FFE0,FFFF
msp430f4371,0,0,0,0,EMEX_HIGH,8,EXTENDED,0,80,200,05FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,8000,FFDF,0,0,,,FFE0,FFFF
msp430f4481,0,0,1,0,EMEX_HIGH,8,EXTENDED,0,80,200,09FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,4000,FFDF,0,0,,,FFE0,FFFF
msp430f4491,0,0,1,0,EMEX_HIGH,8,EXTENDED,0,80,200,09FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,1100,FFDF,0,0,,,FFE0,FFFF
msp430f447,0,0,1,0,EMEX_HIGH,8,EXTENDED,0,80,200,05FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,8000,FFDF,0,0,,,FFE0,FFFF
msp430f448,0,0,1,0,EMEX_HIGH,8,EXTENDED,0,80,200,09FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,4000,FFDF,0,0,,,FFE0,FFFF
msp430f449,0,0,1,0,EMEX_HIGH,8,EXTENDED,0,80,200,09FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,1100,FFDF,0,0,,,FFE0,FFFF
msp430fe423,0,0,0,0,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,E000,FFDF,0,0,,,FFE0,FFFF
msp430fe425,0,0,0,0,EMEX_LOW,2,STANDARD,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,C000,FFDF,0,0,,,FFE0,FFFF
msp430fe427,0,0,0,0,EMEX_LOW,2,STANDARD,0,80,200,05FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,8000,FFDF,0,0,,,FFE0,FFFF
msp430fe423a,0,0,0,0,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,E000,FFDF,0,0,,,FFE0,FFFF
msp430fe425a,0,0,0,0,EMEX_LOW,2,STANDARD,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,C000,FFDF,0,0,,,FFE0,FFFF
msp430fe427a,0,0,0,0,EMEX_LOW,2,STANDARD,0,80,200,05FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,8000,FFDF,0,0,,,FFE0,FFFF
msp430fe4232,0,0,0,0,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,E000,FFDF,0,0,,,FFE0,FFFF
msp430fe4242,0,0,0,0,EMEX_LOW,2,STANDARD,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,D000,FFDF,0,0,,,FFE0,FFFF
msp430fe4252,0,0,0,0,EMEX_LOW,2,STANDARD,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,C000,FFDF,0,0,,,FFE0,FFFF
msp430fe4272,0,0,0,0,EMEX_LOW,2,STANDARD,0,80,200,05FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,8000,FFDF,0,0,,,FFE0,FFFF
msp430f4783,0,CPU19,4,0,EMEX_LOW,2,STANDARD,0,80,200,09FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,4000,FFDF,0,0,,,FFE0,FFFF
msp430f4793,0,CPU19,4,0,EMEX_LOW,2,STANDARD,0,80,200,0BFF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,1100,FFDF,0,0,,,FFE0,FFFF
msp430f4784,0,CPU19,4,0,EMEX_LOW,2,STANDARD,0,80,200,09FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,4000,FFDF,0,0,,,FFE0,FFFF
msp430f4794,0,CPU19,4,0,EMEX_LOW,2,STANDARD,0,80,200,0BFF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,1100,FFDF,0,0,,,FFE0,FFFF
msp430f47126,1,CPU19,4,0,EMEX_HIGH,8,EXTENDED,0,80,1100,20FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,40,10FF,10C0,1080,1040,1000,2100,FFBD,0,0,FFBE,2,FFC0,FFFF
msp430f47127,1,CPU19,4,0,EMEX_HIGH,8,EXTENDED,0,80,1100,20FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,40,10FF,10C0,1080,1040,1000,2100,FFBD,0,0,FFBE,2,FFC0,FFFF
msp430f47163,1,CPU19,4,0,EMEX_HIGH,8,EXTENDED,0,80,1100,20FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,40,10FF,10C0,1080,1040,1000,2100,FFBD,10000,18FFF,FFBE,2,FFC0,FFFF
msp430f47173,1,CPU19,4,0,EMEX_HIGH,8,EXTENDED,0,80,1100,30FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,40,10FF,10C0,1080,1040,1000,3100,FFBD,10000,19FFF,FFBE,2,FFC0,FFFF
msp430f47183,1,CPU19,4,0,EMEX_HIGH,8,EXTENDED,0,80,1100,30FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,40,10FF,10C0,1080,1040,1000,3100,FFBD,10000,1FFFF,FFBE,2,FFC0,FFFF
msp430f47193,1,CPU19,4,0,EMEX_HIGH,8,EXTENDED,0,80,1100,20FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,40,10FF,10C0,1080,1040,1000,2100,FFBD,10000,1FFFF,FFBE,2,FFC0,FFFF
msp430f47166,1,CPU19,4,0,EMEX_HIGH,8,EXTENDED,0,80,1100,20FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,40,10FF,10C0,1080,1040,1000,2100,FFBD,10000,18FFF,FFBE,2,FFC0,FFFF
msp430f47176,1,CPU19,4,0,EMEX_HIGH,8,EXTENDED,0,80,1100,30FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,40,10FF,10C0,1080,1040,1000,3100,FFBD,10000,19FFF,FFBE,2,FFC0,FFFF
msp430f47186,1,CPU19,4,0,EMEX_HIGH,8,EXTENDED,0,80,1100,30FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,40,10FF,10C0,1080,1040,1000,3100,FFBD,10000,1FFFF,FFBE,2,FFC0,FFFF
msp430f47196,1,CPU19,4,0,EMEX_HIGH,8,EXTENDED,0,80,1100,20FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,40,10FF,10C0,1080,1040,1000,2100,FFBD,10000,1FFFF,FFBE,2,FFC0,FFFF
msp430f47167,1,CPU19,4,0,EMEX_HIGH,8,EXTENDED,0,80,1100,20FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,40,10FF,10C0,1080,1040,1000,2100,FFBD,10000,18FFF,FFBE,2,FFC0,FFFF
msp430f47177,1,CPU19,4,0,EMEX_HIGH,8,EXTENDED,0,80,1100,30FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,40,10FF,10C0,1080,1040,1000,3100,FFBD,10000,19FFF,FFBE,2,FFC0,FFFF
msp430f47187,1,CPU19,4,0,EMEX_HIGH,8,EXTENDED,0,80,1100,30FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,40,10FF,10C0,1080,1040,1000,3100,FFBD,10000,1FFFF,FFBE,2,FFC0,FFFF
msp430f47197,1,CPU19,4,0,EMEX_HIGH,8,EXTENDED,0,80,1100,20FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,40,10FF,10C0,1080,1040,1000,2100,FFBD,10000,1FFFF,FFBE,2,FFC0,FFFF
msp430f4250,0,0,0,0,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,C000,FFDF,0,0,,,FFE0,FFFF
msp430f4260,0,0,0,0,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,A000,FFDF,0,0,,,FFE0,FFFF
msp430f4270,0,0,0,0,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,8000,FFDF,0,0,,,FFE0,FFFF
msp430fg4250,0,0,0,0,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,C000,FFDF,0,0,,,FFE0,FFFF
msp430fg4260,0,0,0,0,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,A000,FFDF,0,0,,,FFE0,FFFF
msp430fg4270,0,0,0,0,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,8000,FFDF,0,0,,,FFE0,FFFF
msp430fw423,0,0,0,0,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,E000,FFDF,0,0,,,FFE0,FFFF
msp430fw425,0,0,0,0,EMEX_LOW,2,STANDARD,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,C000,FFDF,0,0,,,FFE0,FFFF
msp430fw427,0,0,0,0,EMEX_LOW,2,STANDARD,0,80,200,05FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,8000,FFDF,0,0,,,FFE0,FFFF
msp430fw428,0,0,0,0,EMEX_LOW,2,STANDARD,0,80,200,09FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,4000,FFDF,0,0,,,FFE0,FFFF
msp430fw429,0,0,0,0,EMEX_LOW,2,STANDARD,0,80,200,09FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,1100,FFDF,0,0,,,FFE0,FFFF
msp430fg437,0,0,0,0,EMEX_LOW,2,EXTENDED,0,80,200,05FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,8000,FFDF,0,0,,,FFE0,FFFF
msp430fg438,0,0,0,0,EMEX_LOW,2,EXTENDED,0,80,200,09FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,4000,FFDF,0,0,,,FFE0,FFFF
msp430fg439,0,0,0,0,EMEX_LOW,2,EXTENDED,0,80,200,09FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,1100,FFDF,0,0,,,FFE0,FFFF
msp430f438,0,0,0,0,EMEX_LOW,2,EXTENDED,0,80,200,09FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,4000,FFDF,0,0,,,FFE0,FFFF
msp430f439,0,0,0,0,EMEX_LOW,2,EXTENDED,0,80,200,09FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,80,10FF,1080,1000,0,0,1100,FFDF,0,0,,,FFE0,FFFF
msp430f477,0,0,0,0,EMEX_LOW,2,EXTENDED,0,80,200,09FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,8000,FFDF,0,0,,,FFE0,FFFF
msp430f478,0,0,0,0,EMEX_LOW,2,EXTENDED,0,80,200,09FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,4000,FFDF,0,0,,,FFE0,FFFF
msp430f479,0,0,0,0,EMEX_LOW,2,EXTENDED,0,80,200,09FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,1100,FFDF,0,0,,,FFE0,FFFF
msp430fg477,0,CPU19,0,0,EMEX_LOW,2,EXTENDED,0,80,200,09FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,8000,FFDF,0,0,,,FFE0,FFFF
msp430fg478,0,CPU19,0,0,EMEX_LOW,2,EXTENDED,0,80,200,09FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,4000,FFDF,0,0,,,FFE0,FFFF
msp430fg479,0,CPU19,0,0,EMEX_LOW,2,EXTENDED,0,80,200,09FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,1100,FFDF,0,0,,,FFE0,FFFF
msp430f46161,1,0,1,0,EMEX_HIGH,8,EXTENDED,0,80,1100,20FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,80,10FF,1080,1000,0,0,2100,FFBD,10000,18FFF,FFBE,2,FFC0,FFFF
msp430f46171,1,0,1,0,EMEX_HIGH,8,EXTENDED,0,80,1100,30FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,80,10FF,1080,1000,0,0,3100,FFBD,10000,19FFF,FFBE,2,FFC0,FFFF
msp430f46181,1,0,1,0,EMEX_HIGH,8,EXTENDED,0,80,1100,30FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,80,10FF,1080,1000,0,0,3100,FFBD,10000,1FFFF,FFBE,2,FFC0,FFFF
msp430f46191,1,0,1,0,EMEX_HIGH,8,EXTENDED,0,80,1100,20FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,80,10FF,1080,1000,0,0,2100,FFBD,10000,1FFFF,FFBE,2,FFC0,FFFF
msp430f4616,1,CPU16; CPU19,1,0,EMEX_HIGH,8,EXTENDED,0,80,1100,20FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,80,10FF,1080,1000,0,0,2100,FFBD,10000,18FFF,FFBE,2,FFC0,FFFF
msp430f4617,1,CPU16; CPU19,1,0,EMEX_HIGH,8,EXTENDED,0,80,1100,30FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,80,10FF,1080,1000,0,0,3100,FFBD,10000,19FFF,FFBE,2,FFC0,FFFF
msp430f4618,1,CPU16; CPU19,1,0,EMEX_HIGH,8,EXTENDED,0,80,1100,30FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,80,10FF,1080,1000,0,0,3100,FFBD,10000,1FFFF,FFBE,2,FFC0,FFFF
msp430f4619,1,CPU16; CPU19,1,0,EMEX_HIGH,8,EXTENDED,0,80,1100,20FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,80,10FF,1080,1000,0,0,2100,FFBD,10000,1FFFF,FFBE,2,FFC0,FFFF
msp430fg4616,1,CPU16; CPU19,1,0,EMEX_HIGH,8,EXTENDED,0,80,1100,20FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,80,10FF,1080,1000,0,0,2100,FFBD,10000,18FFF,FFBE,2,FFC0,FFFF
msp430fg4617,1,CPU16; CPU19,1,0,EMEX_HIGH,8,EXTENDED,0,80,1100,30FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,80,10FF,1080,1000,0,0,3100,FFBD,10000,19FFF,FFBE,2,FFC0,FFFF
msp430fg4618,1,CPU16; CPU19,1,0,EMEX_HIGH,8,EXTENDED,0,80,1100,30FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,80,10FF,1080,1000,0,0,3100,FFBD,10000,1FFFF,FFBE,2,FFC0,FFFF
msp430fg4619,1,CPU16; CPU19,1,0,EMEX_HIGH,8,EXTENDED,0,80,1100,20FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,80,10FF,1080,1000,0,0,2100,FFBD,10000,1FFFF,FFBE,2,FFC0,FFFF
msp430f5418,2,CPU15; CPU16; CPU18; CPU20; CPU21; CPU22; CPU23; CPU24; CPU25; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,5C00,FF7F,10000,25BFB,,,FF80,FFFF
msp430f5419,2,CPU15; CPU16; CPU18; CPU20; CPU21; CPU22; CPU23; CPU24; CPU25; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,5C00,FF7F,10000,25BFB,,,FF80,FFFF
msp430f5435,2,CPU15; CPU16; CPU18; CPU20; CPU21; CPU22; CPU23; CPU24; CPU25; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,5C00,FF7F,10000,35BFB,,,FF80,FFFF
msp430f5436,2,CPU15; CPU16; CPU18; CPU20; CPU21; CPU22; CPU23; CPU24; CPU25; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,5C00,FF7F,10000,35BFB,,,FF80,FFFF
msp430f5437,2,CPU15; CPU16; CPU18; CPU20; CPU21; CPU22; CPU23; CPU24; CPU25; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,5C00,FF7F,10000,45BFB,,,FF80,FFFF
msp430f5438,2,CPU15; CPU16; CPU18; CPU20; CPU21; CPU22; CPU23; CPU24; CPU25; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,5C00,FF7F,10000,45BFB,,,FF80,FFFF
msp430f5418a,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,5C00,FF7F,10000,25BFF,,,FF80,FFFF
msp430f5419a,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,5C00,FF7F,10000,25BFF,,,FF80,FFFF
msp430f5435a,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,5C00,FF7F,10000,35BFF,,,FF80,FFFF
msp430f5436a,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,5C00,FF7F,10000,35BFF,,,FF80,FFFF
msp430f5437a,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,5C00,FF7F,10000,45BFF,,,FF80,FFFF
msp430f5438a,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,5C00,FF7F,10000,45BFF,,,FF80,FFFF
msp430f5212,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,143FF,,,FF80,FFFF
msp430f5213,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,1C3FF,,,FF80,FFFF
msp430f5214,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,243FF,,,FF80,FFFF
msp430f5217,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,143FF,,,FF80,FFFF
msp430f5218,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,1C3FF,,,FF80,FFFF
msp430f5219,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,243FF,,,FF80,FFFF
msp430f5222,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,143FF,,,FF80,FFFF
msp430f5223,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,1C3FF,,,FF80,FFFF
msp430f5224,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,243FF,,,FF80,FFFF
msp430f5227,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,143FF,,,FF80,FFFF
msp430f5228,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,1C3FF,,,FF80,FFFF
msp430f5229,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,243FF,,,FF80,FFFF
msp430f5232,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,143FF,,,FF80,FFFF
msp430f5234,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,243FF,,,FF80,FFFF
msp430f5237,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,143FF,,,FF80,FFFF
msp430f5239,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,243FF,,,FF80,FFFF
msp430f5242,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,143FF,,,FF80,FFFF
msp430f5244,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,243FF,,,FF80,FFFF
msp430f5247,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,143FF,,,FF80,FFFF
msp430f5249,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,243FF,,,FF80,FFFF
msp430f5304,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,33FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,E000,FF7F,0,0,,,FF80,FFFF
msp430f5308,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,33FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,0,0,,,FF80,FFFF
msp430f5309,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,33FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,A000,FF7F,0,0,,,FF80,FFFF
msp430f5310,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,33FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,,,FF80,FFFF
msp430f5340,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,33FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,143FF,,,FF80,FFFF
msp430f5341,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,3BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,1C3FF,,,FF80,FFFF
msp430f5342,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,243FF,,,FF80,FFFF
msp430f5324,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,33FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,143FF,,,FF80,FFFF
msp430f5325,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,33FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,143FF,,,FF80,FFFF
msp430f5326,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,3BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,1C3FF,,,FF80,FFFF
msp430f5327,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,3BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,1C3FF,,,FF80,FFFF
msp430f5328,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,243FF,,,FF80,FFFF
msp430f5329,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,243FF,,,FF80,FFFF
msp430f5500,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,33FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,E000,FF7F,0,0,,,FF80,FFFF
msp430f5501,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,33FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,0,0,,,FF80,FFFF
msp430f5502,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,33FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,A000,FF7F,0,0,,,FF80,FFFF
msp430f5503,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,33FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,,,FF80,FFFF
msp430f5504,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,33FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,E000,FF7F,0,0,,,FF80,FFFF
msp430f5505,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,33FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,0,0,,,FF80,FFFF
msp430f5506,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,33FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,A000,FF7F,0,0,,,FF80,FFFF
msp430f5507,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,33FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,,,FF80,FFFF
msp430f5508,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,33FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,0,0,,,FF80,FFFF
msp430f5509,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,33FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,A000,FF7F,0,0,,,FF80,FFFF
msp430f5510,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,33FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,,,FF80,FFFF
msp430f5513,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,33FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,,,FF80,FFFF
msp430f5514,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,33FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,143FF,,,FF80,FFFF
msp430f5515,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,33FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,143FF,,,FF80,FFFF
msp430f5517,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,3BFF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,1C3FF,,,FF80,FFFF
msp430f5519,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,43FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,243FF,,,FF80,FFFF
msp430f5521,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,3BFF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,,,FF80,FFFF
msp430f5522,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,43FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,,,FF80,FFFF
msp430f5524,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,33FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,143FF,,,FF80,FFFF
msp430f5525,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,33FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,143FF,,,FF80,FFFF
msp430f5526,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,3BFF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,1C3FF,,,FF80,FFFF
msp430f5527,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,3BFF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,1C3FF,,,FF80,FFFF
msp430f5528,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,43FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,243FF,,,FF80,FFFF
msp430f5529,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,43FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,243FF,,,FF80,FFFF
msp430p112,0,0,0,0,NONE,0,NONE,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,F000,FFDF,0,0,,,FFE0,FFFF
msp430p313,0,0,0,0,NONE,0,NONE,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,E000,FFDF,0,0,,,FFE0,FFFF
msp430p315,0,0,0,0,NONE,0,NONE,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,C000,FFDF,0,0,,,FFE0,FFFF
msp430p315s,0,0,0,0,NONE,0,NONE,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,C000,FFDF,0,0,,,FFE0,FFFF
msp430p325,0,0,0,0,NONE,0,NONE,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,C000,FFDF,0,0,,,FFE0,FFFF
msp430p337,0,0,1,0,NONE,0,NONE,0,80,200,05FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,8000,FFDF,0,0,,,FFE0,FFFF
cc430f5133,2,CPU18; CPU20; CPU21; CPU22; CPU23; CPU24; CPU25; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,23FD,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,E000,FF7F,0,0,,,FF80,FFFF
cc430f5135,2,CPU18; CPU20; CPU21; CPU22; CPU23; CPU24; CPU25; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,23FD,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,0,0,,,FF80,FFFF
cc430f5137,2,CPU18; CPU20; CPU21; CPU22; CPU23; CPU24; CPU25; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,2BFD,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,,,FF80,FFFF
cc430f6125,2,CPU18; CPU20; CPU21; CPU22; CPU23; CPU24; CPU25; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,23FD,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,0,0,,,FF80,FFFF
cc430f6126,2,CPU18; CPU20; CPU21; CPU22; CPU23; CPU24; CPU25; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,23FD,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,,,FF80,FFFF
cc430f6127,2,CPU18; CPU20; CPU21; CPU22; CPU23; CPU24; CPU25; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,2BFD,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,,,FF80,FFFF
cc430f6135,2,CPU18; CPU20; CPU21; CPU22; CPU23; CPU24; CPU25; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,23FD,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,0,0,,,FF80,FFFF
cc430f6137,2,CPU18; CPU20; CPU21; CPU22; CPU23; CPU24; CPU25; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,2BFD,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,,,FF80,FFFF
cc430f5123,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,23FD,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,E000,FF7F,0,0,,,FF80,FFFF
cc430f5125,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,23FD,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,0,0,,,FF80,FFFF
cc430f5143,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,23FD,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,E000,FF7F,0,0,,,FF80,FFFF
cc430f5145,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,23FD,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,0,0,,,FF80,FFFF
cc430f5147,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,2BFD,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,,,FF80,FFFF
cc430f6143,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,23FD,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,E000,FF7F,0,0,,,FF80,FFFF
cc430f6145,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,23FD,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,0,0,,,FF80,FFFF
cc430f6147,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,2BFD,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,,,FF80,FFFF
msp430f5333,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,27FFF,,,FF80,FFFF
msp430f5335,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,63FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,47FFF,,,FF80,FFFF
msp430f5336,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,63FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,27FFF,,,FF80,FFFF
msp430f5338,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,63FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,47FFF,,,FF80,FFFF
msp430f5630,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,27FFF,,,FF80,FFFF
msp430f5631,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,37FFF,,,FF80,FFFF
msp430f5632,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,47FFF,,,FF80,FFFF
msp430f5633,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,27FFF,,,FF80,FFFF
msp430f5634,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,37FFF,,,FF80,FFFF
msp430f5635,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,47FFF,,,FF80,FFFF
msp430f5636,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,27FFF,,,FF80,FFFF
msp430f5637,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,37FFF,,,FF80,FFFF
msp430f5638,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,47FFF,,,FF80,FFFF
msp430f6433,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,27FFF,,,FF80,FFFF
msp430f6435,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,47FFF,,,FF80,FFFF
msp430f6436,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,27FFF,,,FF80,FFFF
msp430f6438,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,47FFF,,,FF80,FFFF
msp430f6630,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,27FFF,,,FF80,FFFF
msp430f6631,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,37FFF,,,FF80,FFFF
msp430f6632,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,47FFF,,,FF80,FFFF
msp430f6633,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,27FFF,,,FF80,FFFF
msp430f6634,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,37FFF,,,FF80,FFFF
msp430f6635,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,47FFF,,,FF80,FFFF
msp430f6636,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,27FFF,,,FF80,FFFF
msp430f6637,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,37FFF,,,FF80,FFFF
msp430f6638,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,47FFF,,,FF80,FFFF
msp430f5358,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,63FF,F8000,FBFFF,0,0,0,0,0,0,2400,FC000,FFFFF,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,67FFF,,,FF80,FFFF
msp430f5359,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,63FF,F0000,FBFFF,0,0,0,0,0,0,2400,FC000,FFFFF,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,87FFF,,,FF80,FFFF
msp430f5658,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,F8000,FBFFF,0,0,1C00,23FF,0,0,2400,FC000,FFFFF,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,67FFF,,,FF80,FFFF
msp430f5659,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,F0000,FBFFF,0,0,1C00,23FF,0,0,2400,FC000,FFFFF,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,87FFF,,,FF80,FFFF
msp430f6458,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,63FF,F8000,FBFFF,0,0,0,0,0,0,2400,FC000,FFFFF,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,67FFF,,,FF80,FFFF
msp430f6459,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,63FF,F0000,FBFFF,0,0,0,0,0,0,2400,FC000,FFFFF,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,87FFF,,,FF80,FFFF
msp430f6658,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,F8000,FBFFF,0,0,1C00,23FF,0,0,2400,FC000,FFFFF,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,67FFF,,,FF80,FFFF
msp430f6659,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,63FF,F0000,FBFFF,0,0,1C00,23FF,0,0,2400,FC000,FFFFF,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,10000,87FFF,,,FF80,FFFF
msp430fg6425,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,143FF,,,FF80,FFFF
msp430fg6426,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,43FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,243FF,,,FF80,FFFF
msp430fg6625,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,43FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,143FF,,,FF80,FFFF
msp430fg6626,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,2400,43FF,0,0,0,0,1C00,23FF,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,243FF,,,FF80,FFFF
msp430l092,0,CPU18; CPU21; CPU22; CPU23; CPU27; CPU29; CPU30,0,0,EMEX_EXTRA_SMALL_5XX,2,EXTENDED,1,80,2380,23FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1C00,60,1C5F,1C00,0,0,0,1C80,237F,0,0,,,1C60,1C7F
msp430c091,0,CPU18; CPU21; CPU22; CPU23; CPU27; CPU29; CPU30,0,0,EMEX_EXTRA_SMALL_5XX,2,EXTENDED,1,80,2380,23FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1C00,60,1C5F,1C00,0,0,0,FC80,FFDF,0,0,,,FFE0,FFFF
msp430c092,0,CPU18; CPU21; CPU22; CPU23; CPU27; CPU29; CPU30,0,0,EMEX_EXTRA_SMALL_5XX,2,EXTENDED,1,80,2380,23FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1C00,60,1C5F,1C00,0,0,0,F880,FFDF,0,0,,,FFE0,FFFF
msp430xgeneric,2,0,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,6400,FF7F,10000,463FF,,,FF80,FFFF
msp430f5xx_6xxgeneric,2,0,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,6400,FF7F,10000,463FF,,,FF80,FFFF
msp430fr5xx_6xxgeneric,2,0,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,6400,FF7F,10000,463FF,,,FF80,FFFF
msp430fr2xx_4xxgeneric,2,0,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,6400,FF7F,10000,463FF,,,FF80,FFFF
msp430fr57xxgeneric,2,0,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,6400,FF7F,10000,463FF,,,FF80,FFFF
msp430i2xxgeneric,0,0,2,1,EMEX_LOW,2,STANDARD,0,80,200,05FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,400,13FF,1000,0,0,0,C000,FFDB,0,0,FFDC,4,FF80,FFFF
msp430f5131,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,E000,FF7F,0,0,,,FF80,FFFF
msp430f5151,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,0,0,,,FF80,FFFF
msp430f5171,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,,,FF80,FFFF
msp430f5132,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,E000,FF7F,0,0,,,FF80,FFFF
msp430f5152,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,0,0,,,FF80,FFFF
msp430f5172,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,,,FF80,FFFF
msp430f6720,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,0,0,,,FF80,FFFF
msp430f6721,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,,,FF80,FFFF
msp430f6723,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,2BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4000,FF7F,10000,13FFF,,,FF80,FFFF
msp430f6724,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,2BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4000,FF7F,10000,1BFFF,,,FF80,FFFF
msp430f6725,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,2BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4000,FF7F,10000,23FFF,,,FF80,FFFF
msp430f6726,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,3BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4000,FF7F,10000,23FFF,,,FF80,FFFF
msp430f6730,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,0,0,,,FF80,FFFF
msp430f6731,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,,,FF80,FFFF
msp430f6733,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,2BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4000,FF7F,10000,13FFF,,,FF80,FFFF
msp430f6734,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,2BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4000,FF7F,10000,1BFFF,,,FF80,FFFF
msp430f6735,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,2BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4000,FF7F,10000,23FFF,,,FF80,FFFF
msp430f6736,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,3BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4000,FF7F,10000,23FFF,,,FF80,FFFF
msp430f67621,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,2BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4000,FF7F,10000,13FFF,,,FF80,FFFF
msp430f67641,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,2BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4000,FF7F,10000,23FFF,,,FF80,FFFF
msp430f6720a,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,0,0,,,FF80,FFFF
msp430f6721a,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,,,FF80,FFFF
msp430f6723a,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,2BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4000,FF7F,10000,13FFF,,,FF80,FFFF
msp430f6724a,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,2BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4000,FF7F,10000,1BFFF,,,FF80,FFFF
msp430f6725a,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,2BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4000,FF7F,10000,23FFF,,,FF80,FFFF
msp430f6726a,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,3BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4000,FF7F,10000,23FFF,,,FF80,FFFF
msp430f6730a,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,0,0,,,FF80,FFFF
msp430f6731a,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,,,FF80,FFFF
msp430f6733a,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,2BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4000,FF7F,10000,13FFF,,,FF80,FFFF
msp430f6734a,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,2BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4000,FF7F,10000,1BFFF,,,FF80,FFFF
msp430f6735a,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,2BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4000,FF7F,10000,23FFF,,,FF80,FFFF
msp430f6736a,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,3BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4000,FF7F,10000,23FFF,,,FF80,FFFF
msp430f67621a,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,2BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4000,FF7F,10000,13FFF,,,FF80,FFFF
msp430f67641a,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,2BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4000,FF7F,10000,23FFF,,,FF80,FFFF
msp430f67451,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,2BFFF,,,FF80,FFFF
msp430f67651,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,2BFFF,,,FF80,FFFF
msp430f67751,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,2BFFF,,,FF80,FFFF
msp430f67461,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF
msp430f67661,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF
msp430f67761,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF
msp430f67471,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF
msp430f67671,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF
msp430f67771,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF
msp430f67481,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF
msp430f67681,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF
msp430f67781,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF
msp430f67491,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF
msp430f67691,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF
msp430f67791,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF
msp430f6745,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,2BFFF,,,FF80,FFFF
msp430f6765,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,2BFFF,,,FF80,FFFF
msp430f6775,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,2BFFF,,,FF80,FFFF
msp430f6746,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF
msp430f6766,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF
msp430f6776,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF
msp430f6747,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF
msp430f6767,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF
msp430f6777,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF
msp430f6748,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF
msp430f6768,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF
msp430f6778,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF
msp430f6749,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF
msp430f6769,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF
msp430f6779,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF
msp430f67451a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,2BFFF,,,FF80,FFFF
msp430f67651a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,2BFFF,,,FF80,FFFF
msp430f67751a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,2BFFF,,,FF80,FFFF
msp430f67461a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF
msp430f67661a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF
msp430f67761a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF
msp430f67471a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF
msp430f67671a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF
msp430f67771a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF
msp430f67481a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF
msp430f67681a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF
msp430f67781a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF
msp430f67491a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF
msp430f67691a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF
msp430f67791a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF
msp430f6745a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,2BFFF,,,FF80,FFFF
msp430f6765a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,2BFFF,,,FF80,FFFF
msp430f6775a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,2BFFF,,,FF80,FFFF
msp430f6746a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF
msp430f6766a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF
msp430f6776a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF
msp430f6747a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF
msp430f6767a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF
msp430f6777a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,4BFFF,,,FF80,FFFF
msp430f6748a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF
msp430f6768a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF
msp430f6778a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF
msp430f6749a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF
msp430f6769a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF
msp430f6779a,2,CPU21; CPU22; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,9BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,10000,8BFFF,,,FF80,FFFF
msp430fr5720,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,18FF,1880,1800,0,0,F000,FF7F,0,0,FF80,10,FF90,FFFF
msp430fr5721,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,18FF,1880,1800,0,0,F000,FF7F,0,0,FF80,10,FF90,FFFF
msp430fr5722,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,18FF,1880,1800,0,0,E000,FF7F,0,0,FF80,10,FF90,FFFF
msp430fr5723,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,18FF,1880,1800,0,0,E000,FF7F,0,0,FF80,10,FF90,FFFF
msp430fr5724,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,18FF,1880,1800,0,0,E000,FF7F,0,0,FF80,10,FF90,FFFF
msp430fr5725,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,18FF,1880,1800,0,0,E000,FF7F,0,0,FF80,10,FF90,FFFF
msp430fr5726,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,18FF,1880,1800,0,0,C200,FF7F,0,0,FF80,10,FF90,FFFF
msp430fr5727,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,18FF,1880,1800,0,0,C200,FF7F,0,0,FF80,10,FF90,FFFF
msp430fr5728,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,18FF,1880,1800,0,0,C200,FF7F,0,0,FF80,10,FF90,FFFF
msp430fr5729,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,18FF,1880,1800,0,0,C200,FF7F,0,0,FF80,10,FF90,FFFF
msp430fr5730,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,18FF,1880,1800,0,0,F000,FF7F,0,0,FF80,10,FF90,FFFF
msp430fr5731,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,18FF,1880,1800,0,0,F000,FF7F,0,0,FF80,10,FF90,FFFF
msp430fr5732,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,18FF,1880,1800,0,0,E000,FF7F,0,0,FF80,10,FF90,FFFF
msp430fr5733,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,18FF,1880,1800,0,0,E000,FF7F,0,0,FF80,10,FF90,FFFF
msp430fr5734,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,18FF,1880,1800,0,0,E000,FF7F,0,0,FF80,10,FF90,FFFF
msp430fr5735,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,18FF,1880,1800,0,0,E000,FF7F,0,0,FF80,10,FF90,FFFF
msp430fr5736,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,18FF,1880,1800,0,0,C200,FF7F,0,0,FF80,10,FF90,FFFF
msp430fr5737,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,18FF,1880,1800,0,0,C200,FF7F,0,0,FF80,10,FF90,FFFF
msp430fr5738,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,18FF,1880,1800,0,0,C200,FF7F,0,0,FF80,10,FF90,FFFF
msp430fr5739,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,18FF,1880,1800,0,0,C200,FF7F,0,0,FF80,10,FF90,FFFF
msp430g2211,0,0,0,1,EMEX_LOW,2,STANDARD,0,50,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F800,FFDF,0,0,,,FFE0,FFFF
msp430g2201,0,0,0,1,EMEX_LOW,2,STANDARD,0,50,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F800,FFDF,0,0,,,FFE0,FFFF
msp430g2111,0,0,0,1,EMEX_LOW,2,STANDARD,0,50,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,FC00,FFDF,0,0,,,FFE0,FFFF
msp430g2101,0,0,0,1,EMEX_LOW,2,STANDARD,0,50,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,FC00,FFDF,0,0,,,FFE0,FFFF
msp430g2001,0,0,0,1,EMEX_LOW,2,STANDARD,0,50,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,FE00,FFDF,0,0,,,FFE0,FFFF
msp430g2231,0,0,0,1,EMEX_LOW,2,STANDARD,0,50,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F800,FFDF,0,0,,,FFE0,FFFF
msp430g2221,0,0,0,1,EMEX_LOW,2,STANDARD,0,50,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F800,FFDF,0,0,,,FFE0,FFFF
msp430g2131,0,0,0,1,EMEX_LOW,2,STANDARD,0,50,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,FC00,FFDF,0,0,,,FFE0,FFFF
msp430g2121,0,0,0,1,EMEX_LOW,2,STANDARD,0,50,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,FC00,FFDF,0,0,,,FFE0,FFFF
msp430afe221,0,0,2,1,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F000,FFDF,0,0,,,FFE0,FFFF
msp430afe231,0,0,2,1,EMEX_LOW,2,STANDARD,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,E000,FFDF,0,0,,,FFE0,FFFF
msp430afe251,0,0,2,1,EMEX_LOW,2,STANDARD,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,C000,FFDF,0,0,,,FFE0,FFFF
msp430afe222,0,0,2,1,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F000,FFDF,0,0,,,FFE0,FFFF
msp430afe232,0,0,2,1,EMEX_LOW,2,STANDARD,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,E000,FFDF,0,0,,,FFE0,FFFF
msp430afe252,0,0,2,1,EMEX_LOW,2,STANDARD,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,C000,FFDF,0,0,,,FFE0,FFFF
msp430afe223,0,0,2,1,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F000,FFDF,0,0,,,FFE0,FFFF
msp430afe233,0,0,2,1,EMEX_LOW,2,STANDARD,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,E000,FFDF,0,0,,,FFE0,FFFF
msp430afe253,0,0,2,1,EMEX_LOW,2,STANDARD,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,C000,FFDF,0,0,,,FFE0,FFFF
msp430g2102,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,FC00,FFDF,0,0,,,FFE0,FFFF
msp430g2202,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F800,FFDF,0,0,,,FFE0,FFFF
msp430g2302,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F000,FFDF,0,0,,,FFE0,FFFF
msp430g2402,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,E000,FFDF,0,0,,,FFE0,FFFF
msp430g2132,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,FC00,FFDF,0,0,,,FFE0,FFFF
msp430g2232,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F800,FFDF,0,0,,,FFE0,FFFF
msp430g2332,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F000,FFDF,0,0,,,FFE0,FFFF
msp430g2432,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,E000,FFDF,0,0,,,FFE0,FFFF
msp430g2112,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,FC00,FFDF,0,0,,,FFE0,FFFF
msp430g2212,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F800,FFDF,0,0,,,FFE0,FFFF
msp430g2312,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F000,FFDF,0,0,,,FFE0,FFFF
msp430g2412,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,E000,FFDF,0,0,,,FFE0,FFFF
msp430g2152,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,FC00,FFDF,0,0,,,FFE0,FFFF
msp430g2252,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F800,FFDF,0,0,,,FFE0,FFFF
msp430g2352,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F000,FFDF,0,0,,,FFE0,FFFF
msp430g2452,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,E000,FFDF,0,0,,,FFE0,FFFF
msp430g2113,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,FC00,FFDD,0,0,FFDE,2,FFE0,FFFF
msp430g2213,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F800,FFDD,0,0,FFDE,2,FFE0,FFFF
msp430g2313,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F000,FFDD,0,0,FFDE,2,FFE0,FFFF
msp430g2413,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,E000,FFDD,0,0,FFDE,2,FFE0,FFFF
msp430g2513,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,C000,FFDD,0,0,FFDE,2,FFE0,FFFF
msp430g2153,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,FC00,FFDD,0,0,FFDE,2,FFE0,FFFF
msp430g2253,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F800,FFDD,0,0,FFDE,2,FFE0,FFFF
msp430g2353,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F000,FFDD,0,0,FFDE,2,FFE0,FFFF
msp430g2453,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,E000,FFDD,0,0,FFDE,2,FFE0,FFFF
msp430g2553,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,C000,FFDD,0,0,FFDE,2,FFE0,FFFF
msp430g2203,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F800,FFDD,0,0,FFDE,2,FFE0,FFFF
msp430g2303,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F000,FFDD,0,0,FFDE,2,FFE0,FFFF
msp430g2403,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,E000,FFDD,0,0,FFDE,2,FFE0,FFFF
msp430g2233,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F800,FFDD,0,0,FFDE,2,FFE0,FFFF
msp430g2333,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,02FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F000,FFDD,0,0,FFDE,2,FFE0,FFFF
msp430g2433,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,E000,FFDD,0,0,FFDE,2,FFE0,FFFF
msp430g2533,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,C000,FFDD,0,0,FFDE,2,FFE0,FFFF
msp430tch5e,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,C000,FFDD,0,0,FFDE,2,FFE0,FFFF
msp430g2444,0,CPU19,0,1,EMEX_LOW,2,STANDARD,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,E000,FFDD,0,0,FFDE,2,FFE0,FFFF
msp430g2544,0,CPU19,0,1,EMEX_LOW,2,STANDARD,0,80,200,03FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,C000,FFDD,0,0,FFDE,2,FFE0,FFFF
msp430g2744,0,CPU19,0,1,EMEX_LOW,2,STANDARD,0,80,200,05FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,8000,FFDD,0,0,FFDE,2,FFE0,FFFF
msp430g2755,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,1100,20FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,40,10FF,10C0,1080,1040,1000,8000,FFDD,0,0,FFDE,2,FFE0,FFFF
msp430g2855,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,1100,20FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,40,10FF,10C0,1080,1040,1000,4000,FFDD,0,0,FFDE,2,FFE0,FFFF
msp430g2955,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,1100,20FF,0,0,0,0,0,0,0,0,1100,200,9FF,0,0,0,1000,40,10FF,10C0,1080,1040,1000,2100,FFDD,0,0,FFDE,2,FFE0,FFFF
msp430g2230,0,0,0,1,EMEX_LOW,2,STANDARD,0,50,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F800,FFDF,0,0,,,FFE0,FFFF
msp430g2210,0,0,0,1,EMEX_LOW,2,STANDARD,0,50,200,027F,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,F800,FFDF,0,0,,,FFE0,FFFF
msp430bt5190,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,5C00,FF7F,10000,45BFF,,,FF80,FFFF
msp430fr5857,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,FF80,10,FF90,FFFF
msp430fr5858,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,0,0,FF80,10,FF90,FFFF
msp430fr5859,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF
msp430fr5847,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,FF80,10,FF90,FFFF
msp430fr58471,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,FF80,10,FF90,FFFF
msp430fr5848,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,0,0,FF80,10,FF90,FFFF
msp430fr5849,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF
msp430fr5867,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,FF80,10,FF90,FFFF
msp430fr58671,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,FF80,10,FF90,FFFF
msp430fr5868,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,0,0,FF80,10,FF90,FFFF
msp430fr5869,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF
msp430fr5957,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,FF80,10,FF90,FFFF
msp430fr5958,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,0,0,FF80,10,FF90,FFFF
msp430fr5959,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF
msp430fr5947,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,FF80,10,FF90,FFFF
msp430fr59471,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,FF80,10,FF90,FFFF
msp430fr5948,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,0,0,FF80,10,FF90,FFFF
msp430fr5949,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF
msp430fr5967,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,FF80,10,FF90,FFFF
msp430fr5968,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,0,0,FF80,10,FF90,FFFF
msp430fr5969,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF
msp430fr59691,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF
msp430i2020,0,0,2,1,EMEX_LOW,2,STANDARD,0,80,200,05FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,400,13FF,1000,0,0,0,C000,FFDB,0,0,FFDC,4,FFE0,FFFF
msp430i2021,0,0,2,1,EMEX_LOW,2,STANDARD,0,80,200,09FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,400,13FF,1000,0,0,0,8000,FFDB,0,0,FFDC,4,FFE0,FFFF
msp430i2030,0,0,2,1,EMEX_LOW,2,STANDARD,0,80,200,05FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,400,13FF,1000,0,0,0,C000,FFDB,0,0,FFDC,4,FFE0,FFFF
msp430i2031,0,0,2,1,EMEX_LOW,2,STANDARD,0,80,200,09FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,400,13FF,1000,0,0,0,8000,FFDB,0,0,FFDC,4,FFE0,FFFF
msp430i2040,0,0,2,1,EMEX_LOW,2,STANDARD,0,80,200,05FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,400,13FF,1000,0,0,0,C000,FFDB,0,0,FFDC,4,FFE0,FFFF
msp430i2041,0,0,2,1,EMEX_LOW,2,STANDARD,0,80,200,09FF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1000,400,13FF,1000,0,0,0,8000,FFDB,0,0,FFDC,4,FFE0,FFFF
rf430frl152h,0,CPU21; CPU22,0,0,EMEX_EXTRA_SMALL_5XX,2,EXTENDED,1,80,1C00,2BFF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,F840,FFCF,0,0,FFD0,6,FFE0,FFFF
rf430frl153h,0,CPU21; CPU22,0,0,EMEX_EXTRA_SMALL_5XX,2,EXTENDED,1,80,1C00,2BFF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,F840,FFCF,0,0,FFD0,6,FFE0,FFFF
rf430frl154h,0,CPU21; CPU22,0,0,EMEX_EXTRA_SMALL_5XX,2,EXTENDED,1,80,1C00,2BFF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,F840,FFCF,0,0,FFD0,6,FFE0,FFFF
rf430frl152h_rom,0,CPU21; CPU22,0,0,EMEX_EXTRA_SMALL_5XX,2,EXTENDED,1,80,1C00,1DFF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,F840,FFCF,0,0,FFD0,6,FFE0,FFFF
rf430frl153h_rom,0,CPU21; CPU22,0,0,EMEX_EXTRA_SMALL_5XX,2,EXTENDED,1,80,1C00,1DFF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,F840,FFCF,0,0,FFD0,6,FFE0,FFFF
rf430frl154h_rom,0,CPU21; CPU22,0,0,EMEX_EXTRA_SMALL_5XX,2,EXTENDED,1,80,1C00,1DFF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,F840,FFCF,0,0,FFD0,6,FFE0,FFFF
rf430f5175,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,,,FF80,FFFF
rf430f5155,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,0,0,,,FF80,FFFF
rf430f5144,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,80,1C00,1FFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,C000,FF7F,0,0,,,FF80,FFFF
msp430fr69271,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF
msp430fr68791,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,23FFF,FF80,10,FF90,FFFF
msp430fr69791,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,23FFF,FF80,10,FF90,FFFF
msp430fr6927,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF
msp430fr6928,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,1BFFF,FF80,10,FF90,FFFF
msp430fr6877,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF
msp430fr6977,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF
msp430fr6879,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,23FFF,FF80,10,FF90,FFFF
msp430fr6979,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,23FFF,FF80,10,FF90,FFFF
msp430fr58891,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,23FFF,FF80,10,FF90,FFFF
msp430fr68891,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,23FFF,FF80,10,FF90,FFFF
msp430fr59891,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,23FFF,FF80,10,FF90,FFFF
msp430fr69891,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,23FFF,FF80,10,FF90,FFFF
msp430fr5887,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF
msp430fr5888,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,1BFFF,FF80,10,FF90,FFFF
msp430fr5889,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,23FFF,FF80,10,FF90,FFFF
msp430fr6887,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF
msp430fr6888,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,1BFFF,FF80,10,FF90,FFFF
msp430fr6889,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,23FFF,FF80,10,FF90,FFFF
msp430fr5986,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,0,0,FF80,10,FF90,FFFF
msp430fr5987,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF
msp430fr5988,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,1BFFF,FF80,10,FF90,FFFF
msp430fr5989,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,23FFF,FF80,10,FF90,FFFF
msp430fr6987,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF
msp430fr6988,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,1BFFF,FF80,10,FF90,FFFF
msp430fr6989,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,23FFF,FF80,10,FF90,FFFF
msp430fr5922,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF
msp430fr5870,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,FF80,10,FF90,FFFF
msp430fr5970,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,FF80,10,FF90,FFFF
msp430fr5872,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF
msp430fr5972,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF
msp430fr6820,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,FF80,10,FF90,FFFF
msp430fr6920,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,FF80,10,FF90,FFFF
msp430fr6822,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF
msp430fr6922,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF
msp430fr6870,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,FF80,10,FF90,FFFF
msp430fr6970,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,8000,FF7F,0,0,FF80,10,FF90,FFFF
msp430fr6872,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF
msp430fr6972,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF
msp430fr59221,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF
msp430fr58721,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF
msp430fr59721,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF
msp430fr68221,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF
msp430fr69221,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF
msp430fr68721,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF
msp430fr69721,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,23FF,0,0,6,001F,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,4400,FF7F,10000,13FFF,FF80,10,FF90,FFFF
msp430sl5438a,2,CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40,8,2,EMEX_LARGE_5XX,8,EXTENDED,2,160,1C00,5BFF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,5C00,FF7F,10000,45BFF,,,FF80,FFFF
msp430fr4131,2,CPU21; CPU22; CPU40,0,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2000,21FF,0,0,0,0,0,0,0,0,0,0,0,1000,400,13FF,1800,200,19FF,1800,0,0,0,F000,FF7F,0,0,FF80,8,FF88,FFFF
msp430fr4132,2,CPU21; CPU22; CPU40,0,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2000,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,400,13FF,1800,200,19FF,1800,0,0,0,E000,FF7F,0,0,FF80,8,FF88,FFFF
msp430fr4133,2,CPU21; CPU22; CPU40,0,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2000,27FF,0,0,0,0,0,0,0,0,0,0,0,1000,400,13FF,1800,200,19FF,1800,0,0,0,C400,FF7F,0,0,FF80,8,FF88,FFFF
msp430fr2032,2,CPU21; CPU22; CPU40,0,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2000,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,400,13FF,1800,200,19FF,1800,0,0,0,E000,FF7F,0,0,FF80,8,FF88,FFFF
msp430fr2033,2,CPU21; CPU22; CPU40,0,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2000,27FF,0,0,0,0,0,0,0,0,0,0,0,1000,400,13FF,1800,200,19FF,1800,0,0,0,C400,FF7F,0,0,FF80,8,FF88,FFFF
msp430fr2110,2,CPU21; CPU22; CPU40,0,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2000,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,400,13FF,0,0,0,0,0,0,0,F800,FF7F,0,0,FF80,8,FF88,FFFF
msp430fr2111,2,CPU21; CPU22; CPU40,0,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2000,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,400,13FF,0,0,0,0,0,0,0,F100,FF7F,0,0,FF80,8,FF88,FFFF
msp430fr2310,2,CPU21; CPU22; CPU40,0,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2000,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,800,17FF,0,0,0,0,0,0,0,F800,FF7F,0,0,FF80,8,FF88,FFFF
msp430fr2311,2,CPU21; CPU22; CPU40,0,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2000,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,800,17FF,0,0,0,0,0,0,0,F100,FF7F,0,0,FF80,8,FF88,FFFF
msp430fr2433,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2000,2FFF,0,0,0,0,0,0,0,0,0,0,0,1000,800,17FF,1800,200,19FF,1800,0,0,0,C400,FF7F,0,0,FF80,8,FF88,FFFF
msp430fr2532,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2000,23FF,0,0,0,0,0,0,0,0,0,0,0,1000,800,17FF,1800,200,19FF,1800,0,0,0,E000,FF7F,0,0,FF80,8,FF88,FFFF
msp430fr2533,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2000,27FF,0,0,0,0,0,0,0,0,0,0,0,1000,800,17FF,1800,200,19FF,1800,0,0,0,C400,FF7F,0,0,FF80,8,FF88,FFFF
msp430fr2632,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2000,27FF,0,0,0,0,0,0,0,0,0,0,0,1000,800,17FF,1800,200,19FF,1800,0,0,0,E000,FF7F,0,0,FF80,8,FF88,FFFF
msp430fr2633,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2000,2FFF,0,0,0,0,0,0,0,0,0,0,0,1000,800,17FF,1800,200,19FF,1800,0,0,0,C400,FF7F,0,0,FF80,8,FF88,FFFF
msp430f5252,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,63FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,A400,FF7F,10000,2A3FF,,,FF80,FFFF
msp430f5253,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,63FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,A400,FF7F,10000,2A3FF,,,FF80,FFFF
msp430f5254,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,A3FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,A400,FF7F,10000,2A3FF,,,FF80,FFFF
msp430f5255,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,A3FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,A400,FF7F,10000,2A3FF,,,FF80,FFFF
msp430f5256,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,63FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,A400,FF7F,10000,2A3FF,,,FF80,FFFF
msp430f5257,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,63FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,A400,FF7F,10000,2A3FF,,,FF80,FFFF
msp430f5258,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,A3FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,A400,FF7F,10000,2A3FF,,,FF80,FFFF
msp430f5259,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2400,A3FF,0,0,0,0,0,0,0,0,0,0,0,1000,200,17FF,1800,80,19FF,1980,1900,1880,1800,A400,FF7F,10000,2A3FF,,,FF80,FFFF
msp430fr5962,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,3BFF,0,0,A,001F,0,0,0,0,0,0,0,1000,800,17FF,1800,200,19FF,1980,1900,1880,1800,4000,FF7F,10000,23FFF,FF80,10,FF90,FFFF
msp430fr5964,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,3BFF,0,0,A,001F,0,0,0,0,0,0,0,1000,800,17FF,1800,200,19FF,1980,1900,1880,1800,4000,FF7F,10000,43FFF,FF80,10,FF90,FFFF
msp430fr5992,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,2BFF,0,0,A,001F,0,0,2C00,3BFF,0,0,0,1000,800,17FF,1800,200,19FF,1980,1900,1880,1800,4000,FF7F,10000,23FFF,FF80,10,FF90,FFFF
msp430fr5994,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,2BFF,0,0,A,001F,0,0,2C00,3BFF,0,0,0,1000,800,17FF,1800,200,19FF,1980,1900,1880,1800,4000,FF7F,10000,43FFF,FF80,10,FF90,FFFF
msp430fr59941,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,2BFF,0,0,A,001F,0,0,2C00,3BFF,0,0,0,1000,800,17FF,1800,200,19FF,1980,1900,1880,1800,4000,FF7F,10000,43FFF,FF80,10,FF90,FFFF
msp430fr2100,2,CPU21; CPU22; CPU40,0,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2000,21FF,0,0,0,0,0,0,0,0,0,0,0,1000,400,13FF,0,0,0,0,0,0,0,FC00,FF7F,0,0,FF80,8,FF88,FFFF
msp430fr2000,2,CPU21; CPU22; CPU40,0,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2000,21FF,0,0,0,0,0,0,0,0,0,0,0,1000,400,13FF,0,0,0,0,0,0,0,FE00,FF7F,0,0,FF80,8,FF88,FFFF
msp430fr2355,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2000,2FFF,0,0,6,001F,0,0,0,0,0,0,0,1000,800,17FF,1800,200,19FF,0,0,0,0,8000,FF7F,0,0,FF80,22,FFA2,FFFF
msp430fr2155,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2000,2FFF,0,0,6,001F,0,0,0,0,0,0,0,1000,800,17FF,1800,200,19FF,0,0,0,0,8000,FF7F,0,0,FF80,22,FFA2,FFFF
msp430fr2353,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2000,27FF,0,0,6,001F,0,0,0,0,0,0,0,1000,800,17FF,1800,200,19FF,0,0,0,0,C000,FF7F,0,0,FF80,22,FFA2,FFFF
msp430fr2153,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2000,27FF,0,0,6,001F,0,0,0,0,0,0,0,1000,800,17FF,1800,200,19FF,0,0,0,0,C000,FF7F,0,0,FF80,22,FFA2,FFFF
msp430fr2522,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2000,27FF,0,0,0,0,0,0,0,0,0,0,0,1000,800,17FF,1800,100,18FF,0,0,0,0,E300,FF7F,0,0,FF80,8,FF88,FFFF
msp430fr2512,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2000,27FF,0,0,0,0,0,0,0,0,0,0,0,1000,800,17FF,1800,100,18FF,0,0,0,0,E300,FF7F,0,0,FF80,8,FF88,FFFF
msp430fr2422,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2000,27FF,0,0,0,0,0,0,0,0,0,0,0,1000,800,17FF,1800,100,18FF,0,0,0,0,E300,FF7F,0,0,FF80,8,FF88,FFFF
msp430fr2676,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2000,3FFF,0,0,6,001F,0,0,0,0,0,0,0,1000,800,17FF,1800,200,19FF,0,0,0,0,8000,FF7F,10000,17FFF,FF80,22,FFA2,FFFF
msp430fr2476,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2000,3FFF,0,0,6,001F,0,0,0,0,0,0,0,1000,800,17FF,1800,200,19FF,0,0,0,0,8000,FF7F,10000,17FFF,FF80,22,FFA2,FFFF
msp430fr2675,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2000,37FF,0,0,6,001F,0,0,0,0,0,0,0,1000,800,17FF,1800,200,19FF,0,0,0,0,8000,FF7F,0,0,FF80,22,FFA2,FFFF
msp430fr2673,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2000,2FFF,0,0,6,001F,0,0,0,0,0,0,0,1000,800,17FF,1800,200,19FF,0,0,0,0,C000,FF7F,0,0,FF80,22,FFA2,FFFF
msp430fr2475,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2000,2FFF,0,0,6,001F,0,0,0,0,0,0,0,1000,800,17FF,1800,200,19FF,0,0,0,0,8000,FF7F,0,0,FF80,22,FFA2,FFFF
msp430fr2672,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,2000,27FF,0,0,6,001F,0,0,0,0,0,0,0,1000,800,17FF,1800,200,19FF,0,0,0,0,E000,FF7F,0,0,FF80,22,FFA2,FFFF
msp430fr6043,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,2BFF,0,0,A,001F,0,0,5000,5FFF,0,0,0,1000,800,17FF,0,0,0,0,0,0,0,6000,FF7F,10000,15FFF,FF80,10,FF90,FFFF
msp430fr5043,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,2BFF,0,0,A,001F,0,0,5000,5FFF,0,0,0,1000,800,17FF,0,0,0,0,0,0,0,6000,FF7F,10000,15FFF,FF80,10,FF90,FFFF
msp430fr6041,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,2BFF,0,0,A,001F,0,0,5000,5FFF,0,0,0,1000,800,17FF,0,0,0,0,0,0,0,8000,FF7F,0,0,FF80,10,FF90,FFFF
msp430fr60431,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,2BFF,0,0,A,001F,0,0,5000,5FFF,0,0,0,1000,800,17FF,0,0,0,0,0,0,0,6000,FF7F,10000,15FFF,FF80,10,FF90,FFFF
msp430fr5041,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,2BFF,0,0,A,001F,0,0,5000,5FFF,0,0,0,1000,800,17FF,0,0,0,0,0,0,0,8000,FF7F,0,0,FF80,10,FF90,FFFF
msp430fr50431,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,2BFF,0,0,A,001F,0,0,5000,5FFF,0,0,0,1000,800,17FF,0,0,0,0,0,0,0,6000,FF7F,10000,15FFF,FF80,10,FF90,FFFF
msp430fr6005,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,2BFF,0,0,A,001F,0,0,2C00,3BFF,0,0,0,1000,800,17FF,0,0,0,0,0,0,0,4000,FF7F,10000,23FFF,FF80,10,FF90,FFFF
msp430fr6047,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,2BFF,0,0,A,001F,0,0,2C00,3BFF,0,0,0,1000,800,17FF,0,0,0,0,0,0,0,4000,FF7F,10000,43FFF,FF80,10,FF90,FFFF
msp430fr6037,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,2BFF,0,0,A,001F,0,0,2C00,3BFF,0,0,0,1000,800,17FF,0,0,0,0,0,0,0,4000,FF7F,10000,43FFF,FF80,10,FF90,FFFF
msp430fr6045,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,2BFF,0,0,A,001F,0,0,2C00,3BFF,0,0,0,1000,800,17FF,0,0,0,0,0,0,0,4000,FF7F,10000,23FFF,FF80,10,FF90,FFFF
msp430fr60471,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,2BFF,0,0,A,001F,0,0,2C00,3BFF,0,0,0,1000,800,17FF,0,0,0,0,0,0,0,4000,FF7F,10000,43FFF,FF80,10,FF90,FFFF
msp430fr6035,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,2BFF,0,0,A,001F,0,0,2C00,3BFF,0,0,0,1000,800,17FF,0,0,0,0,0,0,0,4000,FF7F,10000,23FFF,FF80,10,FF90,FFFF
msp430fr6007,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,2BFF,0,0,A,001F,0,0,2C00,3BFF,0,0,0,1000,800,17FF,0,0,0,0,0,0,0,4000,FF7F,10000,43FFF,FF80,10,FF90,FFFF
msp430fr60371,2,CPU21; CPU22; CPU40,8,2,EMEX_SMALL_5XX,3,EXTENDED,1,160,1C00,2BFF,0,0,A,001F,0,0,2C00,3BFF,0,0,0,1000,800,17FF,0,0,0,0,0,0,0,4000,FF7F,10000,43FFF,FF80,10,FF90,FFFF
1 # /* ============================================================================ */
2 # /* Copyright (c) 2016 Texas Instruments Incorporated */
3 # /* All rights reserved. */
4 # /* */
5 # /* Redistribution and use in source and binary forms with or without */
6 # /* modification are permitted provided that the following conditions */
7 # /* are met: */
8 # /* */
9 # /* * Redistributions of source code must retain the above copyright */
10 # /* notice this list of conditions and the following disclaimer. */
11 # /* */
12 # /* * Redistributions in binary form must reproduce the above copyright */
13 # /* notice this list of conditions and the following disclaimer in the */
14 # /* documentation and/or other materials provided with the distribution. */
15 # /* */
16 # /* * Neither the name of Texas Instruments Incorporated nor the names of */
17 # /* its contributors may be used to endorse or promote products derived */
18 # /* from this software without specific prior written permission. */
19 # /* */
20 # /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */
21 # /* AND ANY EXPRESS OR IMPLIED WARRANTIES INCLUDING BUT NOT LIMITED TO */
22 # /* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */
23 # /* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */
24 # /* CONTRIBUTORS BE LIABLE FOR ANY DIRECT INDIRECT INCIDENTAL SPECIAL */
25 # /* EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO */
26 # /* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE DATA OR PROFITS; */
27 # /* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY */
28 # /* WHETHER IN CONTRACT STRICT LIABILITY OR TORT (INCLUDING NEGLIGENCE OR */
29 # /* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE */
30 # /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
31 # /* ============================================================================ */
32
33 Version: 1.21 Date: 5/14/2020 14:14:02
34
35 # ============================================================================
36 # CPU
37 # 0 STD MSP430 CPU
38 # 1 MSP430X CPU
39 # 2 MSP430XV2 CPU
40 #
41 #
42 # HWMPY
43 # 0 No Hardware Multiplier
44 # 1 16 Bit Hardware Multiplier
45 # 2 16 Bit Hardware Multiplier with sign Extension (2xx Devices)
46 #
47 # 4 32 Bit Hardware Multiplier
48 # 8 32 Bit Hardware Multiplier (5xx)
49 #
50 #
51 # SPI2Wire
52 # 0 JTAG only - no scan
53 # 1 SBW (default) - scan allowed
54 # 2 JTAG (Default) - scan allowed
55 # 3 SBW only - no scan
56 # ============================================================================
57
58
59 # Device Name CPU_TYPE CPU_Bugs MPY_TYPE SBW EEM BREAKPOINTS CLOCKCONTROL CYCLECOUNTER STACKSIZE RAMStart RAMEnd RAMStart2 RAMEnd2 TINYRAMStart TINYRAMEnd USBRAMStart USBRAMEnd LEARAMStart LEARAMEnd MirrowedRAMSource MirrowedRAMStart MirrowedRAMEnd BSLStart BSLSize BSLEnd INFOStart INFOSize INFOEnd INFOA INFOB INFOC INFOD FStart FEnd FStart2 FEnd2 Signature_Start Signature_Size INTStart INTEnd
60 msp430c111 0 0 0 0 NONE 0 NONE 0 50 200 027F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F800 FFDF 0 0 FFE0 FFFF
61 msp430c1111 0 0 0 0 NONE 0 NONE 0 50 200 027F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F800 FFDF 0 0 FFE0 FFFF
62 msp430c112 0 0 0 0 NONE 0 NONE 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F000 FFDF 0 0 FFE0 FFFF
63 msp430c1121 0 0 0 0 NONE 0 NONE 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F000 FFDF 0 0 FFE0 FFFF
64 msp430c1331 0 0 0 0 NONE 0 NONE 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 E000 FFDF 0 0 FFE0 FFFF
65 msp430c1351 0 0 0 0 NONE 0 NONE 0 80 200 03FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C000 FFDF 0 0 FFE0 FFFF
66 msp430c311s 0 0 0 0 NONE 0 NONE 0 50 200 027F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F800 FFDF 0 0 FFE0 FFFF
67 msp430c312 0 0 0 0 NONE 0 NONE 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F000 FFDF 0 0 FFE0 FFFF
68 msp430c313 0 0 0 0 NONE 0 NONE 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 E000 FFDF 0 0 FFE0 FFFF
69 msp430c314 0 0 0 0 NONE 0 NONE 0 80 200 03FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D000 FFDF 0 0 FFE0 FFFF
70 msp430c315 0 0 0 0 NONE 0 NONE 0 80 200 03FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C000 FFDF 0 0 FFE0 FFFF
71 msp430c323 0 0 0 0 NONE 0 NONE 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 E000 FFDF 0 0 FFE0 FFFF
72 msp430c325 0 0 0 0 NONE 0 NONE 0 80 200 03FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C000 FFDF 0 0 FFE0 FFFF
73 msp430c336 0 0 1 0 NONE 0 NONE 0 80 200 05FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A000 FFDF 0 0 FFE0 FFFF
74 msp430c337 0 0 1 0 NONE 0 NONE 0 80 200 05FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8000 FFDF 0 0 FFE0 FFFF
75 msp430c412 0 0 0 0 NONE 0 NONE 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F000 FFDF 0 0 FFE0 FFFF
76 msp430c413 0 0 0 0 NONE 0 NONE 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 E000 FFDF 0 0 FFE0 FFFF
77 msp430cg4616 1 CPU16; CPU19 1 0 NONE 0 NONE 0 80 1100 20FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 80 10FF 1080 1000 0 0 2100 FFBF 10000 18FFF FFC0 FFFF
78 msp430cg4617 1 CPU16; CPU19 1 0 NONE 0 NONE 0 80 1100 30FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 80 10FF 1080 1000 0 0 3100 FFBF 10000 19FFF FFC0 FFFF
79 msp430cg4618 1 CPU16; CPU19 1 0 NONE 0 NONE 0 80 1100 30FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 80 10FF 1080 1000 0 0 3100 FFBF 10000 1FFFF FFC0 FFFF
80 msp430cg4619 1 CPU16; CPU19 1 0 NONE 0 NONE 0 80 1100 20FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 80 10FF 1080 1000 0 0 2100 FFBF 10000 1FFFF FFC0 FFFF
81 msp430e112 0 0 0 0 NONE 0 NONE 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F000 FFDF 0 0 FFE0 FFFF
82 msp430e313 0 0 0 0 NONE 0 NONE 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 E000 FFDF 0 0 FFE0 FFFF
83 msp430e315 0 0 0 0 NONE 0 NONE 0 80 200 03FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C000 FFDF 0 0 FFE0 FFFF
84 msp430e325 0 0 0 0 NONE 0 NONE 0 80 200 03FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C000 FFDF 0 0 FFE0 FFFF
85 msp430e337 0 0 1 0 NONE 0 NONE 0 80 200 05FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8000 FFDF 0 0 FFE0 FFFF
86 msp430f110 0 0 0 0 EMEX_LOW 2 NONE 0 50 200 027F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1080 80 10FF 1080 0 0 0 FC00 FFDF 0 0 FFE0 FFFF
87 msp430f1101 0 0 0 0 EMEX_LOW 2 NONE 0 50 200 027F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1080 80 10FF 1080 0 0 0 FC00 FFDF 0 0 FFE0 FFFF
88 msp430f1101a 0 0 0 0 EMEX_LOW 2 NONE 0 50 200 027F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1080 80 10FF 1080 0 0 0 FC00 FFDF 0 0 FFE0 FFFF
89 msp430f1111 0 0 0 0 EMEX_LOW 2 NONE 0 50 200 027F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 F800 FFDF 0 0 FFE0 FFFF
90 msp430f1111a 0 0 0 0 EMEX_LOW 2 NONE 0 50 200 027F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 F800 FFDF 0 0 FFE0 FFFF
91 msp430f112 0 0 0 0 EMEX_LOW 2 NONE 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 F000 FFDF 0 0 FFE0 FFFF
92 msp430f1121 0 0 0 0 EMEX_LOW 2 NONE 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 F000 FFDF 0 0 FFE0 FFFF
93 msp430f1121a 0 0 0 0 EMEX_LOW 2 NONE 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 F000 FFDF 0 0 FFE0 FFFF
94 msp430f1122 0 0 0 0 EMEX_LOW 2 NONE 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 F000 FFDF 0 0 FFE0 FFFF
95 msp430f1132 0 0 0 0 EMEX_LOW 2 NONE 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 E000 FFDF 0 0 FFE0 FFFF
96 msp430f122 0 0 0 0 EMEX_LOW 2 NONE 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 F000 FFDF 0 0 FFE0 FFFF
97 msp430f1222 0 0 0 0 EMEX_LOW 2 NONE 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 F000 FFDF 0 0 FFE0 FFFF
98 msp430f123 0 0 0 0 EMEX_LOW 2 NONE 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 E000 FFDF 0 0 FFE0 FFFF
99 msp430f1232 0 0 0 0 EMEX_LOW 2 NONE 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 E000 FFDF 0 0 FFE0 FFFF
100 msp430f133 0 0 0 0 EMEX_MEDIUM 3 NONE 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 E000 FFDF 0 0 FFE0 FFFF
101 msp430f135 0 0 0 0 EMEX_MEDIUM 3 NONE 0 80 200 03FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 C000 FFDF 0 0 FFE0 FFFF
102 msp430f147 0 0 1 0 EMEX_MEDIUM 3 NONE 0 80 200 05FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 8000 FFDF 0 0 FFE0 FFFF
103 msp430f148 0 0 1 0 EMEX_MEDIUM 3 NONE 0 80 200 09FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 4000 FFDF 0 0 FFE0 FFFF
104 msp430f149 0 0 1 0 EMEX_MEDIUM 3 NONE 0 80 200 09FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 1100 FFDF 0 0 FFE0 FFFF
105 msp430f1471 0 0 1 0 EMEX_MEDIUM 3 NONE 0 80 200 05FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 8000 FFDF 0 0 FFE0 FFFF
106 msp430f1481 0 0 1 0 EMEX_MEDIUM 3 NONE 0 80 200 09FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 4000 FFDF 0 0 FFE0 FFFF
107 msp430f1491 0 0 1 0 EMEX_MEDIUM 3 NONE 0 80 200 09FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 1100 FFDF 0 0 FFE0 FFFF
108 msp430f155 0 0 0 0 EMEX_HIGH 8 EXTENDED 0 80 200 03FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 C000 FFDF 0 0 FFE0 FFFF
109 msp430f156 0 0 0 0 EMEX_HIGH 8 EXTENDED 0 80 200 05FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 A000 FFDF 0 0 FFE0 FFFF
110 msp430f157 0 0 0 0 EMEX_HIGH 8 EXTENDED 0 80 200 05FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 8000 FFDF 0 0 FFE0 FFFF
111 msp430f167 0 0 1 0 EMEX_HIGH 8 EXTENDED 0 80 200 05FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 8000 FFDF 0 0 FFE0 FFFF
112 msp430f168 0 0 1 0 EMEX_HIGH 8 EXTENDED 0 80 200 09FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 4000 FFDF 0 0 FFE0 FFFF
113 msp430f169 0 0 1 0 EMEX_HIGH 8 EXTENDED 0 80 200 09FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 1100 FFDF 0 0 FFE0 FFFF
114 msp430f1610 0 0 1 0 EMEX_HIGH 8 EXTENDED 0 80 1100 24FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 80 10FF 1080 1000 0 0 8000 FFDF 0 0 FFE0 FFFF
115 msp430f1611 0 0 1 0 EMEX_HIGH 8 EXTENDED 0 80 1100 38FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 80 10FF 1080 1000 0 0 4000 FFDF 0 0 FFE0 FFFF
116 msp430f1612 0 0 1 0 EMEX_HIGH 8 EXTENDED 0 80 1100 24FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 80 10FF 1080 1000 0 0 2500 FFDF 0 0 FFE0 FFFF
117 msp430f2001 0 0 0 1 EMEX_LOW 2 STANDARD 0 50 200 027F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 FC00 FFDF 0 0 FFE0 FFFF
118 msp430f2011 0 0 0 1 EMEX_LOW 2 STANDARD 0 50 200 027F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 F800 FFDF 0 0 FFE0 FFFF
119 msp430f2002 0 0 0 1 EMEX_LOW 2 STANDARD 0 50 200 027F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 FC00 FFDF 0 0 FFE0 FFFF
120 msp430f2012 0 0 0 1 EMEX_LOW 2 STANDARD 0 50 200 027F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 F800 FFDF 0 0 FFE0 FFFF
121 msp430f2003 0 0 0 1 EMEX_LOW 2 STANDARD 0 50 200 027F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 FC00 FFDF 0 0 FFE0 FFFF
122 msp430f2013 0 0 0 1 EMEX_LOW 2 STANDARD 0 50 200 027F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 F800 FFDF 0 0 FFE0 FFFF
123 msp430f2101 0 CPU19 0 0 EMEX_LOW 2 STANDARD 0 50 200 027F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 FC00 FFDD 0 0 FFDE 2 FFE0 FFFF
124 msp430f2111 0 CPU19 0 0 EMEX_LOW 2 STANDARD 0 50 200 027F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 F800 FFDD 0 0 FFDE 2 FFE0 FFFF
125 msp430f2121 0 CPU19 0 0 EMEX_LOW 2 STANDARD 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 F000 FFDD 0 0 FFDE 2 FFE0 FFFF
126 msp430f2131 0 CPU19 0 0 EMEX_LOW 2 STANDARD 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 E000 FFDD 0 0 FFDE 2 FFE0 FFFF
127 msp430f2112 0 CPU19 0 1 EMEX_LOW 2 STANDARD 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 F800 FFDD 0 0 FFDE 2 FFE0 FFFF
128 msp430f2122 0 CPU19 0 1 EMEX_LOW 2 STANDARD 0 80 200 03FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 F000 FFDD 0 0 FFDE 2 FFE0 FFFF
129 msp430f2132 0 CPU19 0 1 EMEX_LOW 2 STANDARD 0 80 200 03FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 E000 FFDD 0 0 FFDE 2 FFE0 FFFF
130 msp430f2232 0 CPU19 0 1 EMEX_LOW 2 STANDARD 0 80 200 03FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 E000 FFDD 0 0 FFDE 2 FFE0 FFFF
131 msp430f2252 0 CPU19 0 1 EMEX_LOW 2 STANDARD 0 80 200 03FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 C000 FFDD 0 0 FFDE 2 FFE0 FFFF
132 msp430f2272 0 CPU19 0 1 EMEX_LOW 2 STANDARD 0 80 200 05FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 8000 FFDD 0 0 FFDE 2 FFE0 FFFF
133 msp430f2234 0 CPU19 0 1 EMEX_LOW 2 STANDARD 0 80 200 03FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 E000 FFDD 0 0 FFDE 2 FFE0 FFFF
134 msp430f2254 0 CPU19 0 1 EMEX_LOW 2 STANDARD 0 80 200 03FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 C000 FFDD 0 0 FFDE 2 FFE0 FFFF
135 msp430f2274 0 CPU19 0 1 EMEX_LOW 2 STANDARD 0 80 200 05FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 8000 FFDD 0 0 FFDE 2 FFE0 FFFF
136 msp430f2330 0 CPU19 2 0 EMEX_LOW 2 STANDARD 0 80 200 05FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 E000 FFDD 0 0 FFDE 2 FFE0 FFFF
137 msp430f2350 0 CPU19 2 0 EMEX_LOW 2 STANDARD 0 80 200 09FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 C000 FFDD 0 0 FFDE 2 FFE0 FFFF
138 msp430f2370 0 CPU19 2 0 EMEX_LOW 2 STANDARD 0 80 200 09FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 8000 FFDD 0 0 FFDE 2 FFE0 FFFF
139 msp430f233 0 CPU19 2 0 EMEX_MEDIUM 3 EXTENDED 0 80 200 05FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 E000 FFDD 0 0 FFDE 2 FFE0 FFFF
140 msp430f235 0 CPU19 2 0 EMEX_MEDIUM 3 EXTENDED 0 80 200 09FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 C000 FFDD 0 0 FFDE 2 FFE0 FFFF
141 msp430f247 0 CPU19 2 0 EMEX_MEDIUM 3 EXTENDED 0 80 1100 20FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 40 10FF 10C0 1080 1040 1000 8000 FFBF 0 0 FFDE 2 FFC0 FFFF
142 msp430f248 0 CPU19 2 0 EMEX_MEDIUM 3 EXTENDED 0 80 1100 20FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 40 10FF 10C0 1080 1040 1000 4000 FFBF 0 0 FFDE 2 FFC0 FFFF
143 msp430f249 0 CPU19 2 0 EMEX_MEDIUM 3 EXTENDED 0 80 200 09FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 1100 FFBF 0 0 FFDE 2 FFC0 FFFF
144 msp430f2410 0 CPU19 2 0 EMEX_MEDIUM 3 EXTENDED 0 80 1100 20FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 40 10FF 10C0 1080 1040 1000 2100 FFBF 0 0 FFDE 2 FFC0 FFFF
145 msp430f2471 0 CPU19 2 0 EMEX_MEDIUM 3 EXTENDED 0 80 1100 20FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 40 10FF 10C0 1080 1040 1000 8000 FFBF 0 0 FFDE 2 FFC0 FFFF
146 msp430f2481 0 CPU19 2 0 EMEX_MEDIUM 3 EXTENDED 0 80 1100 20FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 40 10FF 10C0 1080 1040 1000 4000 FFBF 0 0 FFDE 2 FFC0 FFFF
147 msp430f2491 0 CPU19 2 0 EMEX_MEDIUM 3 EXTENDED 0 80 200 09FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 1100 FFBF 0 0 FFDE 2 FFC0 FFFF
148 msp430f2416 1 CPU16; CPU19 2 0 EMEX_HIGH 8 EXTENDED 0 80 1100 20FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 40 10FF 10C0 1080 1040 1000 2100 FFBD 10000 18FFF FFBE 2 FFC0 FFFF
149 msp430f2417 1 CPU16; CPU19 2 0 EMEX_HIGH 8 EXTENDED 0 80 1100 30FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 40 10FF 10C0 1080 1040 1000 3100 FFBD 10000 19FFF FFBE 2 FFC0 FFFF
150 msp430f2418 1 CPU16; CPU19 2 0 EMEX_HIGH 8 EXTENDED 0 80 1100 30FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 40 10FF 10C0 1080 1040 1000 3100 FFBD 10000 1FFFF FFBE 2 FFC0 FFFF
151 msp430f2419 1 CPU16; CPU19 2 0 EMEX_HIGH 8 EXTENDED 0 80 1100 20FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 40 10FF 10C0 1080 1040 1000 2100 FFBD 10000 1FFFF FFBE 2 FFC0 FFFF
152 msp430f2616 1 CPU16; CPU19 2 0 EMEX_HIGH 8 EXTENDED 0 80 1100 20FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 40 10FF 10C0 1080 1040 1000 2100 FFBD 10000 18FFF FFBE 2 FFC0 FFFF
153 msp430f2617 1 CPU16; CPU19 2 0 EMEX_HIGH 8 EXTENDED 0 80 1100 30FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 40 10FF 10C0 1080 1040 1000 3100 FFBD 10000 19FFF FFBE 2 FFC0 FFFF
154 msp430f2618 1 CPU16; CPU19 2 0 EMEX_HIGH 8 EXTENDED 0 80 1100 30FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 40 10FF 10C0 1080 1040 1000 3100 FFBD 10000 1FFFF FFBE 2 FFC0 FFFF
155 msp430f2619 1 CPU16; CPU19 2 0 EMEX_HIGH 8 EXTENDED 0 80 1100 20FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 40 10FF 10C0 1080 1040 1000 2100 FFBD 10000 1FFFF FFBE 2 FFC0 FFFF
156 msp430f412 0 0 0 0 EMEX_LOW 2 STANDARD 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 F000 FFBD 0 0 FFE0 FFFF
157 msp430f413 0 0 0 0 EMEX_LOW 2 STANDARD 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 E000 FFDF 0 0 FFE0 FFFF
158 msp430f415 0 0 0 0 EMEX_LOW 2 STANDARD 0 80 200 03FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 C000 FFDF 0 0 FFE0 FFFF
159 msp430f417 0 0 0 0 EMEX_LOW 2 STANDARD 0 80 200 05FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 8000 FFDF 0 0 FFE0 FFFF
160 msp430f4132 0 CPU19 0 1 EMEX_LOW 2 EXTENDED 0 80 200 03FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 E000 FFDF 0 0 FFE0 FFFF
161 msp430f4152 0 CPU19 0 1 EMEX_LOW 2 EXTENDED 0 80 200 03FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 C000 FFDF 0 0 FFE0 FFFF
162 msp430f423 0 0 1 0 EMEX_LOW 2 STANDARD 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 E000 FFDF 0 0 FFE0 FFFF
163 msp430f425 0 0 1 0 EMEX_LOW 2 STANDARD 0 80 200 03FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 C000 FFDF 0 0 FFE0 FFFF
164 msp430f427 0 0 1 0 EMEX_LOW 2 STANDARD 0 80 200 05FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 8000 FFDF 0 0 FFE0 FFFF
165 msp430f423a 0 0 1 0 EMEX_LOW 2 STANDARD 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 E000 FFDF 0 0 FFE0 FFFF
166 msp430f425a 0 0 1 0 EMEX_LOW 2 STANDARD 0 80 200 03FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 C000 FFDF 0 0 FFE0 FFFF
167 msp430f427a 0 0 1 0 EMEX_LOW 2 STANDARD 0 80 200 05FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 8000 FFDF 0 0 FFE0 FFFF
168 msp430f435 0 0 0 0 EMEX_HIGH 8 EXTENDED 0 80 200 03FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 C000 FFDF 0 0 FFE0 FFFF
169 msp430f436 0 0 0 0 EMEX_HIGH 8 EXTENDED 0 80 200 05FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 A000 FFDF 0 0 FFE0 FFFF
170 msp430f437 0 0 0 0 EMEX_HIGH 8 EXTENDED 0 80 200 05FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 8000 FFDF 0 0 FFE0 FFFF
171 msp430f4351 0 0 0 0 EMEX_HIGH 8 EXTENDED 0 80 200 03FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 C000 FFDF 0 0 FFE0 FFFF
172 msp430f4361 0 0 0 0 EMEX_HIGH 8 EXTENDED 0 80 200 05FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 A000 FFDF 0 0 FFE0 FFFF
173 msp430f4371 0 0 0 0 EMEX_HIGH 8 EXTENDED 0 80 200 05FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 8000 FFDF 0 0 FFE0 FFFF
174 msp430f4481 0 0 1 0 EMEX_HIGH 8 EXTENDED 0 80 200 09FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 4000 FFDF 0 0 FFE0 FFFF
175 msp430f4491 0 0 1 0 EMEX_HIGH 8 EXTENDED 0 80 200 09FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 1100 FFDF 0 0 FFE0 FFFF
176 msp430f447 0 0 1 0 EMEX_HIGH 8 EXTENDED 0 80 200 05FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 8000 FFDF 0 0 FFE0 FFFF
177 msp430f448 0 0 1 0 EMEX_HIGH 8 EXTENDED 0 80 200 09FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 4000 FFDF 0 0 FFE0 FFFF
178 msp430f449 0 0 1 0 EMEX_HIGH 8 EXTENDED 0 80 200 09FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 1100 FFDF 0 0 FFE0 FFFF
179 msp430fe423 0 0 0 0 EMEX_LOW 2 STANDARD 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 E000 FFDF 0 0 FFE0 FFFF
180 msp430fe425 0 0 0 0 EMEX_LOW 2 STANDARD 0 80 200 03FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 C000 FFDF 0 0 FFE0 FFFF
181 msp430fe427 0 0 0 0 EMEX_LOW 2 STANDARD 0 80 200 05FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 8000 FFDF 0 0 FFE0 FFFF
182 msp430fe423a 0 0 0 0 EMEX_LOW 2 STANDARD 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 E000 FFDF 0 0 FFE0 FFFF
183 msp430fe425a 0 0 0 0 EMEX_LOW 2 STANDARD 0 80 200 03FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 C000 FFDF 0 0 FFE0 FFFF
184 msp430fe427a 0 0 0 0 EMEX_LOW 2 STANDARD 0 80 200 05FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 8000 FFDF 0 0 FFE0 FFFF
185 msp430fe4232 0 0 0 0 EMEX_LOW 2 STANDARD 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 E000 FFDF 0 0 FFE0 FFFF
186 msp430fe4242 0 0 0 0 EMEX_LOW 2 STANDARD 0 80 200 03FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 D000 FFDF 0 0 FFE0 FFFF
187 msp430fe4252 0 0 0 0 EMEX_LOW 2 STANDARD 0 80 200 03FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 C000 FFDF 0 0 FFE0 FFFF
188 msp430fe4272 0 0 0 0 EMEX_LOW 2 STANDARD 0 80 200 05FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 8000 FFDF 0 0 FFE0 FFFF
189 msp430f4783 0 CPU19 4 0 EMEX_LOW 2 STANDARD 0 80 200 09FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 4000 FFDF 0 0 FFE0 FFFF
190 msp430f4793 0 CPU19 4 0 EMEX_LOW 2 STANDARD 0 80 200 0BFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 1100 FFDF 0 0 FFE0 FFFF
191 msp430f4784 0 CPU19 4 0 EMEX_LOW 2 STANDARD 0 80 200 09FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 4000 FFDF 0 0 FFE0 FFFF
192 msp430f4794 0 CPU19 4 0 EMEX_LOW 2 STANDARD 0 80 200 0BFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 1100 FFDF 0 0 FFE0 FFFF
193 msp430f47126 1 CPU19 4 0 EMEX_HIGH 8 EXTENDED 0 80 1100 20FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 40 10FF 10C0 1080 1040 1000 2100 FFBD 0 0 FFBE 2 FFC0 FFFF
194 msp430f47127 1 CPU19 4 0 EMEX_HIGH 8 EXTENDED 0 80 1100 20FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 40 10FF 10C0 1080 1040 1000 2100 FFBD 0 0 FFBE 2 FFC0 FFFF
195 msp430f47163 1 CPU19 4 0 EMEX_HIGH 8 EXTENDED 0 80 1100 20FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 40 10FF 10C0 1080 1040 1000 2100 FFBD 10000 18FFF FFBE 2 FFC0 FFFF
196 msp430f47173 1 CPU19 4 0 EMEX_HIGH 8 EXTENDED 0 80 1100 30FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 40 10FF 10C0 1080 1040 1000 3100 FFBD 10000 19FFF FFBE 2 FFC0 FFFF
197 msp430f47183 1 CPU19 4 0 EMEX_HIGH 8 EXTENDED 0 80 1100 30FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 40 10FF 10C0 1080 1040 1000 3100 FFBD 10000 1FFFF FFBE 2 FFC0 FFFF
198 msp430f47193 1 CPU19 4 0 EMEX_HIGH 8 EXTENDED 0 80 1100 20FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 40 10FF 10C0 1080 1040 1000 2100 FFBD 10000 1FFFF FFBE 2 FFC0 FFFF
199 msp430f47166 1 CPU19 4 0 EMEX_HIGH 8 EXTENDED 0 80 1100 20FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 40 10FF 10C0 1080 1040 1000 2100 FFBD 10000 18FFF FFBE 2 FFC0 FFFF
200 msp430f47176 1 CPU19 4 0 EMEX_HIGH 8 EXTENDED 0 80 1100 30FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 40 10FF 10C0 1080 1040 1000 3100 FFBD 10000 19FFF FFBE 2 FFC0 FFFF
201 msp430f47186 1 CPU19 4 0 EMEX_HIGH 8 EXTENDED 0 80 1100 30FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 40 10FF 10C0 1080 1040 1000 3100 FFBD 10000 1FFFF FFBE 2 FFC0 FFFF
202 msp430f47196 1 CPU19 4 0 EMEX_HIGH 8 EXTENDED 0 80 1100 20FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 40 10FF 10C0 1080 1040 1000 2100 FFBD 10000 1FFFF FFBE 2 FFC0 FFFF
203 msp430f47167 1 CPU19 4 0 EMEX_HIGH 8 EXTENDED 0 80 1100 20FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 40 10FF 10C0 1080 1040 1000 2100 FFBD 10000 18FFF FFBE 2 FFC0 FFFF
204 msp430f47177 1 CPU19 4 0 EMEX_HIGH 8 EXTENDED 0 80 1100 30FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 40 10FF 10C0 1080 1040 1000 3100 FFBD 10000 19FFF FFBE 2 FFC0 FFFF
205 msp430f47187 1 CPU19 4 0 EMEX_HIGH 8 EXTENDED 0 80 1100 30FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 40 10FF 10C0 1080 1040 1000 3100 FFBD 10000 1FFFF FFBE 2 FFC0 FFFF
206 msp430f47197 1 CPU19 4 0 EMEX_HIGH 8 EXTENDED 0 80 1100 20FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 40 10FF 10C0 1080 1040 1000 2100 FFBD 10000 1FFFF FFBE 2 FFC0 FFFF
207 msp430f4250 0 0 0 0 EMEX_LOW 2 STANDARD 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 C000 FFDF 0 0 FFE0 FFFF
208 msp430f4260 0 0 0 0 EMEX_LOW 2 STANDARD 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 A000 FFDF 0 0 FFE0 FFFF
209 msp430f4270 0 0 0 0 EMEX_LOW 2 STANDARD 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 8000 FFDF 0 0 FFE0 FFFF
210 msp430fg4250 0 0 0 0 EMEX_LOW 2 STANDARD 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 C000 FFDF 0 0 FFE0 FFFF
211 msp430fg4260 0 0 0 0 EMEX_LOW 2 STANDARD 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 A000 FFDF 0 0 FFE0 FFFF
212 msp430fg4270 0 0 0 0 EMEX_LOW 2 STANDARD 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 8000 FFDF 0 0 FFE0 FFFF
213 msp430fw423 0 0 0 0 EMEX_LOW 2 STANDARD 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 E000 FFDF 0 0 FFE0 FFFF
214 msp430fw425 0 0 0 0 EMEX_LOW 2 STANDARD 0 80 200 03FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 C000 FFDF 0 0 FFE0 FFFF
215 msp430fw427 0 0 0 0 EMEX_LOW 2 STANDARD 0 80 200 05FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 8000 FFDF 0 0 FFE0 FFFF
216 msp430fw428 0 0 0 0 EMEX_LOW 2 STANDARD 0 80 200 09FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 4000 FFDF 0 0 FFE0 FFFF
217 msp430fw429 0 0 0 0 EMEX_LOW 2 STANDARD 0 80 200 09FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 1100 FFDF 0 0 FFE0 FFFF
218 msp430fg437 0 0 0 0 EMEX_LOW 2 EXTENDED 0 80 200 05FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 8000 FFDF 0 0 FFE0 FFFF
219 msp430fg438 0 0 0 0 EMEX_LOW 2 EXTENDED 0 80 200 09FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 4000 FFDF 0 0 FFE0 FFFF
220 msp430fg439 0 0 0 0 EMEX_LOW 2 EXTENDED 0 80 200 09FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 1100 FFDF 0 0 FFE0 FFFF
221 msp430f438 0 0 0 0 EMEX_LOW 2 EXTENDED 0 80 200 09FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 4000 FFDF 0 0 FFE0 FFFF
222 msp430f439 0 0 0 0 EMEX_LOW 2 EXTENDED 0 80 200 09FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 80 10FF 1080 1000 0 0 1100 FFDF 0 0 FFE0 FFFF
223 msp430f477 0 0 0 0 EMEX_LOW 2 EXTENDED 0 80 200 09FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 8000 FFDF 0 0 FFE0 FFFF
224 msp430f478 0 0 0 0 EMEX_LOW 2 EXTENDED 0 80 200 09FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 4000 FFDF 0 0 FFE0 FFFF
225 msp430f479 0 0 0 0 EMEX_LOW 2 EXTENDED 0 80 200 09FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 1100 FFDF 0 0 FFE0 FFFF
226 msp430fg477 0 CPU19 0 0 EMEX_LOW 2 EXTENDED 0 80 200 09FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 8000 FFDF 0 0 FFE0 FFFF
227 msp430fg478 0 CPU19 0 0 EMEX_LOW 2 EXTENDED 0 80 200 09FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 4000 FFDF 0 0 FFE0 FFFF
228 msp430fg479 0 CPU19 0 0 EMEX_LOW 2 EXTENDED 0 80 200 09FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 1100 FFDF 0 0 FFE0 FFFF
229 msp430f46161 1 0 1 0 EMEX_HIGH 8 EXTENDED 0 80 1100 20FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 80 10FF 1080 1000 0 0 2100 FFBD 10000 18FFF FFBE 2 FFC0 FFFF
230 msp430f46171 1 0 1 0 EMEX_HIGH 8 EXTENDED 0 80 1100 30FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 80 10FF 1080 1000 0 0 3100 FFBD 10000 19FFF FFBE 2 FFC0 FFFF
231 msp430f46181 1 0 1 0 EMEX_HIGH 8 EXTENDED 0 80 1100 30FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 80 10FF 1080 1000 0 0 3100 FFBD 10000 1FFFF FFBE 2 FFC0 FFFF
232 msp430f46191 1 0 1 0 EMEX_HIGH 8 EXTENDED 0 80 1100 20FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 80 10FF 1080 1000 0 0 2100 FFBD 10000 1FFFF FFBE 2 FFC0 FFFF
233 msp430f4616 1 CPU16; CPU19 1 0 EMEX_HIGH 8 EXTENDED 0 80 1100 20FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 80 10FF 1080 1000 0 0 2100 FFBD 10000 18FFF FFBE 2 FFC0 FFFF
234 msp430f4617 1 CPU16; CPU19 1 0 EMEX_HIGH 8 EXTENDED 0 80 1100 30FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 80 10FF 1080 1000 0 0 3100 FFBD 10000 19FFF FFBE 2 FFC0 FFFF
235 msp430f4618 1 CPU16; CPU19 1 0 EMEX_HIGH 8 EXTENDED 0 80 1100 30FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 80 10FF 1080 1000 0 0 3100 FFBD 10000 1FFFF FFBE 2 FFC0 FFFF
236 msp430f4619 1 CPU16; CPU19 1 0 EMEX_HIGH 8 EXTENDED 0 80 1100 20FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 80 10FF 1080 1000 0 0 2100 FFBD 10000 1FFFF FFBE 2 FFC0 FFFF
237 msp430fg4616 1 CPU16; CPU19 1 0 EMEX_HIGH 8 EXTENDED 0 80 1100 20FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 80 10FF 1080 1000 0 0 2100 FFBD 10000 18FFF FFBE 2 FFC0 FFFF
238 msp430fg4617 1 CPU16; CPU19 1 0 EMEX_HIGH 8 EXTENDED 0 80 1100 30FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 80 10FF 1080 1000 0 0 3100 FFBD 10000 19FFF FFBE 2 FFC0 FFFF
239 msp430fg4618 1 CPU16; CPU19 1 0 EMEX_HIGH 8 EXTENDED 0 80 1100 30FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 80 10FF 1080 1000 0 0 3100 FFBD 10000 1FFFF FFBE 2 FFC0 FFFF
240 msp430fg4619 1 CPU16; CPU19 1 0 EMEX_HIGH 8 EXTENDED 0 80 1100 20FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 80 10FF 1080 1000 0 0 2100 FFBD 10000 1FFFF FFBE 2 FFC0 FFFF
241 msp430f5418 2 CPU15; CPU16; CPU18; CPU20; CPU21; CPU22; CPU23; CPU24; CPU25; CPU27; CPU29; CPU30; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 5C00 FF7F 10000 25BFB FF80 FFFF
242 msp430f5419 2 CPU15; CPU16; CPU18; CPU20; CPU21; CPU22; CPU23; CPU24; CPU25; CPU27; CPU29; CPU30; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 5C00 FF7F 10000 25BFB FF80 FFFF
243 msp430f5435 2 CPU15; CPU16; CPU18; CPU20; CPU21; CPU22; CPU23; CPU24; CPU25; CPU27; CPU29; CPU30; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 5C00 FF7F 10000 35BFB FF80 FFFF
244 msp430f5436 2 CPU15; CPU16; CPU18; CPU20; CPU21; CPU22; CPU23; CPU24; CPU25; CPU27; CPU29; CPU30; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 5C00 FF7F 10000 35BFB FF80 FFFF
245 msp430f5437 2 CPU15; CPU16; CPU18; CPU20; CPU21; CPU22; CPU23; CPU24; CPU25; CPU27; CPU29; CPU30; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 5C00 FF7F 10000 45BFB FF80 FFFF
246 msp430f5438 2 CPU15; CPU16; CPU18; CPU20; CPU21; CPU22; CPU23; CPU24; CPU25; CPU27; CPU29; CPU30; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 5C00 FF7F 10000 45BFB FF80 FFFF
247 msp430f5418a 2 CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 5C00 FF7F 10000 25BFF FF80 FFFF
248 msp430f5419a 2 CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 5C00 FF7F 10000 25BFF FF80 FFFF
249 msp430f5435a 2 CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 5C00 FF7F 10000 35BFF FF80 FFFF
250 msp430f5436a 2 CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 5C00 FF7F 10000 35BFF FF80 FFFF
251 msp430f5437a 2 CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 5C00 FF7F 10000 45BFF FF80 FFFF
252 msp430f5438a 2 CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 5C00 FF7F 10000 45BFF FF80 FFFF
253 msp430f5212 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2400 43FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 143FF FF80 FFFF
254 msp430f5213 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2400 43FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 1C3FF FF80 FFFF
255 msp430f5214 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2400 43FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 243FF FF80 FFFF
256 msp430f5217 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2400 43FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 143FF FF80 FFFF
257 msp430f5218 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2400 43FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 1C3FF FF80 FFFF
258 msp430f5219 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2400 43FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 243FF FF80 FFFF
259 msp430f5222 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2400 43FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 143FF FF80 FFFF
260 msp430f5223 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2400 43FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 1C3FF FF80 FFFF
261 msp430f5224 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2400 43FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 243FF FF80 FFFF
262 msp430f5227 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2400 43FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 143FF FF80 FFFF
263 msp430f5228 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2400 43FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 1C3FF FF80 FFFF
264 msp430f5229 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2400 43FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 243FF FF80 FFFF
265 msp430f5232 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2400 43FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 143FF FF80 FFFF
266 msp430f5234 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2400 43FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 243FF FF80 FFFF
267 msp430f5237 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2400 43FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 143FF FF80 FFFF
268 msp430f5239 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2400 43FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 243FF FF80 FFFF
269 msp430f5242 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2400 43FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 143FF FF80 FFFF
270 msp430f5244 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2400 43FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 243FF FF80 FFFF
271 msp430f5247 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2400 43FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 143FF FF80 FFFF
272 msp430f5249 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2400 43FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 243FF FF80 FFFF
273 msp430f5304 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 33FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 E000 FF7F 0 0 FF80 FFFF
274 msp430f5308 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 33FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 0 0 FF80 FFFF
275 msp430f5309 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 33FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 A000 FF7F 0 0 FF80 FFFF
276 msp430f5310 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 33FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 0 0 FF80 FFFF
277 msp430f5340 2 CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 33FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 143FF FF80 FFFF
278 msp430f5341 2 CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 3BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 1C3FF FF80 FFFF
279 msp430f5342 2 CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 43FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 243FF FF80 FFFF
280 msp430f5324 2 CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 33FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 143FF FF80 FFFF
281 msp430f5325 2 CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 33FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 143FF FF80 FFFF
282 msp430f5326 2 CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 3BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 1C3FF FF80 FFFF
283 msp430f5327 2 CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 3BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 1C3FF FF80 FFFF
284 msp430f5328 2 CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 43FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 243FF FF80 FFFF
285 msp430f5329 2 CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 43FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 243FF FF80 FFFF
286 msp430f5500 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2400 33FF 0 0 0 0 1C00 23FF 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 E000 FF7F 0 0 FF80 FFFF
287 msp430f5501 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2400 33FF 0 0 0 0 1C00 23FF 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 0 0 FF80 FFFF
288 msp430f5502 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2400 33FF 0 0 0 0 1C00 23FF 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 A000 FF7F 0 0 FF80 FFFF
289 msp430f5503 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2400 33FF 0 0 0 0 1C00 23FF 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 0 0 FF80 FFFF
290 msp430f5504 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2400 33FF 0 0 0 0 1C00 23FF 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 E000 FF7F 0 0 FF80 FFFF
291 msp430f5505 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2400 33FF 0 0 0 0 1C00 23FF 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 0 0 FF80 FFFF
292 msp430f5506 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2400 33FF 0 0 0 0 1C00 23FF 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 A000 FF7F 0 0 FF80 FFFF
293 msp430f5507 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2400 33FF 0 0 0 0 1C00 23FF 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 0 0 FF80 FFFF
294 msp430f5508 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2400 33FF 0 0 0 0 1C00 23FF 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 0 0 FF80 FFFF
295 msp430f5509 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2400 33FF 0 0 0 0 1C00 23FF 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 A000 FF7F 0 0 FF80 FFFF
296 msp430f5510 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2400 33FF 0 0 0 0 1C00 23FF 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 0 0 FF80 FFFF
297 msp430f5513 2 CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 2400 33FF 0 0 0 0 1C00 23FF 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 0 0 FF80 FFFF
298 msp430f5514 2 CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 2400 33FF 0 0 0 0 1C00 23FF 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 143FF FF80 FFFF
299 msp430f5515 2 CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 2400 33FF 0 0 0 0 1C00 23FF 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 143FF FF80 FFFF
300 msp430f5517 2 CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 2400 3BFF 0 0 0 0 1C00 23FF 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 1C3FF FF80 FFFF
301 msp430f5519 2 CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 2400 43FF 0 0 0 0 1C00 23FF 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 243FF FF80 FFFF
302 msp430f5521 2 CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 2400 3BFF 0 0 0 0 1C00 23FF 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 0 0 FF80 FFFF
303 msp430f5522 2 CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 2400 43FF 0 0 0 0 1C00 23FF 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 0 0 FF80 FFFF
304 msp430f5524 2 CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 2400 33FF 0 0 0 0 1C00 23FF 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 143FF FF80 FFFF
305 msp430f5525 2 CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 2400 33FF 0 0 0 0 1C00 23FF 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 143FF FF80 FFFF
306 msp430f5526 2 CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 2400 3BFF 0 0 0 0 1C00 23FF 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 1C3FF FF80 FFFF
307 msp430f5527 2 CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 2400 3BFF 0 0 0 0 1C00 23FF 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 1C3FF FF80 FFFF
308 msp430f5528 2 CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 2400 43FF 0 0 0 0 1C00 23FF 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 243FF FF80 FFFF
309 msp430f5529 2 CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 2400 43FF 0 0 0 0 1C00 23FF 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 243FF FF80 FFFF
310 msp430p112 0 0 0 0 NONE 0 NONE 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F000 FFDF 0 0 FFE0 FFFF
311 msp430p313 0 0 0 0 NONE 0 NONE 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 E000 FFDF 0 0 FFE0 FFFF
312 msp430p315 0 0 0 0 NONE 0 NONE 0 80 200 03FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C000 FFDF 0 0 FFE0 FFFF
313 msp430p315s 0 0 0 0 NONE 0 NONE 0 80 200 03FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C000 FFDF 0 0 FFE0 FFFF
314 msp430p325 0 0 0 0 NONE 0 NONE 0 80 200 03FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C000 FFDF 0 0 FFE0 FFFF
315 msp430p337 0 0 1 0 NONE 0 NONE 0 80 200 05FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8000 FFDF 0 0 FFE0 FFFF
316 cc430f5133 2 CPU18; CPU20; CPU21; CPU22; CPU23; CPU24; CPU25; CPU27; CPU29; CPU30; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 23FD 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 E000 FF7F 0 0 FF80 FFFF
317 cc430f5135 2 CPU18; CPU20; CPU21; CPU22; CPU23; CPU24; CPU25; CPU27; CPU29; CPU30; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 23FD 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 0 0 FF80 FFFF
318 cc430f5137 2 CPU18; CPU20; CPU21; CPU22; CPU23; CPU24; CPU25; CPU27; CPU29; CPU30; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 2BFD 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 0 0 FF80 FFFF
319 cc430f6125 2 CPU18; CPU20; CPU21; CPU22; CPU23; CPU24; CPU25; CPU27; CPU29; CPU30; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 23FD 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 0 0 FF80 FFFF
320 cc430f6126 2 CPU18; CPU20; CPU21; CPU22; CPU23; CPU24; CPU25; CPU27; CPU29; CPU30; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 23FD 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 0 0 FF80 FFFF
321 cc430f6127 2 CPU18; CPU20; CPU21; CPU22; CPU23; CPU24; CPU25; CPU27; CPU29; CPU30; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 2BFD 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 0 0 FF80 FFFF
322 cc430f6135 2 CPU18; CPU20; CPU21; CPU22; CPU23; CPU24; CPU25; CPU27; CPU29; CPU30; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 23FD 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 0 0 FF80 FFFF
323 cc430f6137 2 CPU18; CPU20; CPU21; CPU22; CPU23; CPU24; CPU25; CPU27; CPU29; CPU30; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 2BFD 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 0 0 FF80 FFFF
324 cc430f5123 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 23FD 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 E000 FF7F 0 0 FF80 FFFF
325 cc430f5125 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 23FD 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 0 0 FF80 FFFF
326 cc430f5143 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 23FD 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 E000 FF7F 0 0 FF80 FFFF
327 cc430f5145 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 23FD 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 0 0 FF80 FFFF
328 cc430f5147 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 2BFD 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 0 0 FF80 FFFF
329 cc430f6143 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 23FD 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 E000 FF7F 0 0 FF80 FFFF
330 cc430f6145 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 23FD 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 0 0 FF80 FFFF
331 cc430f6147 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 2BFD 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 0 0 FF80 FFFF
332 msp430f5333 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 43FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 10000 27FFF FF80 FFFF
333 msp430f5335 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 63FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 10000 47FFF FF80 FFFF
334 msp430f5336 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 63FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 10000 27FFF FF80 FFFF
335 msp430f5338 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 63FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 10000 47FFF FF80 FFFF
336 msp430f5630 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 2400 63FF 0 0 0 0 1C00 23FF 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 10000 27FFF FF80 FFFF
337 msp430f5631 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 2400 63FF 0 0 0 0 1C00 23FF 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 10000 37FFF FF80 FFFF
338 msp430f5632 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 2400 63FF 0 0 0 0 1C00 23FF 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 10000 47FFF FF80 FFFF
339 msp430f5633 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 2400 63FF 0 0 0 0 1C00 23FF 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 10000 27FFF FF80 FFFF
340 msp430f5634 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 2400 63FF 0 0 0 0 1C00 23FF 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 10000 37FFF FF80 FFFF
341 msp430f5635 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 2400 63FF 0 0 0 0 1C00 23FF 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 10000 47FFF FF80 FFFF
342 msp430f5636 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 2400 63FF 0 0 0 0 1C00 23FF 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 10000 27FFF FF80 FFFF
343 msp430f5637 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 2400 63FF 0 0 0 0 1C00 23FF 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 10000 37FFF FF80 FFFF
344 msp430f5638 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 2400 63FF 0 0 0 0 1C00 23FF 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 10000 47FFF FF80 FFFF
345 msp430f6433 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 2400 43FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 10000 27FFF FF80 FFFF
346 msp430f6435 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 2400 63FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 10000 47FFF FF80 FFFF
347 msp430f6436 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 2400 63FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 10000 27FFF FF80 FFFF
348 msp430f6438 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 2400 63FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 10000 47FFF FF80 FFFF
349 msp430f6630 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 2400 63FF 0 0 0 0 1C00 23FF 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 10000 27FFF FF80 FFFF
350 msp430f6631 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 2400 63FF 0 0 0 0 1C00 23FF 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 10000 37FFF FF80 FFFF
351 msp430f6632 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 2400 63FF 0 0 0 0 1C00 23FF 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 10000 47FFF FF80 FFFF
352 msp430f6633 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 2400 63FF 0 0 0 0 1C00 23FF 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 10000 27FFF FF80 FFFF
353 msp430f6634 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 2400 63FF 0 0 0 0 1C00 23FF 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 10000 37FFF FF80 FFFF
354 msp430f6635 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 2400 63FF 0 0 0 0 1C00 23FF 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 10000 47FFF FF80 FFFF
355 msp430f6636 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 2400 63FF 0 0 0 0 1C00 23FF 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 10000 27FFF FF80 FFFF
356 msp430f6637 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 2400 63FF 0 0 0 0 1C00 23FF 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 10000 37FFF FF80 FFFF
357 msp430f6638 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 2400 63FF 0 0 0 0 1C00 23FF 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 10000 47FFF FF80 FFFF
358 msp430f5358 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 63FF F8000 FBFFF 0 0 0 0 0 0 2400 FC000 FFFFF 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 10000 67FFF FF80 FFFF
359 msp430f5359 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 63FF F0000 FBFFF 0 0 0 0 0 0 2400 FC000 FFFFF 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 10000 87FFF FF80 FFFF
360 msp430f5658 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 2400 63FF F8000 FBFFF 0 0 1C00 23FF 0 0 2400 FC000 FFFFF 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 10000 67FFF FF80 FFFF
361 msp430f5659 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 2400 63FF F0000 FBFFF 0 0 1C00 23FF 0 0 2400 FC000 FFFFF 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 10000 87FFF FF80 FFFF
362 msp430f6458 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 63FF F8000 FBFFF 0 0 0 0 0 0 2400 FC000 FFFFF 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 10000 67FFF FF80 FFFF
363 msp430f6459 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 63FF F0000 FBFFF 0 0 0 0 0 0 2400 FC000 FFFFF 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 10000 87FFF FF80 FFFF
364 msp430f6658 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 2400 63FF F8000 FBFFF 0 0 1C00 23FF 0 0 2400 FC000 FFFFF 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 10000 67FFF FF80 FFFF
365 msp430f6659 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 2400 63FF F0000 FBFFF 0 0 1C00 23FF 0 0 2400 FC000 FFFFF 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 10000 87FFF FF80 FFFF
366 msp430fg6425 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 43FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 143FF FF80 FFFF
367 msp430fg6426 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 43FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 243FF FF80 FFFF
368 msp430fg6625 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 2400 43FF 0 0 0 0 1C00 23FF 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 143FF FF80 FFFF
369 msp430fg6626 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 2400 43FF 0 0 0 0 1C00 23FF 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 243FF FF80 FFFF
370 msp430l092 0 CPU18; CPU21; CPU22; CPU23; CPU27; CPU29; CPU30 0 0 EMEX_EXTRA_SMALL_5XX 2 EXTENDED 1 80 2380 23FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1C00 60 1C5F 1C00 0 0 0 1C80 237F 0 0 1C60 1C7F
371 msp430c091 0 CPU18; CPU21; CPU22; CPU23; CPU27; CPU29; CPU30 0 0 EMEX_EXTRA_SMALL_5XX 2 EXTENDED 1 80 2380 23FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1C00 60 1C5F 1C00 0 0 0 FC80 FFDF 0 0 FFE0 FFFF
372 msp430c092 0 CPU18; CPU21; CPU22; CPU23; CPU27; CPU29; CPU30 0 0 EMEX_EXTRA_SMALL_5XX 2 EXTENDED 1 80 2380 23FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1C00 60 1C5F 1C00 0 0 0 F880 FFDF 0 0 FFE0 FFFF
373 msp430xgeneric 2 0 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 6400 FF7F 10000 463FF FF80 FFFF
374 msp430f5xx_6xxgeneric 2 0 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 6400 FF7F 10000 463FF FF80 FFFF
375 msp430fr5xx_6xxgeneric 2 0 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 6400 FF7F 10000 463FF FF80 FFFF
376 msp430fr2xx_4xxgeneric 2 0 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 6400 FF7F 10000 463FF FF80 FFFF
377 msp430fr57xxgeneric 2 0 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 6400 FF7F 10000 463FF FF80 FFFF
378 msp430i2xxgeneric 0 0 2 1 EMEX_LOW 2 STANDARD 0 80 200 05FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 400 13FF 1000 0 0 0 C000 FFDB 0 0 FFDC 4 FF80 FFFF
379 msp430f5131 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 1FFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 E000 FF7F 0 0 FF80 FFFF
380 msp430f5151 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 23FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 0 0 FF80 FFFF
381 msp430f5171 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 23FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 0 0 FF80 FFFF
382 msp430f5132 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 1FFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 E000 FF7F 0 0 FF80 FFFF
383 msp430f5152 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 23FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 0 0 FF80 FFFF
384 msp430f5172 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 23FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 0 0 FF80 FFFF
385 msp430f6720 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 1FFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 0 0 FF80 FFFF
386 msp430f6721 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 23FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 0 0 FF80 FFFF
387 msp430f6723 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 2BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4000 FF7F 10000 13FFF FF80 FFFF
388 msp430f6724 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 2BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4000 FF7F 10000 1BFFF FF80 FFFF
389 msp430f6725 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 2BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4000 FF7F 10000 23FFF FF80 FFFF
390 msp430f6726 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 3BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4000 FF7F 10000 23FFF FF80 FFFF
391 msp430f6730 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 1FFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 0 0 FF80 FFFF
392 msp430f6731 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 23FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 0 0 FF80 FFFF
393 msp430f6733 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 2BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4000 FF7F 10000 13FFF FF80 FFFF
394 msp430f6734 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 2BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4000 FF7F 10000 1BFFF FF80 FFFF
395 msp430f6735 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 2BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4000 FF7F 10000 23FFF FF80 FFFF
396 msp430f6736 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 3BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4000 FF7F 10000 23FFF FF80 FFFF
397 msp430f67621 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 2BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4000 FF7F 10000 13FFF FF80 FFFF
398 msp430f67641 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 2BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4000 FF7F 10000 23FFF FF80 FFFF
399 msp430f6720a 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 1FFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 0 0 FF80 FFFF
400 msp430f6721a 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 23FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 0 0 FF80 FFFF
401 msp430f6723a 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 2BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4000 FF7F 10000 13FFF FF80 FFFF
402 msp430f6724a 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 2BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4000 FF7F 10000 1BFFF FF80 FFFF
403 msp430f6725a 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 2BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4000 FF7F 10000 23FFF FF80 FFFF
404 msp430f6726a 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 3BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4000 FF7F 10000 23FFF FF80 FFFF
405 msp430f6730a 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 1FFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 0 0 FF80 FFFF
406 msp430f6731a 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 23FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 0 0 FF80 FFFF
407 msp430f6733a 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 2BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4000 FF7F 10000 13FFF FF80 FFFF
408 msp430f6734a 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 2BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4000 FF7F 10000 1BFFF FF80 FFFF
409 msp430f6735a 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 2BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4000 FF7F 10000 23FFF FF80 FFFF
410 msp430f6736a 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 3BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4000 FF7F 10000 23FFF FF80 FFFF
411 msp430f67621a 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 2BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4000 FF7F 10000 13FFF FF80 FFFF
412 msp430f67641a 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 2BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4000 FF7F 10000 23FFF FF80 FFFF
413 msp430f67451 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 2BFFF FF80 FFFF
414 msp430f67651 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 2BFFF FF80 FFFF
415 msp430f67751 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 2BFFF FF80 FFFF
416 msp430f67461 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 4BFFF FF80 FFFF
417 msp430f67661 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 4BFFF FF80 FFFF
418 msp430f67761 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 4BFFF FF80 FFFF
419 msp430f67471 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 9BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 4BFFF FF80 FFFF
420 msp430f67671 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 9BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 4BFFF FF80 FFFF
421 msp430f67771 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 9BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 4BFFF FF80 FFFF
422 msp430f67481 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 8BFFF FF80 FFFF
423 msp430f67681 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 8BFFF FF80 FFFF
424 msp430f67781 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 8BFFF FF80 FFFF
425 msp430f67491 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 9BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 8BFFF FF80 FFFF
426 msp430f67691 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 9BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 8BFFF FF80 FFFF
427 msp430f67791 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 9BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 8BFFF FF80 FFFF
428 msp430f6745 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 2BFFF FF80 FFFF
429 msp430f6765 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 2BFFF FF80 FFFF
430 msp430f6775 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 2BFFF FF80 FFFF
431 msp430f6746 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 4BFFF FF80 FFFF
432 msp430f6766 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 4BFFF FF80 FFFF
433 msp430f6776 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 4BFFF FF80 FFFF
434 msp430f6747 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 9BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 4BFFF FF80 FFFF
435 msp430f6767 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 9BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 4BFFF FF80 FFFF
436 msp430f6777 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 9BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 4BFFF FF80 FFFF
437 msp430f6748 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 8BFFF FF80 FFFF
438 msp430f6768 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 8BFFF FF80 FFFF
439 msp430f6778 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 8BFFF FF80 FFFF
440 msp430f6749 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 9BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 8BFFF FF80 FFFF
441 msp430f6769 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 9BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 8BFFF FF80 FFFF
442 msp430f6779 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 9BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 8BFFF FF80 FFFF
443 msp430f67451a 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 2BFFF FF80 FFFF
444 msp430f67651a 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 2BFFF FF80 FFFF
445 msp430f67751a 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 2BFFF FF80 FFFF
446 msp430f67461a 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 4BFFF FF80 FFFF
447 msp430f67661a 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 4BFFF FF80 FFFF
448 msp430f67761a 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 4BFFF FF80 FFFF
449 msp430f67471a 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 9BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 4BFFF FF80 FFFF
450 msp430f67671a 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 9BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 4BFFF FF80 FFFF
451 msp430f67771a 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 9BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 4BFFF FF80 FFFF
452 msp430f67481a 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 8BFFF FF80 FFFF
453 msp430f67681a 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 8BFFF FF80 FFFF
454 msp430f67781a 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 8BFFF FF80 FFFF
455 msp430f67491a 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 9BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 8BFFF FF80 FFFF
456 msp430f67691a 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 9BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 8BFFF FF80 FFFF
457 msp430f67791a 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 9BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 8BFFF FF80 FFFF
458 msp430f6745a 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 2BFFF FF80 FFFF
459 msp430f6765a 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 2BFFF FF80 FFFF
460 msp430f6775a 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 2BFFF FF80 FFFF
461 msp430f6746a 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 4BFFF FF80 FFFF
462 msp430f6766a 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 4BFFF FF80 FFFF
463 msp430f6776a 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 4BFFF FF80 FFFF
464 msp430f6747a 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 9BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 4BFFF FF80 FFFF
465 msp430f6767a 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 9BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 4BFFF FF80 FFFF
466 msp430f6777a 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 9BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 4BFFF FF80 FFFF
467 msp430f6748a 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 8BFFF FF80 FFFF
468 msp430f6768a 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 8BFFF FF80 FFFF
469 msp430f6778a 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 8BFFF FF80 FFFF
470 msp430f6749a 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 9BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 8BFFF FF80 FFFF
471 msp430f6769a 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 9BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 8BFFF FF80 FFFF
472 msp430f6779a 2 CPU21; CPU22; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 9BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 10000 8BFFF FF80 FFFF
473 msp430fr5720 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 1FFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 18FF 1880 1800 0 0 F000 FF7F 0 0 FF80 10 FF90 FFFF
474 msp430fr5721 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 1FFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 18FF 1880 1800 0 0 F000 FF7F 0 0 FF80 10 FF90 FFFF
475 msp430fr5722 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 1FFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 18FF 1880 1800 0 0 E000 FF7F 0 0 FF80 10 FF90 FFFF
476 msp430fr5723 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 1FFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 18FF 1880 1800 0 0 E000 FF7F 0 0 FF80 10 FF90 FFFF
477 msp430fr5724 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 1FFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 18FF 1880 1800 0 0 E000 FF7F 0 0 FF80 10 FF90 FFFF
478 msp430fr5725 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 1FFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 18FF 1880 1800 0 0 E000 FF7F 0 0 FF80 10 FF90 FFFF
479 msp430fr5726 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 1FFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 18FF 1880 1800 0 0 C200 FF7F 0 0 FF80 10 FF90 FFFF
480 msp430fr5727 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 1FFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 18FF 1880 1800 0 0 C200 FF7F 0 0 FF80 10 FF90 FFFF
481 msp430fr5728 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 1FFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 18FF 1880 1800 0 0 C200 FF7F 0 0 FF80 10 FF90 FFFF
482 msp430fr5729 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 1FFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 18FF 1880 1800 0 0 C200 FF7F 0 0 FF80 10 FF90 FFFF
483 msp430fr5730 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 1FFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 18FF 1880 1800 0 0 F000 FF7F 0 0 FF80 10 FF90 FFFF
484 msp430fr5731 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 1FFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 18FF 1880 1800 0 0 F000 FF7F 0 0 FF80 10 FF90 FFFF
485 msp430fr5732 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 1FFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 18FF 1880 1800 0 0 E000 FF7F 0 0 FF80 10 FF90 FFFF
486 msp430fr5733 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 1FFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 18FF 1880 1800 0 0 E000 FF7F 0 0 FF80 10 FF90 FFFF
487 msp430fr5734 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 1FFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 18FF 1880 1800 0 0 E000 FF7F 0 0 FF80 10 FF90 FFFF
488 msp430fr5735 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 1FFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 18FF 1880 1800 0 0 E000 FF7F 0 0 FF80 10 FF90 FFFF
489 msp430fr5736 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 1FFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 18FF 1880 1800 0 0 C200 FF7F 0 0 FF80 10 FF90 FFFF
490 msp430fr5737 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 1FFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 18FF 1880 1800 0 0 C200 FF7F 0 0 FF80 10 FF90 FFFF
491 msp430fr5738 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 1FFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 18FF 1880 1800 0 0 C200 FF7F 0 0 FF80 10 FF90 FFFF
492 msp430fr5739 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 1FFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 18FF 1880 1800 0 0 C200 FF7F 0 0 FF80 10 FF90 FFFF
493 msp430g2211 0 0 0 1 EMEX_LOW 2 STANDARD 0 50 200 027F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 F800 FFDF 0 0 FFE0 FFFF
494 msp430g2201 0 0 0 1 EMEX_LOW 2 STANDARD 0 50 200 027F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 F800 FFDF 0 0 FFE0 FFFF
495 msp430g2111 0 0 0 1 EMEX_LOW 2 STANDARD 0 50 200 027F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 FC00 FFDF 0 0 FFE0 FFFF
496 msp430g2101 0 0 0 1 EMEX_LOW 2 STANDARD 0 50 200 027F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 FC00 FFDF 0 0 FFE0 FFFF
497 msp430g2001 0 0 0 1 EMEX_LOW 2 STANDARD 0 50 200 027F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 FE00 FFDF 0 0 FFE0 FFFF
498 msp430g2231 0 0 0 1 EMEX_LOW 2 STANDARD 0 50 200 027F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 F800 FFDF 0 0 FFE0 FFFF
499 msp430g2221 0 0 0 1 EMEX_LOW 2 STANDARD 0 50 200 027F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 F800 FFDF 0 0 FFE0 FFFF
500 msp430g2131 0 0 0 1 EMEX_LOW 2 STANDARD 0 50 200 027F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 FC00 FFDF 0 0 FFE0 FFFF
501 msp430g2121 0 0 0 1 EMEX_LOW 2 STANDARD 0 50 200 027F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 FC00 FFDF 0 0 FFE0 FFFF
502 msp430afe221 0 0 2 1 EMEX_LOW 2 STANDARD 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 F000 FFDF 0 0 FFE0 FFFF
503 msp430afe231 0 0 2 1 EMEX_LOW 2 STANDARD 0 80 200 03FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 E000 FFDF 0 0 FFE0 FFFF
504 msp430afe251 0 0 2 1 EMEX_LOW 2 STANDARD 0 80 200 03FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 C000 FFDF 0 0 FFE0 FFFF
505 msp430afe222 0 0 2 1 EMEX_LOW 2 STANDARD 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 F000 FFDF 0 0 FFE0 FFFF
506 msp430afe232 0 0 2 1 EMEX_LOW 2 STANDARD 0 80 200 03FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 E000 FFDF 0 0 FFE0 FFFF
507 msp430afe252 0 0 2 1 EMEX_LOW 2 STANDARD 0 80 200 03FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 C000 FFDF 0 0 FFE0 FFFF
508 msp430afe223 0 0 2 1 EMEX_LOW 2 STANDARD 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 F000 FFDF 0 0 FFE0 FFFF
509 msp430afe233 0 0 2 1 EMEX_LOW 2 STANDARD 0 80 200 03FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 E000 FFDF 0 0 FFE0 FFFF
510 msp430afe253 0 0 2 1 EMEX_LOW 2 STANDARD 0 80 200 03FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 C000 FFDF 0 0 FFE0 FFFF
511 msp430g2102 0 0 0 1 EMEX_LOW 2 STANDARD 0 80 200 027F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 FC00 FFDF 0 0 FFE0 FFFF
512 msp430g2202 0 0 0 1 EMEX_LOW 2 STANDARD 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 F800 FFDF 0 0 FFE0 FFFF
513 msp430g2302 0 0 0 1 EMEX_LOW 2 STANDARD 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 F000 FFDF 0 0 FFE0 FFFF
514 msp430g2402 0 0 0 1 EMEX_LOW 2 STANDARD 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 E000 FFDF 0 0 FFE0 FFFF
515 msp430g2132 0 0 0 1 EMEX_LOW 2 STANDARD 0 80 200 027F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 FC00 FFDF 0 0 FFE0 FFFF
516 msp430g2232 0 0 0 1 EMEX_LOW 2 STANDARD 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 F800 FFDF 0 0 FFE0 FFFF
517 msp430g2332 0 0 0 1 EMEX_LOW 2 STANDARD 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 F000 FFDF 0 0 FFE0 FFFF
518 msp430g2432 0 0 0 1 EMEX_LOW 2 STANDARD 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 E000 FFDF 0 0 FFE0 FFFF
519 msp430g2112 0 0 0 1 EMEX_LOW 2 STANDARD 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 FC00 FFDF 0 0 FFE0 FFFF
520 msp430g2212 0 0 0 1 EMEX_LOW 2 STANDARD 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 F800 FFDF 0 0 FFE0 FFFF
521 msp430g2312 0 0 0 1 EMEX_LOW 2 STANDARD 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 F000 FFDF 0 0 FFE0 FFFF
522 msp430g2412 0 0 0 1 EMEX_LOW 2 STANDARD 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 E000 FFDF 0 0 FFE0 FFFF
523 msp430g2152 0 0 0 1 EMEX_LOW 2 STANDARD 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 FC00 FFDF 0 0 FFE0 FFFF
524 msp430g2252 0 0 0 1 EMEX_LOW 2 STANDARD 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 F800 FFDF 0 0 FFE0 FFFF
525 msp430g2352 0 0 0 1 EMEX_LOW 2 STANDARD 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 F000 FFDF 0 0 FFE0 FFFF
526 msp430g2452 0 0 0 1 EMEX_LOW 2 STANDARD 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 E000 FFDF 0 0 FFE0 FFFF
527 msp430g2113 0 0 0 1 EMEX_LOW 2 STANDARD 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 FC00 FFDD 0 0 FFDE 2 FFE0 FFFF
528 msp430g2213 0 0 0 1 EMEX_LOW 2 STANDARD 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 F800 FFDD 0 0 FFDE 2 FFE0 FFFF
529 msp430g2313 0 0 0 1 EMEX_LOW 2 STANDARD 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 F000 FFDD 0 0 FFDE 2 FFE0 FFFF
530 msp430g2413 0 0 0 1 EMEX_LOW 2 STANDARD 0 80 200 03FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 E000 FFDD 0 0 FFDE 2 FFE0 FFFF
531 msp430g2513 0 0 0 1 EMEX_LOW 2 STANDARD 0 80 200 03FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 C000 FFDD 0 0 FFDE 2 FFE0 FFFF
532 msp430g2153 0 0 0 1 EMEX_LOW 2 STANDARD 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 FC00 FFDD 0 0 FFDE 2 FFE0 FFFF
533 msp430g2253 0 0 0 1 EMEX_LOW 2 STANDARD 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 F800 FFDD 0 0 FFDE 2 FFE0 FFFF
534 msp430g2353 0 0 0 1 EMEX_LOW 2 STANDARD 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 F000 FFDD 0 0 FFDE 2 FFE0 FFFF
535 msp430g2453 0 0 0 1 EMEX_LOW 2 STANDARD 0 80 200 03FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 E000 FFDD 0 0 FFDE 2 FFE0 FFFF
536 msp430g2553 0 0 0 1 EMEX_LOW 2 STANDARD 0 80 200 03FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 C000 FFDD 0 0 FFDE 2 FFE0 FFFF
537 msp430g2203 0 0 0 1 EMEX_LOW 2 STANDARD 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 F800 FFDD 0 0 FFDE 2 FFE0 FFFF
538 msp430g2303 0 0 0 1 EMEX_LOW 2 STANDARD 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 F000 FFDD 0 0 FFDE 2 FFE0 FFFF
539 msp430g2403 0 0 0 1 EMEX_LOW 2 STANDARD 0 80 200 03FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 E000 FFDD 0 0 FFDE 2 FFE0 FFFF
540 msp430g2233 0 0 0 1 EMEX_LOW 2 STANDARD 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 F800 FFDD 0 0 FFDE 2 FFE0 FFFF
541 msp430g2333 0 0 0 1 EMEX_LOW 2 STANDARD 0 80 200 02FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 F000 FFDD 0 0 FFDE 2 FFE0 FFFF
542 msp430g2433 0 0 0 1 EMEX_LOW 2 STANDARD 0 80 200 03FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 E000 FFDD 0 0 FFDE 2 FFE0 FFFF
543 msp430g2533 0 0 0 1 EMEX_LOW 2 STANDARD 0 80 200 03FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 C000 FFDD 0 0 FFDE 2 FFE0 FFFF
544 msp430tch5e 0 0 0 1 EMEX_LOW 2 STANDARD 0 80 200 03FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 C000 FFDD 0 0 FFDE 2 FFE0 FFFF
545 msp430g2444 0 CPU19 0 1 EMEX_LOW 2 STANDARD 0 80 200 03FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 E000 FFDD 0 0 FFDE 2 FFE0 FFFF
546 msp430g2544 0 CPU19 0 1 EMEX_LOW 2 STANDARD 0 80 200 03FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 C000 FFDD 0 0 FFDE 2 FFE0 FFFF
547 msp430g2744 0 CPU19 0 1 EMEX_LOW 2 STANDARD 0 80 200 05FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 8000 FFDD 0 0 FFDE 2 FFE0 FFFF
548 msp430g2755 0 0 0 1 EMEX_LOW 2 STANDARD 0 80 1100 20FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 40 10FF 10C0 1080 1040 1000 8000 FFDD 0 0 FFDE 2 FFE0 FFFF
549 msp430g2855 0 0 0 1 EMEX_LOW 2 STANDARD 0 80 1100 20FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 40 10FF 10C0 1080 1040 1000 4000 FFDD 0 0 FFDE 2 FFE0 FFFF
550 msp430g2955 0 0 0 1 EMEX_LOW 2 STANDARD 0 80 1100 20FF 0 0 0 0 0 0 0 0 1100 200 9FF 0 0 0 1000 40 10FF 10C0 1080 1040 1000 2100 FFDD 0 0 FFDE 2 FFE0 FFFF
551 msp430g2230 0 0 0 1 EMEX_LOW 2 STANDARD 0 50 200 027F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 F800 FFDF 0 0 FFE0 FFFF
552 msp430g2210 0 0 0 1 EMEX_LOW 2 STANDARD 0 50 200 027F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 40 10FF 10C0 1080 1040 1000 F800 FFDF 0 0 FFE0 FFFF
553 msp430bt5190 2 CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 5C00 FF7F 10000 45BFF FF80 FFFF
554 msp430fr5857 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 1FFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 0 0 FF80 10 FF90 FFFF
555 msp430fr5858 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 0 0 FF80 10 FF90 FFFF
556 msp430fr5859 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 13FFF FF80 10 FF90 FFFF
557 msp430fr5847 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 1FFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 0 0 FF80 10 FF90 FFFF
558 msp430fr58471 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 1FFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 0 0 FF80 10 FF90 FFFF
559 msp430fr5848 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 0 0 FF80 10 FF90 FFFF
560 msp430fr5849 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 13FFF FF80 10 FF90 FFFF
561 msp430fr5867 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 1FFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 0 0 FF80 10 FF90 FFFF
562 msp430fr58671 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 1FFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 0 0 FF80 10 FF90 FFFF
563 msp430fr5868 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 0 0 FF80 10 FF90 FFFF
564 msp430fr5869 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 13FFF FF80 10 FF90 FFFF
565 msp430fr5957 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 1FFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 0 0 FF80 10 FF90 FFFF
566 msp430fr5958 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 0 0 FF80 10 FF90 FFFF
567 msp430fr5959 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 13FFF FF80 10 FF90 FFFF
568 msp430fr5947 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 1FFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 0 0 FF80 10 FF90 FFFF
569 msp430fr59471 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 1FFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 0 0 FF80 10 FF90 FFFF
570 msp430fr5948 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 0 0 FF80 10 FF90 FFFF
571 msp430fr5949 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 13FFF FF80 10 FF90 FFFF
572 msp430fr5967 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 1FFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 0 0 FF80 10 FF90 FFFF
573 msp430fr5968 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 0 0 FF80 10 FF90 FFFF
574 msp430fr5969 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 13FFF FF80 10 FF90 FFFF
575 msp430fr59691 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 13FFF FF80 10 FF90 FFFF
576 msp430i2020 0 0 2 1 EMEX_LOW 2 STANDARD 0 80 200 05FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 400 13FF 1000 0 0 0 C000 FFDB 0 0 FFDC 4 FFE0 FFFF
577 msp430i2021 0 0 2 1 EMEX_LOW 2 STANDARD 0 80 200 09FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 400 13FF 1000 0 0 0 8000 FFDB 0 0 FFDC 4 FFE0 FFFF
578 msp430i2030 0 0 2 1 EMEX_LOW 2 STANDARD 0 80 200 05FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 400 13FF 1000 0 0 0 C000 FFDB 0 0 FFDC 4 FFE0 FFFF
579 msp430i2031 0 0 2 1 EMEX_LOW 2 STANDARD 0 80 200 09FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 400 13FF 1000 0 0 0 8000 FFDB 0 0 FFDC 4 FFE0 FFFF
580 msp430i2040 0 0 2 1 EMEX_LOW 2 STANDARD 0 80 200 05FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 400 13FF 1000 0 0 0 C000 FFDB 0 0 FFDC 4 FFE0 FFFF
581 msp430i2041 0 0 2 1 EMEX_LOW 2 STANDARD 0 80 200 09FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 400 13FF 1000 0 0 0 8000 FFDB 0 0 FFDC 4 FFE0 FFFF
582 rf430frl152h 0 CPU21; CPU22 0 0 EMEX_EXTRA_SMALL_5XX 2 EXTENDED 1 80 1C00 2BFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F840 FFCF 0 0 FFD0 6 FFE0 FFFF
583 rf430frl153h 0 CPU21; CPU22 0 0 EMEX_EXTRA_SMALL_5XX 2 EXTENDED 1 80 1C00 2BFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F840 FFCF 0 0 FFD0 6 FFE0 FFFF
584 rf430frl154h 0 CPU21; CPU22 0 0 EMEX_EXTRA_SMALL_5XX 2 EXTENDED 1 80 1C00 2BFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F840 FFCF 0 0 FFD0 6 FFE0 FFFF
585 rf430frl152h_rom 0 CPU21; CPU22 0 0 EMEX_EXTRA_SMALL_5XX 2 EXTENDED 1 80 1C00 1DFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F840 FFCF 0 0 FFD0 6 FFE0 FFFF
586 rf430frl153h_rom 0 CPU21; CPU22 0 0 EMEX_EXTRA_SMALL_5XX 2 EXTENDED 1 80 1C00 1DFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F840 FFCF 0 0 FFD0 6 FFE0 FFFF
587 rf430frl154h_rom 0 CPU21; CPU22 0 0 EMEX_EXTRA_SMALL_5XX 2 EXTENDED 1 80 1C00 1DFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F840 FFCF 0 0 FFD0 6 FFE0 FFFF
588 rf430f5175 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 23FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 0 0 FF80 FFFF
589 rf430f5155 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 1FFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 0 0 FF80 FFFF
590 rf430f5144 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 80 1C00 1FFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 C000 FF7F 0 0 FF80 FFFF
591 msp430fr69271 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 6 001F 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 13FFF FF80 10 FF90 FFFF
592 msp430fr68791 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 6 001F 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 23FFF FF80 10 FF90 FFFF
593 msp430fr69791 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 6 001F 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 23FFF FF80 10 FF90 FFFF
594 msp430fr6927 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 6 001F 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 13FFF FF80 10 FF90 FFFF
595 msp430fr6928 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 6 001F 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 1BFFF FF80 10 FF90 FFFF
596 msp430fr6877 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 6 001F 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 13FFF FF80 10 FF90 FFFF
597 msp430fr6977 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 6 001F 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 13FFF FF80 10 FF90 FFFF
598 msp430fr6879 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 6 001F 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 23FFF FF80 10 FF90 FFFF
599 msp430fr6979 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 6 001F 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 23FFF FF80 10 FF90 FFFF
600 msp430fr58891 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 6 001F 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 23FFF FF80 10 FF90 FFFF
601 msp430fr68891 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 6 001F 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 23FFF FF80 10 FF90 FFFF
602 msp430fr59891 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 6 001F 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 23FFF FF80 10 FF90 FFFF
603 msp430fr69891 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 6 001F 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 23FFF FF80 10 FF90 FFFF
604 msp430fr5887 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 6 001F 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 13FFF FF80 10 FF90 FFFF
605 msp430fr5888 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 6 001F 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 1BFFF FF80 10 FF90 FFFF
606 msp430fr5889 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 6 001F 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 23FFF FF80 10 FF90 FFFF
607 msp430fr6887 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 6 001F 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 13FFF FF80 10 FF90 FFFF
608 msp430fr6888 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 6 001F 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 1BFFF FF80 10 FF90 FFFF
609 msp430fr6889 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 6 001F 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 23FFF FF80 10 FF90 FFFF
610 msp430fr5986 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 6 001F 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 0 0 FF80 10 FF90 FFFF
611 msp430fr5987 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 6 001F 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 13FFF FF80 10 FF90 FFFF
612 msp430fr5988 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 6 001F 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 1BFFF FF80 10 FF90 FFFF
613 msp430fr5989 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 6 001F 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 23FFF FF80 10 FF90 FFFF
614 msp430fr6987 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 6 001F 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 13FFF FF80 10 FF90 FFFF
615 msp430fr6988 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 6 001F 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 1BFFF FF80 10 FF90 FFFF
616 msp430fr6989 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 6 001F 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 23FFF FF80 10 FF90 FFFF
617 msp430fr5922 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 6 001F 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 13FFF FF80 10 FF90 FFFF
618 msp430fr5870 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 6 001F 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 0 0 FF80 10 FF90 FFFF
619 msp430fr5970 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 6 001F 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 0 0 FF80 10 FF90 FFFF
620 msp430fr5872 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 6 001F 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 13FFF FF80 10 FF90 FFFF
621 msp430fr5972 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 6 001F 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 13FFF FF80 10 FF90 FFFF
622 msp430fr6820 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 6 001F 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 0 0 FF80 10 FF90 FFFF
623 msp430fr6920 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 6 001F 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 0 0 FF80 10 FF90 FFFF
624 msp430fr6822 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 6 001F 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 13FFF FF80 10 FF90 FFFF
625 msp430fr6922 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 6 001F 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 13FFF FF80 10 FF90 FFFF
626 msp430fr6870 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 6 001F 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 0 0 FF80 10 FF90 FFFF
627 msp430fr6970 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 6 001F 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 8000 FF7F 0 0 FF80 10 FF90 FFFF
628 msp430fr6872 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 6 001F 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 13FFF FF80 10 FF90 FFFF
629 msp430fr6972 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 6 001F 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 13FFF FF80 10 FF90 FFFF
630 msp430fr59221 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 6 001F 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 13FFF FF80 10 FF90 FFFF
631 msp430fr58721 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 6 001F 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 13FFF FF80 10 FF90 FFFF
632 msp430fr59721 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 6 001F 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 13FFF FF80 10 FF90 FFFF
633 msp430fr68221 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 6 001F 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 13FFF FF80 10 FF90 FFFF
634 msp430fr69221 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 6 001F 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 13FFF FF80 10 FF90 FFFF
635 msp430fr68721 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 6 001F 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 13FFF FF80 10 FF90 FFFF
636 msp430fr69721 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 23FF 0 0 6 001F 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 4400 FF7F 10000 13FFF FF80 10 FF90 FFFF
637 msp430sl5438a 2 CPU21; CPU22; CPU23; CPU27; CPU29; CPU30; CPU40 8 2 EMEX_LARGE_5XX 8 EXTENDED 2 160 1C00 5BFF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 5C00 FF7F 10000 45BFF FF80 FFFF
638 msp430fr4131 2 CPU21; CPU22; CPU40 0 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2000 21FF 0 0 0 0 0 0 0 0 0 0 0 1000 400 13FF 1800 200 19FF 1800 0 0 0 F000 FF7F 0 0 FF80 8 FF88 FFFF
639 msp430fr4132 2 CPU21; CPU22; CPU40 0 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2000 23FF 0 0 0 0 0 0 0 0 0 0 0 1000 400 13FF 1800 200 19FF 1800 0 0 0 E000 FF7F 0 0 FF80 8 FF88 FFFF
640 msp430fr4133 2 CPU21; CPU22; CPU40 0 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2000 27FF 0 0 0 0 0 0 0 0 0 0 0 1000 400 13FF 1800 200 19FF 1800 0 0 0 C400 FF7F 0 0 FF80 8 FF88 FFFF
641 msp430fr2032 2 CPU21; CPU22; CPU40 0 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2000 23FF 0 0 0 0 0 0 0 0 0 0 0 1000 400 13FF 1800 200 19FF 1800 0 0 0 E000 FF7F 0 0 FF80 8 FF88 FFFF
642 msp430fr2033 2 CPU21; CPU22; CPU40 0 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2000 27FF 0 0 0 0 0 0 0 0 0 0 0 1000 400 13FF 1800 200 19FF 1800 0 0 0 C400 FF7F 0 0 FF80 8 FF88 FFFF
643 msp430fr2110 2 CPU21; CPU22; CPU40 0 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2000 23FF 0 0 0 0 0 0 0 0 0 0 0 1000 400 13FF 0 0 0 0 0 0 0 F800 FF7F 0 0 FF80 8 FF88 FFFF
644 msp430fr2111 2 CPU21; CPU22; CPU40 0 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2000 23FF 0 0 0 0 0 0 0 0 0 0 0 1000 400 13FF 0 0 0 0 0 0 0 F100 FF7F 0 0 FF80 8 FF88 FFFF
645 msp430fr2310 2 CPU21; CPU22; CPU40 0 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2000 23FF 0 0 0 0 0 0 0 0 0 0 0 1000 800 17FF 0 0 0 0 0 0 0 F800 FF7F 0 0 FF80 8 FF88 FFFF
646 msp430fr2311 2 CPU21; CPU22; CPU40 0 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2000 23FF 0 0 0 0 0 0 0 0 0 0 0 1000 800 17FF 0 0 0 0 0 0 0 F100 FF7F 0 0 FF80 8 FF88 FFFF
647 msp430fr2433 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2000 2FFF 0 0 0 0 0 0 0 0 0 0 0 1000 800 17FF 1800 200 19FF 1800 0 0 0 C400 FF7F 0 0 FF80 8 FF88 FFFF
648 msp430fr2532 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2000 23FF 0 0 0 0 0 0 0 0 0 0 0 1000 800 17FF 1800 200 19FF 1800 0 0 0 E000 FF7F 0 0 FF80 8 FF88 FFFF
649 msp430fr2533 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2000 27FF 0 0 0 0 0 0 0 0 0 0 0 1000 800 17FF 1800 200 19FF 1800 0 0 0 C400 FF7F 0 0 FF80 8 FF88 FFFF
650 msp430fr2632 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2000 27FF 0 0 0 0 0 0 0 0 0 0 0 1000 800 17FF 1800 200 19FF 1800 0 0 0 E000 FF7F 0 0 FF80 8 FF88 FFFF
651 msp430fr2633 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2000 2FFF 0 0 0 0 0 0 0 0 0 0 0 1000 800 17FF 1800 200 19FF 1800 0 0 0 C400 FF7F 0 0 FF80 8 FF88 FFFF
652 msp430f5252 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2400 63FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 A400 FF7F 10000 2A3FF FF80 FFFF
653 msp430f5253 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2400 63FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 A400 FF7F 10000 2A3FF FF80 FFFF
654 msp430f5254 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2400 A3FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 A400 FF7F 10000 2A3FF FF80 FFFF
655 msp430f5255 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2400 A3FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 A400 FF7F 10000 2A3FF FF80 FFFF
656 msp430f5256 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2400 63FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 A400 FF7F 10000 2A3FF FF80 FFFF
657 msp430f5257 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2400 63FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 A400 FF7F 10000 2A3FF FF80 FFFF
658 msp430f5258 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2400 A3FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 A400 FF7F 10000 2A3FF FF80 FFFF
659 msp430f5259 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2400 A3FF 0 0 0 0 0 0 0 0 0 0 0 1000 200 17FF 1800 80 19FF 1980 1900 1880 1800 A400 FF7F 10000 2A3FF FF80 FFFF
660 msp430fr5962 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 3BFF 0 0 A 001F 0 0 0 0 0 0 0 1000 800 17FF 1800 200 19FF 1980 1900 1880 1800 4000 FF7F 10000 23FFF FF80 10 FF90 FFFF
661 msp430fr5964 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 3BFF 0 0 A 001F 0 0 0 0 0 0 0 1000 800 17FF 1800 200 19FF 1980 1900 1880 1800 4000 FF7F 10000 43FFF FF80 10 FF90 FFFF
662 msp430fr5992 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 2BFF 0 0 A 001F 0 0 2C00 3BFF 0 0 0 1000 800 17FF 1800 200 19FF 1980 1900 1880 1800 4000 FF7F 10000 23FFF FF80 10 FF90 FFFF
663 msp430fr5994 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 2BFF 0 0 A 001F 0 0 2C00 3BFF 0 0 0 1000 800 17FF 1800 200 19FF 1980 1900 1880 1800 4000 FF7F 10000 43FFF FF80 10 FF90 FFFF
664 msp430fr59941 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 2BFF 0 0 A 001F 0 0 2C00 3BFF 0 0 0 1000 800 17FF 1800 200 19FF 1980 1900 1880 1800 4000 FF7F 10000 43FFF FF80 10 FF90 FFFF
665 msp430fr2100 2 CPU21; CPU22; CPU40 0 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2000 21FF 0 0 0 0 0 0 0 0 0 0 0 1000 400 13FF 0 0 0 0 0 0 0 FC00 FF7F 0 0 FF80 8 FF88 FFFF
666 msp430fr2000 2 CPU21; CPU22; CPU40 0 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2000 21FF 0 0 0 0 0 0 0 0 0 0 0 1000 400 13FF 0 0 0 0 0 0 0 FE00 FF7F 0 0 FF80 8 FF88 FFFF
667 msp430fr2355 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2000 2FFF 0 0 6 001F 0 0 0 0 0 0 0 1000 800 17FF 1800 200 19FF 0 0 0 0 8000 FF7F 0 0 FF80 22 FFA2 FFFF
668 msp430fr2155 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2000 2FFF 0 0 6 001F 0 0 0 0 0 0 0 1000 800 17FF 1800 200 19FF 0 0 0 0 8000 FF7F 0 0 FF80 22 FFA2 FFFF
669 msp430fr2353 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2000 27FF 0 0 6 001F 0 0 0 0 0 0 0 1000 800 17FF 1800 200 19FF 0 0 0 0 C000 FF7F 0 0 FF80 22 FFA2 FFFF
670 msp430fr2153 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2000 27FF 0 0 6 001F 0 0 0 0 0 0 0 1000 800 17FF 1800 200 19FF 0 0 0 0 C000 FF7F 0 0 FF80 22 FFA2 FFFF
671 msp430fr2522 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2000 27FF 0 0 0 0 0 0 0 0 0 0 0 1000 800 17FF 1800 100 18FF 0 0 0 0 E300 FF7F 0 0 FF80 8 FF88 FFFF
672 msp430fr2512 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2000 27FF 0 0 0 0 0 0 0 0 0 0 0 1000 800 17FF 1800 100 18FF 0 0 0 0 E300 FF7F 0 0 FF80 8 FF88 FFFF
673 msp430fr2422 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2000 27FF 0 0 0 0 0 0 0 0 0 0 0 1000 800 17FF 1800 100 18FF 0 0 0 0 E300 FF7F 0 0 FF80 8 FF88 FFFF
674 msp430fr2676 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2000 3FFF 0 0 6 001F 0 0 0 0 0 0 0 1000 800 17FF 1800 200 19FF 0 0 0 0 8000 FF7F 10000 17FFF FF80 22 FFA2 FFFF
675 msp430fr2476 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2000 3FFF 0 0 6 001F 0 0 0 0 0 0 0 1000 800 17FF 1800 200 19FF 0 0 0 0 8000 FF7F 10000 17FFF FF80 22 FFA2 FFFF
676 msp430fr2675 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2000 37FF 0 0 6 001F 0 0 0 0 0 0 0 1000 800 17FF 1800 200 19FF 0 0 0 0 8000 FF7F 0 0 FF80 22 FFA2 FFFF
677 msp430fr2673 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2000 2FFF 0 0 6 001F 0 0 0 0 0 0 0 1000 800 17FF 1800 200 19FF 0 0 0 0 C000 FF7F 0 0 FF80 22 FFA2 FFFF
678 msp430fr2475 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2000 2FFF 0 0 6 001F 0 0 0 0 0 0 0 1000 800 17FF 1800 200 19FF 0 0 0 0 8000 FF7F 0 0 FF80 22 FFA2 FFFF
679 msp430fr2672 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 2000 27FF 0 0 6 001F 0 0 0 0 0 0 0 1000 800 17FF 1800 200 19FF 0 0 0 0 E000 FF7F 0 0 FF80 22 FFA2 FFFF
680 msp430fr6043 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 2BFF 0 0 A 001F 0 0 5000 5FFF 0 0 0 1000 800 17FF 0 0 0 0 0 0 0 6000 FF7F 10000 15FFF FF80 10 FF90 FFFF
681 msp430fr5043 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 2BFF 0 0 A 001F 0 0 5000 5FFF 0 0 0 1000 800 17FF 0 0 0 0 0 0 0 6000 FF7F 10000 15FFF FF80 10 FF90 FFFF
682 msp430fr6041 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 2BFF 0 0 A 001F 0 0 5000 5FFF 0 0 0 1000 800 17FF 0 0 0 0 0 0 0 8000 FF7F 0 0 FF80 10 FF90 FFFF
683 msp430fr60431 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 2BFF 0 0 A 001F 0 0 5000 5FFF 0 0 0 1000 800 17FF 0 0 0 0 0 0 0 6000 FF7F 10000 15FFF FF80 10 FF90 FFFF
684 msp430fr5041 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 2BFF 0 0 A 001F 0 0 5000 5FFF 0 0 0 1000 800 17FF 0 0 0 0 0 0 0 8000 FF7F 0 0 FF80 10 FF90 FFFF
685 msp430fr50431 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 2BFF 0 0 A 001F 0 0 5000 5FFF 0 0 0 1000 800 17FF 0 0 0 0 0 0 0 6000 FF7F 10000 15FFF FF80 10 FF90 FFFF
686 msp430fr6005 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 2BFF 0 0 A 001F 0 0 2C00 3BFF 0 0 0 1000 800 17FF 0 0 0 0 0 0 0 4000 FF7F 10000 23FFF FF80 10 FF90 FFFF
687 msp430fr6047 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 2BFF 0 0 A 001F 0 0 2C00 3BFF 0 0 0 1000 800 17FF 0 0 0 0 0 0 0 4000 FF7F 10000 43FFF FF80 10 FF90 FFFF
688 msp430fr6037 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 2BFF 0 0 A 001F 0 0 2C00 3BFF 0 0 0 1000 800 17FF 0 0 0 0 0 0 0 4000 FF7F 10000 43FFF FF80 10 FF90 FFFF
689 msp430fr6045 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 2BFF 0 0 A 001F 0 0 2C00 3BFF 0 0 0 1000 800 17FF 0 0 0 0 0 0 0 4000 FF7F 10000 23FFF FF80 10 FF90 FFFF
690 msp430fr60471 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 2BFF 0 0 A 001F 0 0 2C00 3BFF 0 0 0 1000 800 17FF 0 0 0 0 0 0 0 4000 FF7F 10000 43FFF FF80 10 FF90 FFFF
691 msp430fr6035 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 2BFF 0 0 A 001F 0 0 2C00 3BFF 0 0 0 1000 800 17FF 0 0 0 0 0 0 0 4000 FF7F 10000 23FFF FF80 10 FF90 FFFF
692 msp430fr6007 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 2BFF 0 0 A 001F 0 0 2C00 3BFF 0 0 0 1000 800 17FF 0 0 0 0 0 0 0 4000 FF7F 10000 43FFF FF80 10 FF90 FFFF
693 msp430fr60371 2 CPU21; CPU22; CPU40 8 2 EMEX_SMALL_5XX 3 EXTENDED 1 160 1C00 2BFF 0 0 A 001F 0 0 2C00 3BFF 0 0 0 1000 800 17FF 0 0 0 0 0 0 0 4000 FF7F 10000 43FFF FF80 10 FF90 FFFF

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/*******************************************************************************
* in430.h -
*
* Copyright (C) 2003-2020 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
/* 1.210 */
#ifndef __IN430_H__
#define __IN430_H__
/* Definitions for projects using the GNU C/C++ compiler */
#if !defined(__ASSEMBLER__)
/* Definitions of things which are intrinsics with IAR and CCS, but which don't
appear to be intrinsics with the GCC compiler */
/* The data type used to hold interrupt state */
typedef unsigned int __istate_t;
#define _no_operation() __asm__ __volatile__ ("nop")
#define _get_interrupt_state() \
({ \
unsigned int __x; \
__asm__ __volatile__( \
"mov SR, %0" \
: "=r" ((unsigned int) __x) \
:); \
__x; \
})
#if defined(__MSP430_HAS_MSP430XV2_CPU__) || defined(__MSP430_HAS_MSP430X_CPU__)
#define _set_interrupt_state(x) \
({ \
__asm__ __volatile__ ("nop { mov %0, SR { nop" \
: : "ri"((unsigned int) x) \
);\
})
#define _enable_interrupts() __asm__ __volatile__ ("nop { eint { nop")
#define _bis_SR_register(x) \
__asm__ __volatile__ ("nop { bis.w %0, SR { nop" \
: : "ri"((unsigned int) x) \
)
#else
#define _set_interrupt_state(x) \
({ \
__asm__ __volatile__ ("mov %0, SR { nop" \
: : "ri"((unsigned int) x) \
);\
})
#define _enable_interrupts() __asm__ __volatile__ ("eint")
#define _bis_SR_register(x) \
__asm__ __volatile__ ("bis.w %0, SR" \
: : "ri"((unsigned int) x) \
)
#endif
#define _disable_interrupts() __asm__ __volatile__ ("dint { nop")
#define _bic_SR_register(x) \
__asm__ __volatile__ ("bic.w %0, SR { nop" \
: : "ri"((unsigned int) x) \
)
#define _get_SR_register() \
({ \
unsigned int __x; \
__asm__ __volatile__( \
"mov SR, %0" \
: "=r" ((unsigned int) __x) \
:); \
__x; \
})
#define _swap_bytes(x) \
({ \
unsigned int __dst = x; \
__asm__ __volatile__( \
"swpb %0" \
: "+r" ((unsigned int) __dst) \
:); \
__dst; \
})
/* Alternative names for GCC built-ins */
#define _bic_SR_register_on_exit(x) __bic_SR_register_on_exit(x)
#define _bis_SR_register_on_exit(x) __bis_SR_register_on_exit(x)
/* Additional intrinsics provided for IAR/CCS compatibility */
#define _bcd_add_short(x,y) \
({ \
unsigned short __z = ((unsigned short) y); \
__asm__ __volatile__( \
"clrc \n\t" \
"dadd.w %1, %0" \
: "+r" ((unsigned short) __z) \
: "ri" ((unsigned short) x) \
); \
__z; \
})
#define __bcd_add_short(x,y) _bcd_add_short(x,y)
#define _bcd_add_long(x,y) \
({ \
unsigned long __z = ((unsigned long) y); \
__asm__ __volatile__( \
"clrc \n\t" \
"dadd.w %L1, %L0 \n\t" \
"dadd.w %H1, %H0" \
: "+r" ((unsigned long) __z) \
: "ri" ((unsigned long) x) \
); \
__z; \
})
#define __bcd_add_long(x,y) _bcd_add_long(x,y)
#define _get_SP_register() \
({ \
unsigned int __x; \
__asm__ __volatile__( \
"mov SP, %0" \
: "=r" ((unsigned int) __x) \
:); \
__x; \
})
#define __get_SP_register() _get_SP_register()
#define _set_SP_register(x) \
({ \
__asm__ __volatile__ ("mov %0, SP" \
: : "ri"((unsigned int) x) \
);\
})
#define __set_SP_register(x) _set_SP_register(x)
#define _data16_write_addr(addr,src) \
({ \
unsigned long __src = src; \
__asm__ __volatile__ ( \
"movx.a %1, 0(%0)" \
: : "r"((unsigned int) addr), "m"((unsigned long) __src) \
); \
})
#define __data16_write_addr(addr,src) _data16_write_addr(addr,src)
#define _data16_read_addr(addr) \
({ \
unsigned long __dst; \
__asm__ __volatile__ ( \
"movx.a @%1, %0" \
: "=m"((unsigned long) __dst) \
: "r"((unsigned int) addr) \
); \
__dst; \
})
#define __data16_read_addr(addr) _data16_read_addr(addr)
#define _data20_write_char(addr,src) \
({ \
unsigned int __tmp; \
unsigned long __addr = addr; \
__asm__ __volatile__ ( \
"movx.a %1, %0 \n\t" \
"mov.b %2, 0(%0)" \
: "=&r"((unsigned int) __tmp) \
: "m"((unsigned long) __addr), "ri"((char) src) \
); \
})
#define __data20_write_char(addr,src) _data20_write_char(addr,src)
#define _data20_read_char(addr) \
({ \
char __dst; \
unsigned int __tmp; \
unsigned long __addr = addr; \
__asm__ __volatile__ ( \
"movx.a %2, %1 \n\t" \
"mov.b 0(%1), %0" \
: "=r"((char) __dst), "=&r"((unsigned int) __tmp) \
: "m"((unsigned long) __addr) \
); \
__dst ; \
})
#define __data20_read_char(addr) _data20_read_char(addr)
#define _data20_write_short(addr,src) \
({ \
unsigned int __tmp; \
unsigned long __addr = addr; \
__asm__ __volatile__ ( \
"movx.a %1, %0 \n\t" \
"mov.w %2, 0(%0)" \
: "=&r"((unsigned int) __tmp) \
: "m"((unsigned long) __addr), "ri"((short) src) \
); \
})
#define __data20_write_short(addr,src) _data20_write_short(addr,src)
#define _data20_read_short(addr) \
({ \
short __dst; \
unsigned int __tmp; \
unsigned long __addr = addr; \
__asm__ __volatile__ ( \
"movx.a %2, %1 \n\t" \
"mov.w 0(%1), %0" \
: "=r"((short) __dst), "=&r"((unsigned int) __tmp) \
: "m"((unsigned long) __addr) \
); \
__dst ; \
})
#define __data20_read_short(addr) _data20_read_short(addr)
#define _data20_write_long(addr,src) \
({ \
unsigned int __tmp; \
unsigned long __addr = addr; \
__asm__ __volatile__ ( \
"movx.a %1, %0 \n\t" \
"mov.w %L2, 0(%0) \n\t" \
"mov.w %H2, 2(%0)" \
: "=&r"((unsigned int) __tmp) \
: "m"((unsigned long) __addr), "ri"((long) src) \
); \
})
#define __data20_write_long(addr,src) _data20_write_long(addr,src)
#define _data20_read_long(addr) \
({ \
long __dst; \
unsigned int __tmp; \
unsigned long __addr = addr; \
__asm__ __volatile__ ( \
"movx.a %2, %1 \n\t" \
"mov.w 0(%1), %L0 \n\t" \
"mov.w 2(%1), %H0" \
: "=r"((long) __dst), "=&r"((unsigned int) __tmp) \
: "m"((unsigned long) __addr) \
); \
__dst ; \
})
#define __data20_read_long(addr) _data20_read_long(addr)
#define _low_power_mode_0() _bis_SR_register(0x18)
#define _low_power_mode_1() _bis_SR_register(0x58)
#define _low_power_mode_2() _bis_SR_register(0x98)
#define _low_power_mode_3() _bis_SR_register(0xD8)
#define _low_power_mode_4() _bis_SR_register(0xF8)
#define _low_power_mode_off_on_exit() _bic_SR_register_on_exit(0xF0)
#define __low_power_mode_0() _low_power_mode_0()
#define __low_power_mode_1() _low_power_mode_1()
#define __low_power_mode_2() _low_power_mode_2()
#define __low_power_mode_3() _low_power_mode_3()
#define __low_power_mode_4() _low_power_mode_4()
#define __low_power_mode_off_on_exit() _low_power_mode_off_on_exit()
#define _even_in_range(x,y) (x)
#define __even_in_range(x,y) _even_in_range(x,y)
/* Define some alternative names for the intrinsics, which have been used
in the various versions of IAR and GCC */
#define __no_operation() _no_operation()
#define __get_interrupt_state() _get_interrupt_state()
#define __set_interrupt_state(x) _set_interrupt_state(x)
#define __enable_interrupt() _enable_interrupts()
#define __disable_interrupt() _disable_interrupts()
#define __bic_SR_register(x) _bic_SR_register(x)
#define __bis_SR_register(x) _bis_SR_register(x)
#define __get_SR_register() _get_SR_register()
#define __swap_bytes(x) _swap_bytes(x)
#define __nop() _no_operation()
#define __eint() _enable_interrupts()
#define __dint() _disable_interrupts()
#define _NOP() _no_operation()
#define _EINT() _enable_interrupts()
#define _DINT() _disable_interrupts()
#define _BIC_SR(x) _bic_SR_register(x)
#define _BIC_SR_IRQ(x) _bic_SR_register_on_exit(x)
#define _BIS_SR(x) _bis_SR_register(x)
#define _BIS_SR_IRQ(x) _bis_SR_register_on_exit(x)
#define _BIS_NMI_IE1(x) _bis_nmi_ie1(x)
#define _SWAP_BYTES(x) _swap_bytes(x)
#define __no_init __attribute__((noinit))
#endif /* !defined _GNU_ASSEMBLER_ */
#endif /* __IN430_H__ */

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cpu/msp430_common/vendor/msp430-gcc-support-files/include/iomacros.h vendored Normal file
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/*******************************************************************************
* iomacros.h -
*
* Copyright (C) 2003-2020 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
/* 1.210 */
#if !defined(_IOMACROS_H_)
#define _IOMACROS_H_
#if defined(__ASSEMBLER__)
/* Definitions for assembly compilation using the GNU assembler */
#define sfrb(x,x_) x=x_
#define sfrw(x,x_) x=x_
#define sfra(x,x_) x=x_
#define sfrl(x,x_) x=x_
#define const_sfrb(x,x_) x=x_
#define const_sfrw(x,x_) x=x_
#define const_sfra(x,x_) x=x_
#define const_sfrl(x,x_) x=x_
#define sfr_b(x)
#define sfr_w(x)
#define sfr_a(x)
#define sfr_l(x)
#else
#define sfr_b(x) extern volatile unsigned char x
#define sfr_w(x) extern volatile unsigned int x
#define sfr_a(x) extern volatile unsigned long int x
#define sfr_l(x) extern volatile unsigned long int x
#define sfrb_(x,x_) extern volatile unsigned char x __asm__(#x_)
#define sfrw_(x,x_) extern volatile unsigned int x __asm__(#x_)
#define sfra_(x,x_) extern volatile unsigned long int x __asm__(#x_)
#define sfrl_(x,x_) extern volatile unsigned long int x __asm__(#x_)
#define sfrb(x,x_) sfrb_(x,x_)
#define sfrw(x,x_) sfrw_(x,x_)
#define sfra(x,x_) sfra_(x,x_)
#define sfrl(x,x_) sfrl_(x,x_)
#define const_sfrb(x,x_) const sfrb_(x,x_)
#define const_sfrw(x,x_) const sfrw_(x,x_)
#define const_sfra(x,x_) const sfra_(x,x_)
#define const_sfrl(x,x_) const sfrl_(x,x_)
#define __interrupt __attribute__((__interrupt__))
#define __interrupt_vec(vec) __attribute__((interrupt(vec)))
#endif /* defined(__ASSEMBLER__) */
#endif /* _IOMACROS_H_ */

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cpu/msp430_common/vendor/msp430-gcc-support-files/include/msp430.h vendored Normal file
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cpu/msp430_common/vendor/msp430-gcc-support-files/include/msp430f1611.h vendored Normal file
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/* ============================================================================ */
/* Copyright (c) 2020, Texas Instruments Incorporated */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following conditions */
/* are met: */
/* */
/* * Redistributions of source code must retain the above copyright */
/* notice, this list of conditions and the following disclaimer. */
/* */
/* * Redistributions in binary form must reproduce the above copyright */
/* notice, this list of conditions and the following disclaimer in the */
/* documentation and/or other materials provided with the distribution. */
/* */
/* * Neither the name of Texas Instruments Incorporated nor the names of */
/* its contributors may be used to endorse or promote products derived */
/* from this software without specific prior written permission. */
/* */
/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */
/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */
/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */
/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */
/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */
/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */
/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */
/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */
/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */
/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ============================================================================ */
/* This file supports MSP430F1611 devices. */
/* Version: 1.210 */
/* Default linker script, for normal executables */
OUTPUT_ARCH(msp430)
ENTRY(_start)
MEMORY {
SFR : ORIGIN = 0x0000, LENGTH = 0x0010 /* END=0x0010, size 16 */
RAM : ORIGIN = 0x1100, LENGTH = 0x2800 /* END=0x38FF, size 10240 */
RAM_MIRROR : ORIGIN = 0x0200, LENGTH = 0x0800
INFOMEM : ORIGIN = 0x1000, LENGTH = 0x0100 /* END=0x10FF, size 256 as 2 128-byte segments */
INFOA : ORIGIN = 0x1080, LENGTH = 0x0080 /* END=0x10FF, size 128 */
INFOB : ORIGIN = 0x1000, LENGTH = 0x0080 /* END=0x107F, size 128 */
ROM (rx) : ORIGIN = 0x4000, LENGTH = 0xBFE0 /* END=0xFFDF, size 49120 */
VECT1 : ORIGIN = 0xFFE0, LENGTH = 0x0002
VECT2 : ORIGIN = 0xFFE2, LENGTH = 0x0002
VECT3 : ORIGIN = 0xFFE4, LENGTH = 0x0002
VECT4 : ORIGIN = 0xFFE6, LENGTH = 0x0002
VECT5 : ORIGIN = 0xFFE8, LENGTH = 0x0002
VECT6 : ORIGIN = 0xFFEA, LENGTH = 0x0002
VECT7 : ORIGIN = 0xFFEC, LENGTH = 0x0002
VECT8 : ORIGIN = 0xFFEE, LENGTH = 0x0002
VECT9 : ORIGIN = 0xFFF0, LENGTH = 0x0002
VECT10 : ORIGIN = 0xFFF2, LENGTH = 0x0002
VECT11 : ORIGIN = 0xFFF4, LENGTH = 0x0002
VECT12 : ORIGIN = 0xFFF6, LENGTH = 0x0002
VECT13 : ORIGIN = 0xFFF8, LENGTH = 0x0002
VECT14 : ORIGIN = 0xFFFA, LENGTH = 0x0002
VECT15 : ORIGIN = 0xFFFC, LENGTH = 0x0002
RESETVEC : ORIGIN = 0xFFFE, LENGTH = 0x0002
}
SECTIONS
{
__interrupt_vector_1 : { KEEP (*(__interrupt_vector_1 )) KEEP (*(__interrupt_vector_dacdma)) } > VECT1
__interrupt_vector_2 : { KEEP (*(__interrupt_vector_2 )) KEEP (*(__interrupt_vector_port2)) } > VECT2
__interrupt_vector_3 : { KEEP (*(__interrupt_vector_3 )) KEEP (*(__interrupt_vector_usart1tx)) } > VECT3
__interrupt_vector_4 : { KEEP (*(__interrupt_vector_4 )) KEEP (*(__interrupt_vector_usart1rx)) } > VECT4
__interrupt_vector_5 : { KEEP (*(__interrupt_vector_5 )) KEEP (*(__interrupt_vector_port1)) } > VECT5
__interrupt_vector_6 : { KEEP (*(__interrupt_vector_6 )) KEEP (*(__interrupt_vector_timera1)) } > VECT6
__interrupt_vector_7 : { KEEP (*(__interrupt_vector_7 )) KEEP (*(__interrupt_vector_timera0)) } > VECT7
__interrupt_vector_8 : { KEEP (*(__interrupt_vector_8 )) KEEP (*(__interrupt_vector_adc12)) } > VECT8
__interrupt_vector_9 : { KEEP (*(__interrupt_vector_9 )) KEEP (*(__interrupt_vector_usart0tx)) } > VECT9
__interrupt_vector_10 : { KEEP (*(__interrupt_vector_10)) KEEP (*(__interrupt_vector_usart0rx)) } > VECT10
__interrupt_vector_11 : { KEEP (*(__interrupt_vector_11)) KEEP (*(__interrupt_vector_wdt)) } > VECT11
__interrupt_vector_12 : { KEEP (*(__interrupt_vector_12)) KEEP (*(__interrupt_vector_comparatora)) } > VECT12
__interrupt_vector_13 : { KEEP (*(__interrupt_vector_13)) KEEP (*(__interrupt_vector_timerb1)) } > VECT13
__interrupt_vector_14 : { KEEP (*(__interrupt_vector_14)) KEEP (*(__interrupt_vector_timerb0)) } > VECT14
__interrupt_vector_15 : { KEEP (*(__interrupt_vector_15)) KEEP (*(__interrupt_vector_nmi)) } > VECT15
__reset_vector :
{
KEEP (*(__interrupt_vector_16))
KEEP (*(__interrupt_vector_reset))
KEEP (*(.resetvec))
} > RESETVEC
.rodata :
{
. = ALIGN(2);
*(.plt)
*(.rodata .rodata.* .gnu.linkonce.r.* .const .const:*)
*(.rodata1)
KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)
} > ROM
/* Note: This is a separate .rodata section for sections which are
read only but which older linkers treat as read-write.
This prevents older linkers from marking the entire .rodata
section as read-write. */
.rodata2 :
{
. = ALIGN(2);
PROVIDE (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE (__preinit_array_end = .);
. = ALIGN(2);
PROVIDE (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
PROVIDE (__init_array_end = .);
. = ALIGN(2);
PROVIDE (__fini_array_start = .);
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
PROVIDE (__fini_array_end = .);
. = ALIGN(2);
*(.eh_frame_hdr)
KEEP (*(.eh_frame))
/* gcc uses crtbegin.o to find the start of the constructors, so
we make sure it is first. Because this is a wildcard, it
doesn't matter if the user does not actually link against
crtbegin.o; the linker won't look for a file to match a
wildcard. The wildcard also means that it doesn't matter which
directory crtbegin.o is in. */
KEEP (*crtbegin*.o(.ctors))
/* We don't want to include the .ctor section from from the
crtend.o file until after the sorted ctors. The .ctor section
from the crtend file contains the end of ctors marker and it
must be last */
KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
KEEP (*crtbegin*.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
} > ROM
.text :
{
. = ALIGN(2);
PROVIDE (_start = .);
KEEP (*(SORT(.crt_*)))
*(.lowtext .text .stub .text.* .gnu.linkonce.t.* .text:*)
KEEP (*(.text.*personality*))
/* .gnu.warning sections are handled specially by elf32.em. */
*(.gnu.warning)
*(.interp .hash .dynsym .dynstr .gnu.version*)
PROVIDE (__etext = .);
PROVIDE (_etext = .);
PROVIDE (etext = .);
. = ALIGN(2);
KEEP (*(.init))
KEEP (*(.fini))
KEEP (*(.tm_clone_table))
} > ROM
.data :
{
. = ALIGN(2);
PROVIDE (__datastart = .);
KEEP (*(.jcr))
*(.data.rel.ro.local) *(.data.rel.ro*)
*(.dynamic)
*(.data .data.* .gnu.linkonce.d.*)
KEEP (*(.gnu.linkonce.d.*personality*))
SORT(CONSTRUCTORS)
*(.data1)
*(.got.plt) *(.got)
/* We want the small data sections together, so single-instruction offsets
can access them all, and initialized data all before uninitialized, so
we can shorten the on-disk segment size. */
. = ALIGN(2);
*(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1)
. = ALIGN(2);
_edata = .;
PROVIDE (edata = .);
PROVIDE (__dataend = .);
} > RAM AT>ROM
/* Note that crt0 assumes this is a multiple of two; all the
start/stop symbols are also assumed word-aligned. */
PROVIDE(__romdatastart = LOADADDR(.data));
PROVIDE (__romdatacopysize = SIZEOF(.data));
.bss :
{
. = ALIGN(2);
PROVIDE (__bssstart = .);
*(.dynbss)
*(.sbss .sbss.*)
*(.bss .bss.* .gnu.linkonce.b.*)
. = ALIGN(2);
*(COMMON)
PROVIDE (__bssend = .);
} > RAM
PROVIDE (__bsssize = SIZEOF(.bss));
/* This section contains data that is not initialised during load
or application reset. */
.noinit (NOLOAD) :
{
. = ALIGN(2);
PROVIDE (__noinit_start = .);
*(.noinit)
. = ALIGN(2);
PROVIDE (__noinit_end = .);
end = .;
} > RAM
/* We create this section so that "end" will always be in the
RAM region (matching .stack below), even if the .bss
section is empty. */
.heap (NOLOAD) :
{
. = ALIGN(2);
__heap_start__ = .;
_end = __heap_start__;
PROVIDE (end = .);
KEEP (*(.heap))
_end = .;
PROVIDE (end = .);
/* This word is here so that the section is not empty, and thus
not discarded by the linker. The actual value does not matter
and is ignored. */
LONG(0);
__heap_end__ = .;
__HeapLimit = __heap_end__;
} > RAM
/* WARNING: Do not place anything in RAM here.
The heap section must be the last section in RAM and the stack
section must be placed at the very end of the RAM region. */
.stack (ORIGIN (RAM) + LENGTH(RAM)) :
{
PROVIDE (__stack = .);
*(.stack)
}
.infoA : {} > INFOA /* MSP430 INFO FLASH MEMORY SEGMENTS */
.infoB : {} > INFOB
.MSP430.attributes 0 :
{
KEEP (*(.MSP430.attributes))
KEEP (*(.gnu.attributes))
KEEP (*(__TI_build_attributes))
}
/* The rest are all not normally part of the runtime image. */
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end ) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
/DISCARD/ : { *(.note.GNU-stack) }
}
/****************************************************************************/
/* Include peripherals memory map */
/****************************************************************************/
INCLUDE msp430f1611_symbols.ld

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cpu/msp430_common/vendor/msp430-gcc-support-files/include/msp430f1611_symbols.ld vendored Normal file
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/* ============================================================================ */
/* Copyright (c) 2020, Texas Instruments Incorporated */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following conditions */
/* are met: */
/* */
/* * Redistributions of source code must retain the above copyright */
/* notice, this list of conditions and the following disclaimer. */
/* */
/* * Redistributions in binary form must reproduce the above copyright */
/* notice, this list of conditions and the following disclaimer in the */
/* documentation and/or other materials provided with the distribution. */
/* */
/* * Neither the name of Texas Instruments Incorporated nor the names of */
/* its contributors may be used to endorse or promote products derived */
/* from this software without specific prior written permission. */
/* */
/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */
/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */
/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */
/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */
/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */
/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */
/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */
/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */
/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */
/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ============================================================================ */
/* This file supports MSP430F1611 devices. */
/* Version: 1.210 */
/************************************************************
* STANDARD BITS
************************************************************/
/************************************************************
* STATUS REGISTER BITS
************************************************************/
/************************************************************
* PERIPHERAL FILE MAP
************************************************************/
/************************************************************
* SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS
************************************************************/
PROVIDE(IE1 = 0x0000);
PROVIDE(IFG1 = 0x0002);
PROVIDE(ME1 = 0x0004);
PROVIDE(IE2 = 0x0001);
PROVIDE(IFG2 = 0x0003);
PROVIDE(ME2 = 0x0005);
/************************************************************
* WATCHDOG TIMER
************************************************************/
PROVIDE(WDTCTL = 0x0120);
/************************************************************
* HARDWARE MULTIPLIER
************************************************************/
PROVIDE(MPY = 0x0130);
PROVIDE(MPYS = 0x0132);
PROVIDE(MAC = 0x0134);
PROVIDE(MACS = 0x0136);
PROVIDE(OP2 = 0x0138);
PROVIDE(RESLO = 0x013A);
PROVIDE(RESHI = 0x013C);
PROVIDE(SUMEXT = 0x013E);
/************************************************************
* DIGITAL I/O Port1/2
************************************************************/
PROVIDE(P1IN = 0x0020);
PROVIDE(P1OUT = 0x0021);
PROVIDE(P1DIR = 0x0022);
PROVIDE(P1IFG = 0x0023);
PROVIDE(P1IES = 0x0024);
PROVIDE(P1IE = 0x0025);
PROVIDE(P1SEL = 0x0026);
PROVIDE(P2IN = 0x0028);
PROVIDE(P2OUT = 0x0029);
PROVIDE(P2DIR = 0x002A);
PROVIDE(P2IFG = 0x002B);
PROVIDE(P2IES = 0x002C);
PROVIDE(P2IE = 0x002D);
PROVIDE(P2SEL = 0x002E);
/************************************************************
* DIGITAL I/O Port3/4
************************************************************/
PROVIDE(P3IN = 0x0018);
PROVIDE(P3OUT = 0x0019);
PROVIDE(P3DIR = 0x001A);
PROVIDE(P3SEL = 0x001B);
PROVIDE(P4IN = 0x001C);
PROVIDE(P4OUT = 0x001D);
PROVIDE(P4DIR = 0x001E);
PROVIDE(P4SEL = 0x001F);
/************************************************************
* DIGITAL I/O Port5/6
************************************************************/
PROVIDE(P5IN = 0x0030);
PROVIDE(P5OUT = 0x0031);
PROVIDE(P5DIR = 0x0032);
PROVIDE(P5SEL = 0x0033);
PROVIDE(P6IN = 0x0034);
PROVIDE(P6OUT = 0x0035);
PROVIDE(P6DIR = 0x0036);
PROVIDE(P6SEL = 0x0037);
/************************************************************
* USART
************************************************************/
/************************************************************
* USART 0
************************************************************/
PROVIDE(U0CTL = 0x0070);
PROVIDE(U0TCTL = 0x0071);
PROVIDE(U0RCTL = 0x0072);
PROVIDE(U0MCTL = 0x0073);
PROVIDE(U0BR0 = 0x0074);
PROVIDE(U0BR1 = 0x0075);
PROVIDE(U0RXBUF = 0x0076);
PROVIDE(U0TXBUF = 0x0077);
/************************************************************
* USART 1
************************************************************/
PROVIDE(U1CTL = 0x0078);
PROVIDE(U1TCTL = 0x0079);
PROVIDE(U1RCTL = 0x007A);
PROVIDE(U1MCTL = 0x007B);
PROVIDE(U1BR0 = 0x007C);
PROVIDE(U1BR1 = 0x007D);
PROVIDE(U1RXBUF = 0x007E);
PROVIDE(U1TXBUF = 0x007F);
/************************************************************
* USART0 I2C
************************************************************/
PROVIDE(I2CIE = 0x0050);
PROVIDE(I2CIFG = 0x0051);
PROVIDE(I2CNDAT = 0x0052);
PROVIDE(I2CTCTL = 0x0071);
PROVIDE(I2CDCTL = 0x0072);
PROVIDE(I2CPSC = 0x0073);
PROVIDE(I2CSCLH = 0x0074);
PROVIDE(I2CSCLL = 0x0075);
PROVIDE(I2CDRB = 0x0076);
PROVIDE(I2CDRW = 0x0076);
PROVIDE(I2COA = 0x0118);
PROVIDE(I2CSA = 0x011A);
PROVIDE(I2CIV = 0x011C);
/************************************************************
* Timer A3
************************************************************/
PROVIDE(TAIV = 0x012E);
PROVIDE(TACTL = 0x0160);
PROVIDE(TACCTL0 = 0x0162);
PROVIDE(TACCTL1 = 0x0164);
PROVIDE(TACCTL2 = 0x0166);
PROVIDE(TAR = 0x0170);
PROVIDE(TACCR0 = 0x0172);
PROVIDE(TACCR1 = 0x0174);
PROVIDE(TACCR2 = 0x0176);
/************************************************************
* Timer B7
************************************************************/
PROVIDE(TBIV = 0x011E);
PROVIDE(TBCTL = 0x0180);
PROVIDE(TBCCTL0 = 0x0182);
PROVIDE(TBCCTL1 = 0x0184);
PROVIDE(TBCCTL2 = 0x0186);
PROVIDE(TBCCTL3 = 0x0188);
PROVIDE(TBCCTL4 = 0x018A);
PROVIDE(TBCCTL5 = 0x018C);
PROVIDE(TBCCTL6 = 0x018E);
PROVIDE(TBR = 0x0190);
PROVIDE(TBCCR0 = 0x0192);
PROVIDE(TBCCR1 = 0x0194);
PROVIDE(TBCCR2 = 0x0196);
PROVIDE(TBCCR3 = 0x0198);
PROVIDE(TBCCR4 = 0x019A);
PROVIDE(TBCCR5 = 0x019C);
PROVIDE(TBCCR6 = 0x019E);
/************************************************************
* Basic Clock Module
************************************************************/
PROVIDE(DCOCTL = 0x0056);
PROVIDE(BCSCTL1 = 0x0057);
PROVIDE(BCSCTL2 = 0x0058);
/************************************************************
* Brown-Out, Supply Voltage Supervision (SVS)
************************************************************/
PROVIDE(SVSCTL = 0x0055);
/*************************************************************
* Flash Memory
*************************************************************/
PROVIDE(FCTL1 = 0x0128);
PROVIDE(FCTL2 = 0x012A);
PROVIDE(FCTL3 = 0x012C);
/************************************************************
* Comparator A
************************************************************/
PROVIDE(CACTL1 = 0x0059);
PROVIDE(CACTL2 = 0x005A);
PROVIDE(CAPD = 0x005B);
/************************************************************
* ADC12
************************************************************/
PROVIDE(ADC12CTL0 = 0x01A0);
PROVIDE(ADC12CTL1 = 0x01A2);
PROVIDE(ADC12IFG = 0x01A4);
PROVIDE(ADC12IE = 0x01A6);
PROVIDE(ADC12IV = 0x01A8);
PROVIDE(ADC12MEM0 = 0x0140);
PROVIDE(ADC12MEM1 = 0x0142);
PROVIDE(ADC12MEM2 = 0x0144);
PROVIDE(ADC12MEM3 = 0x0146);
PROVIDE(ADC12MEM4 = 0x0148);
PROVIDE(ADC12MEM5 = 0x014A);
PROVIDE(ADC12MEM6 = 0x014C);
PROVIDE(ADC12MEM7 = 0x014E);
PROVIDE(ADC12MEM8 = 0x0150);
PROVIDE(ADC12MEM9 = 0x0152);
PROVIDE(ADC12MEM10 = 0x0154);
PROVIDE(ADC12MEM11 = 0x0156);
PROVIDE(ADC12MEM12 = 0x0158);
PROVIDE(ADC12MEM13 = 0x015A);
PROVIDE(ADC12MEM14 = 0x015C);
PROVIDE(ADC12MEM15 = 0x015E);
PROVIDE(ADC12MCTL0 = 0x0080);
PROVIDE(ADC12MCTL1 = 0x0081);
PROVIDE(ADC12MCTL2 = 0x0082);
PROVIDE(ADC12MCTL3 = 0x0083);
PROVIDE(ADC12MCTL4 = 0x0084);
PROVIDE(ADC12MCTL5 = 0x0085);
PROVIDE(ADC12MCTL6 = 0x0086);
PROVIDE(ADC12MCTL7 = 0x0087);
PROVIDE(ADC12MCTL8 = 0x0088);
PROVIDE(ADC12MCTL9 = 0x0089);
PROVIDE(ADC12MCTL10 = 0x008A);
PROVIDE(ADC12MCTL11 = 0x008B);
PROVIDE(ADC12MCTL12 = 0x008C);
PROVIDE(ADC12MCTL13 = 0x008D);
PROVIDE(ADC12MCTL14 = 0x008E);
PROVIDE(ADC12MCTL15 = 0x008F);
/************************************************************
* DAC12
************************************************************/
PROVIDE(DAC12_0CTL = 0x01C0);
PROVIDE(DAC12_1CTL = 0x01C2);
PROVIDE(DAC12_0DAT = 0x01C8);
PROVIDE(DAC12_1DAT = 0x01CA);
/************************************************************
* DMA
************************************************************/
PROVIDE(DMACTL0 = 0x0122);
PROVIDE(DMACTL1 = 0x0124);
PROVIDE(DMA0CTL = 0x01E0);
PROVIDE(DMA1CTL = 0x01E8);
PROVIDE(DMA2CTL = 0x01F0);
PROVIDE(DMA0SA = 0x01E2);
PROVIDE(DMA0DA = 0x01E4);
PROVIDE(DMA0SZ = 0x01E6);
PROVIDE(DMA1SA = 0x01EA);
PROVIDE(DMA1DA = 0x01EC);
PROVIDE(DMA1SZ = 0x01EE);
PROVIDE(DMA2SA = 0x01F2);
PROVIDE(DMA2DA = 0x01F4);
PROVIDE(DMA2SZ = 0x01F6);
/************************************************************
* Interrupt Vectors (offset from 0xFFE0)
************************************************************/
/************************************************************
* End of Modules
************************************************************/

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/* ============================================================================ */
/* Copyright (c) 2020, Texas Instruments Incorporated */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following conditions */
/* are met: */
/* */
/* * Redistributions of source code must retain the above copyright */
/* notice, this list of conditions and the following disclaimer. */
/* */
/* * Redistributions in binary form must reproduce the above copyright */
/* notice, this list of conditions and the following disclaimer in the */
/* documentation and/or other materials provided with the distribution. */
/* */
/* * Neither the name of Texas Instruments Incorporated nor the names of */
/* its contributors may be used to endorse or promote products derived */
/* from this software without specific prior written permission. */
/* */
/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */
/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */
/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */
/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */
/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */
/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */
/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */
/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */
/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */
/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ============================================================================ */
/* This file supports MSP430F1612 devices. */
/* Version: 1.210 */
/* Default linker script, for normal executables */
OUTPUT_ARCH(msp430)
ENTRY(_start)
MEMORY {
SFR : ORIGIN = 0x0000, LENGTH = 0x0010 /* END=0x0010, size 16 */
RAM : ORIGIN = 0x1100, LENGTH = 0x1400 /* END=0x24FF, size 5120 */
RAM_MIRROR : ORIGIN = 0x0200, LENGTH = 0x0800
INFOMEM : ORIGIN = 0x1000, LENGTH = 0x0100 /* END=0x10FF, size 256 as 2 128-byte segments */
INFOA : ORIGIN = 0x1080, LENGTH = 0x0080 /* END=0x10FF, size 128 */
INFOB : ORIGIN = 0x1000, LENGTH = 0x0080 /* END=0x107F, size 128 */
ROM (rx) : ORIGIN = 0x2500, LENGTH = 0xDAE0 /* END=0xFFDF, size 56032 */
VECT1 : ORIGIN = 0xFFE0, LENGTH = 0x0002
VECT2 : ORIGIN = 0xFFE2, LENGTH = 0x0002
VECT3 : ORIGIN = 0xFFE4, LENGTH = 0x0002
VECT4 : ORIGIN = 0xFFE6, LENGTH = 0x0002
VECT5 : ORIGIN = 0xFFE8, LENGTH = 0x0002
VECT6 : ORIGIN = 0xFFEA, LENGTH = 0x0002
VECT7 : ORIGIN = 0xFFEC, LENGTH = 0x0002
VECT8 : ORIGIN = 0xFFEE, LENGTH = 0x0002
VECT9 : ORIGIN = 0xFFF0, LENGTH = 0x0002
VECT10 : ORIGIN = 0xFFF2, LENGTH = 0x0002
VECT11 : ORIGIN = 0xFFF4, LENGTH = 0x0002
VECT12 : ORIGIN = 0xFFF6, LENGTH = 0x0002
VECT13 : ORIGIN = 0xFFF8, LENGTH = 0x0002
VECT14 : ORIGIN = 0xFFFA, LENGTH = 0x0002
VECT15 : ORIGIN = 0xFFFC, LENGTH = 0x0002
RESETVEC : ORIGIN = 0xFFFE, LENGTH = 0x0002
}
SECTIONS
{
__interrupt_vector_1 : { KEEP (*(__interrupt_vector_1 )) KEEP (*(__interrupt_vector_dacdma)) } > VECT1
__interrupt_vector_2 : { KEEP (*(__interrupt_vector_2 )) KEEP (*(__interrupt_vector_port2)) } > VECT2
__interrupt_vector_3 : { KEEP (*(__interrupt_vector_3 )) KEEP (*(__interrupt_vector_usart1tx)) } > VECT3
__interrupt_vector_4 : { KEEP (*(__interrupt_vector_4 )) KEEP (*(__interrupt_vector_usart1rx)) } > VECT4
__interrupt_vector_5 : { KEEP (*(__interrupt_vector_5 )) KEEP (*(__interrupt_vector_port1)) } > VECT5
__interrupt_vector_6 : { KEEP (*(__interrupt_vector_6 )) KEEP (*(__interrupt_vector_timera1)) } > VECT6
__interrupt_vector_7 : { KEEP (*(__interrupt_vector_7 )) KEEP (*(__interrupt_vector_timera0)) } > VECT7
__interrupt_vector_8 : { KEEP (*(__interrupt_vector_8 )) KEEP (*(__interrupt_vector_adc12)) } > VECT8
__interrupt_vector_9 : { KEEP (*(__interrupt_vector_9 )) KEEP (*(__interrupt_vector_usart0tx)) } > VECT9
__interrupt_vector_10 : { KEEP (*(__interrupt_vector_10)) KEEP (*(__interrupt_vector_usart0rx)) } > VECT10
__interrupt_vector_11 : { KEEP (*(__interrupt_vector_11)) KEEP (*(__interrupt_vector_wdt)) } > VECT11
__interrupt_vector_12 : { KEEP (*(__interrupt_vector_12)) KEEP (*(__interrupt_vector_comparatora)) } > VECT12
__interrupt_vector_13 : { KEEP (*(__interrupt_vector_13)) KEEP (*(__interrupt_vector_timerb1)) } > VECT13
__interrupt_vector_14 : { KEEP (*(__interrupt_vector_14)) KEEP (*(__interrupt_vector_timerb0)) } > VECT14
__interrupt_vector_15 : { KEEP (*(__interrupt_vector_15)) KEEP (*(__interrupt_vector_nmi)) } > VECT15
__reset_vector :
{
KEEP (*(__interrupt_vector_16))
KEEP (*(__interrupt_vector_reset))
KEEP (*(.resetvec))
} > RESETVEC
.rodata :
{
. = ALIGN(2);
*(.plt)
*(.rodata .rodata.* .gnu.linkonce.r.* .const .const:*)
*(.rodata1)
KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)
} > ROM
/* Note: This is a separate .rodata section for sections which are
read only but which older linkers treat as read-write.
This prevents older linkers from marking the entire .rodata
section as read-write. */
.rodata2 :
{
. = ALIGN(2);
PROVIDE (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE (__preinit_array_end = .);
. = ALIGN(2);
PROVIDE (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
PROVIDE (__init_array_end = .);
. = ALIGN(2);
PROVIDE (__fini_array_start = .);
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
PROVIDE (__fini_array_end = .);
. = ALIGN(2);
*(.eh_frame_hdr)
KEEP (*(.eh_frame))
/* gcc uses crtbegin.o to find the start of the constructors, so
we make sure it is first. Because this is a wildcard, it
doesn't matter if the user does not actually link against
crtbegin.o; the linker won't look for a file to match a
wildcard. The wildcard also means that it doesn't matter which
directory crtbegin.o is in. */
KEEP (*crtbegin*.o(.ctors))
/* We don't want to include the .ctor section from from the
crtend.o file until after the sorted ctors. The .ctor section
from the crtend file contains the end of ctors marker and it
must be last */
KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
KEEP (*crtbegin*.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
} > ROM
.text :
{
. = ALIGN(2);
PROVIDE (_start = .);
KEEP (*(SORT(.crt_*)))
*(.lowtext .text .stub .text.* .gnu.linkonce.t.* .text:*)
KEEP (*(.text.*personality*))
/* .gnu.warning sections are handled specially by elf32.em. */
*(.gnu.warning)
*(.interp .hash .dynsym .dynstr .gnu.version*)
PROVIDE (__etext = .);
PROVIDE (_etext = .);
PROVIDE (etext = .);
. = ALIGN(2);
KEEP (*(.init))
KEEP (*(.fini))
KEEP (*(.tm_clone_table))
} > ROM
.data :
{
. = ALIGN(2);
PROVIDE (__datastart = .);
KEEP (*(.jcr))
*(.data.rel.ro.local) *(.data.rel.ro*)
*(.dynamic)
*(.data .data.* .gnu.linkonce.d.*)
KEEP (*(.gnu.linkonce.d.*personality*))
SORT(CONSTRUCTORS)
*(.data1)
*(.got.plt) *(.got)
/* We want the small data sections together, so single-instruction offsets
can access them all, and initialized data all before uninitialized, so
we can shorten the on-disk segment size. */
. = ALIGN(2);
*(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1)
. = ALIGN(2);
_edata = .;
PROVIDE (edata = .);
PROVIDE (__dataend = .);
} > RAM AT>ROM
/* Note that crt0 assumes this is a multiple of two; all the
start/stop symbols are also assumed word-aligned. */
PROVIDE(__romdatastart = LOADADDR(.data));
PROVIDE (__romdatacopysize = SIZEOF(.data));
.bss :
{
. = ALIGN(2);
PROVIDE (__bssstart = .);
*(.dynbss)
*(.sbss .sbss.*)
*(.bss .bss.* .gnu.linkonce.b.*)
. = ALIGN(2);
*(COMMON)
PROVIDE (__bssend = .);
} > RAM
PROVIDE (__bsssize = SIZEOF(.bss));
/* This section contains data that is not initialised during load
or application reset. */
.noinit (NOLOAD) :
{
. = ALIGN(2);
PROVIDE (__noinit_start = .);
*(.noinit)
. = ALIGN(2);
PROVIDE (__noinit_end = .);
end = .;
} > RAM
/* We create this section so that "end" will always be in the
RAM region (matching .stack below), even if the .bss
section is empty. */
.heap (NOLOAD) :
{
. = ALIGN(2);
__heap_start__ = .;
_end = __heap_start__;
PROVIDE (end = .);
KEEP (*(.heap))
_end = .;
PROVIDE (end = .);
/* This word is here so that the section is not empty, and thus
not discarded by the linker. The actual value does not matter
and is ignored. */
LONG(0);
__heap_end__ = .;
__HeapLimit = __heap_end__;
} > RAM
/* WARNING: Do not place anything in RAM here.
The heap section must be the last section in RAM and the stack
section must be placed at the very end of the RAM region. */
.stack (ORIGIN (RAM) + LENGTH(RAM)) :
{
PROVIDE (__stack = .);
*(.stack)
}
.infoA : {} > INFOA /* MSP430 INFO FLASH MEMORY SEGMENTS */
.infoB : {} > INFOB
.MSP430.attributes 0 :
{
KEEP (*(.MSP430.attributes))
KEEP (*(.gnu.attributes))
KEEP (*(__TI_build_attributes))
}
/* The rest are all not normally part of the runtime image. */
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end ) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
/DISCARD/ : { *(.note.GNU-stack) }
}
/****************************************************************************/
/* Include peripherals memory map */
/****************************************************************************/
INCLUDE msp430f1612_symbols.ld

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/* ============================================================================ */
/* Copyright (c) 2020, Texas Instruments Incorporated */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following conditions */
/* are met: */
/* */
/* * Redistributions of source code must retain the above copyright */
/* notice, this list of conditions and the following disclaimer. */
/* */
/* * Redistributions in binary form must reproduce the above copyright */
/* notice, this list of conditions and the following disclaimer in the */
/* documentation and/or other materials provided with the distribution. */
/* */
/* * Neither the name of Texas Instruments Incorporated nor the names of */
/* its contributors may be used to endorse or promote products derived */
/* from this software without specific prior written permission. */
/* */
/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */
/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */
/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */
/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */
/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */
/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */
/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */
/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */
/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */
/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ============================================================================ */
/* This file supports MSP430F1612 devices. */
/* Version: 1.210 */
/************************************************************
* STANDARD BITS
************************************************************/
/************************************************************
* STATUS REGISTER BITS
************************************************************/
/************************************************************
* PERIPHERAL FILE MAP
************************************************************/
/************************************************************
* SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS
************************************************************/
PROVIDE(IE1 = 0x0000);
PROVIDE(IFG1 = 0x0002);
PROVIDE(ME1 = 0x0004);
PROVIDE(IE2 = 0x0001);
PROVIDE(IFG2 = 0x0003);
PROVIDE(ME2 = 0x0005);
/************************************************************
* WATCHDOG TIMER
************************************************************/
PROVIDE(WDTCTL = 0x0120);
/************************************************************
* HARDWARE MULTIPLIER
************************************************************/
PROVIDE(MPY = 0x0130);
PROVIDE(MPYS = 0x0132);
PROVIDE(MAC = 0x0134);
PROVIDE(MACS = 0x0136);
PROVIDE(OP2 = 0x0138);
PROVIDE(RESLO = 0x013A);
PROVIDE(RESHI = 0x013C);
PROVIDE(SUMEXT = 0x013E);
/************************************************************
* DIGITAL I/O Port1/2
************************************************************/
PROVIDE(P1IN = 0x0020);
PROVIDE(P1OUT = 0x0021);
PROVIDE(P1DIR = 0x0022);
PROVIDE(P1IFG = 0x0023);
PROVIDE(P1IES = 0x0024);
PROVIDE(P1IE = 0x0025);
PROVIDE(P1SEL = 0x0026);
PROVIDE(P2IN = 0x0028);
PROVIDE(P2OUT = 0x0029);
PROVIDE(P2DIR = 0x002A);
PROVIDE(P2IFG = 0x002B);
PROVIDE(P2IES = 0x002C);
PROVIDE(P2IE = 0x002D);
PROVIDE(P2SEL = 0x002E);
/************************************************************
* DIGITAL I/O Port3/4
************************************************************/
PROVIDE(P3IN = 0x0018);
PROVIDE(P3OUT = 0x0019);
PROVIDE(P3DIR = 0x001A);
PROVIDE(P3SEL = 0x001B);
PROVIDE(P4IN = 0x001C);
PROVIDE(P4OUT = 0x001D);
PROVIDE(P4DIR = 0x001E);
PROVIDE(P4SEL = 0x001F);
/************************************************************
* DIGITAL I/O Port5/6
************************************************************/
PROVIDE(P5IN = 0x0030);
PROVIDE(P5OUT = 0x0031);
PROVIDE(P5DIR = 0x0032);
PROVIDE(P5SEL = 0x0033);
PROVIDE(P6IN = 0x0034);
PROVIDE(P6OUT = 0x0035);
PROVIDE(P6DIR = 0x0036);
PROVIDE(P6SEL = 0x0037);
/************************************************************
* USART
************************************************************/
/************************************************************
* USART 0
************************************************************/
PROVIDE(U0CTL = 0x0070);
PROVIDE(U0TCTL = 0x0071);
PROVIDE(U0RCTL = 0x0072);
PROVIDE(U0MCTL = 0x0073);
PROVIDE(U0BR0 = 0x0074);
PROVIDE(U0BR1 = 0x0075);
PROVIDE(U0RXBUF = 0x0076);
PROVIDE(U0TXBUF = 0x0077);
/************************************************************
* USART 1
************************************************************/
PROVIDE(U1CTL = 0x0078);
PROVIDE(U1TCTL = 0x0079);
PROVIDE(U1RCTL = 0x007A);
PROVIDE(U1MCTL = 0x007B);
PROVIDE(U1BR0 = 0x007C);
PROVIDE(U1BR1 = 0x007D);
PROVIDE(U1RXBUF = 0x007E);
PROVIDE(U1TXBUF = 0x007F);
/************************************************************
* USART0 I2C
************************************************************/
PROVIDE(I2CIE = 0x0050);
PROVIDE(I2CIFG = 0x0051);
PROVIDE(I2CNDAT = 0x0052);
PROVIDE(I2CTCTL = 0x0071);
PROVIDE(I2CDCTL = 0x0072);
PROVIDE(I2CPSC = 0x0073);
PROVIDE(I2CSCLH = 0x0074);
PROVIDE(I2CSCLL = 0x0075);
PROVIDE(I2CDRB = 0x0076);
PROVIDE(I2CDRW = 0x0076);
PROVIDE(I2COA = 0x0118);
PROVIDE(I2CSA = 0x011A);
PROVIDE(I2CIV = 0x011C);
/************************************************************
* Timer A3
************************************************************/
PROVIDE(TAIV = 0x012E);
PROVIDE(TACTL = 0x0160);
PROVIDE(TACCTL0 = 0x0162);
PROVIDE(TACCTL1 = 0x0164);
PROVIDE(TACCTL2 = 0x0166);
PROVIDE(TAR = 0x0170);
PROVIDE(TACCR0 = 0x0172);
PROVIDE(TACCR1 = 0x0174);
PROVIDE(TACCR2 = 0x0176);
/************************************************************
* Timer B7
************************************************************/
PROVIDE(TBIV = 0x011E);
PROVIDE(TBCTL = 0x0180);
PROVIDE(TBCCTL0 = 0x0182);
PROVIDE(TBCCTL1 = 0x0184);
PROVIDE(TBCCTL2 = 0x0186);
PROVIDE(TBCCTL3 = 0x0188);
PROVIDE(TBCCTL4 = 0x018A);
PROVIDE(TBCCTL5 = 0x018C);
PROVIDE(TBCCTL6 = 0x018E);
PROVIDE(TBR = 0x0190);
PROVIDE(TBCCR0 = 0x0192);
PROVIDE(TBCCR1 = 0x0194);
PROVIDE(TBCCR2 = 0x0196);
PROVIDE(TBCCR3 = 0x0198);
PROVIDE(TBCCR4 = 0x019A);
PROVIDE(TBCCR5 = 0x019C);
PROVIDE(TBCCR6 = 0x019E);
/************************************************************
* Basic Clock Module
************************************************************/
PROVIDE(DCOCTL = 0x0056);
PROVIDE(BCSCTL1 = 0x0057);
PROVIDE(BCSCTL2 = 0x0058);
/************************************************************
* Brown-Out, Supply Voltage Supervision (SVS)
************************************************************/
PROVIDE(SVSCTL = 0x0055);
/*************************************************************
* Flash Memory
*************************************************************/
PROVIDE(FCTL1 = 0x0128);
PROVIDE(FCTL2 = 0x012A);
PROVIDE(FCTL3 = 0x012C);
/************************************************************
* Comparator A
************************************************************/
PROVIDE(CACTL1 = 0x0059);
PROVIDE(CACTL2 = 0x005A);
PROVIDE(CAPD = 0x005B);
/************************************************************
* ADC12
************************************************************/
PROVIDE(ADC12CTL0 = 0x01A0);
PROVIDE(ADC12CTL1 = 0x01A2);
PROVIDE(ADC12IFG = 0x01A4);
PROVIDE(ADC12IE = 0x01A6);
PROVIDE(ADC12IV = 0x01A8);
PROVIDE(ADC12MEM0 = 0x0140);
PROVIDE(ADC12MEM1 = 0x0142);
PROVIDE(ADC12MEM2 = 0x0144);
PROVIDE(ADC12MEM3 = 0x0146);
PROVIDE(ADC12MEM4 = 0x0148);
PROVIDE(ADC12MEM5 = 0x014A);
PROVIDE(ADC12MEM6 = 0x014C);
PROVIDE(ADC12MEM7 = 0x014E);
PROVIDE(ADC12MEM8 = 0x0150);
PROVIDE(ADC12MEM9 = 0x0152);
PROVIDE(ADC12MEM10 = 0x0154);
PROVIDE(ADC12MEM11 = 0x0156);
PROVIDE(ADC12MEM12 = 0x0158);
PROVIDE(ADC12MEM13 = 0x015A);
PROVIDE(ADC12MEM14 = 0x015C);
PROVIDE(ADC12MEM15 = 0x015E);
PROVIDE(ADC12MCTL0 = 0x0080);
PROVIDE(ADC12MCTL1 = 0x0081);
PROVIDE(ADC12MCTL2 = 0x0082);
PROVIDE(ADC12MCTL3 = 0x0083);
PROVIDE(ADC12MCTL4 = 0x0084);
PROVIDE(ADC12MCTL5 = 0x0085);
PROVIDE(ADC12MCTL6 = 0x0086);
PROVIDE(ADC12MCTL7 = 0x0087);
PROVIDE(ADC12MCTL8 = 0x0088);
PROVIDE(ADC12MCTL9 = 0x0089);
PROVIDE(ADC12MCTL10 = 0x008A);
PROVIDE(ADC12MCTL11 = 0x008B);
PROVIDE(ADC12MCTL12 = 0x008C);
PROVIDE(ADC12MCTL13 = 0x008D);
PROVIDE(ADC12MCTL14 = 0x008E);
PROVIDE(ADC12MCTL15 = 0x008F);
/************************************************************
* DAC12
************************************************************/
PROVIDE(DAC12_0CTL = 0x01C0);
PROVIDE(DAC12_1CTL = 0x01C2);
PROVIDE(DAC12_0DAT = 0x01C8);
PROVIDE(DAC12_1DAT = 0x01CA);
/************************************************************
* DMA
************************************************************/
PROVIDE(DMACTL0 = 0x0122);
PROVIDE(DMACTL1 = 0x0124);
PROVIDE(DMA0CTL = 0x01E0);
PROVIDE(DMA1CTL = 0x01E8);
PROVIDE(DMA2CTL = 0x01F0);
PROVIDE(DMA0SA = 0x01E2);
PROVIDE(DMA0DA = 0x01E4);
PROVIDE(DMA0SZ = 0x01E6);
PROVIDE(DMA1SA = 0x01EA);
PROVIDE(DMA1DA = 0x01EC);
PROVIDE(DMA1SZ = 0x01EE);
PROVIDE(DMA2SA = 0x01F2);
PROVIDE(DMA2DA = 0x01F4);
PROVIDE(DMA2SZ = 0x01F6);
/************************************************************
* Interrupt Vectors (offset from 0xFFE0)
************************************************************/
/************************************************************
* End of Modules
************************************************************/

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File diff suppressed because it is too large Load Diff

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cpu/msp430_common/vendor/msp430-gcc-support-files/include/msp430f2617.ld vendored Normal file
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@ -0,0 +1,397 @@
/* ============================================================================ */
/* Copyright (c) 2020, Texas Instruments Incorporated */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following conditions */
/* are met: */
/* */
/* * Redistributions of source code must retain the above copyright */
/* notice, this list of conditions and the following disclaimer. */
/* */
/* * Redistributions in binary form must reproduce the above copyright */
/* notice, this list of conditions and the following disclaimer in the */
/* documentation and/or other materials provided with the distribution. */
/* */
/* * Neither the name of Texas Instruments Incorporated nor the names of */
/* its contributors may be used to endorse or promote products derived */
/* from this software without specific prior written permission. */
/* */
/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */
/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */
/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */
/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */
/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */
/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */
/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */
/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */
/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */
/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ============================================================================ */
/* This file supports MSP430F2617 devices. */
/* Version: 1.210 */
/* Default linker script, for normal executables */
OUTPUT_ARCH(msp430)
ENTRY(_start)
MEMORY {
SFR : ORIGIN = 0x0000, LENGTH = 0x0010 /* END=0x0010, size 16 */
RAM : ORIGIN = 0x1100, LENGTH = 0x2000 /* END=0x30FF, size 8192 */
RAM_MIRROR : ORIGIN = 0x0200, LENGTH = 0x0800
INFOMEM : ORIGIN = 0x1000, LENGTH = 0x0100 /* END=0x10FF, size 256 as 4 64-byte segments */
INFOA : ORIGIN = 0x10C0, LENGTH = 0x0040 /* END=0x10FF, size 64 */
INFOB : ORIGIN = 0x1080, LENGTH = 0x0040 /* END=0x10BF, size 64 */
INFOC : ORIGIN = 0x1040, LENGTH = 0x0040 /* END=0x107F, size 64 */
INFOD : ORIGIN = 0x1000, LENGTH = 0x0040 /* END=0x103F, size 64 */
ROM (rx) : ORIGIN = 0x3100, LENGTH = 0xCEBE /* END=0xFFBD, size 52926 */
HIROM (rx) : ORIGIN = 0x00010000, LENGTH = 0x00009FFF
BSLSIGNATURE : ORIGIN = 0xFFBE, LENGTH = 0x0002
VECT1 : ORIGIN = 0xFFC0, LENGTH = 0x0002
VECT2 : ORIGIN = 0xFFC2, LENGTH = 0x0002
VECT3 : ORIGIN = 0xFFC4, LENGTH = 0x0002
VECT4 : ORIGIN = 0xFFC6, LENGTH = 0x0002
VECT5 : ORIGIN = 0xFFC8, LENGTH = 0x0002
VECT6 : ORIGIN = 0xFFCA, LENGTH = 0x0002
VECT7 : ORIGIN = 0xFFCC, LENGTH = 0x0002
VECT8 : ORIGIN = 0xFFCE, LENGTH = 0x0002
VECT9 : ORIGIN = 0xFFD0, LENGTH = 0x0002
VECT10 : ORIGIN = 0xFFD2, LENGTH = 0x0002
VECT11 : ORIGIN = 0xFFD4, LENGTH = 0x0002
VECT12 : ORIGIN = 0xFFD6, LENGTH = 0x0002
VECT13 : ORIGIN = 0xFFD8, LENGTH = 0x0002
VECT14 : ORIGIN = 0xFFDA, LENGTH = 0x0002
VECT15 : ORIGIN = 0xFFDC, LENGTH = 0x0002
VECT16 : ORIGIN = 0xFFDE, LENGTH = 0x0002
VECT17 : ORIGIN = 0xFFE0, LENGTH = 0x0002
VECT18 : ORIGIN = 0xFFE2, LENGTH = 0x0002
VECT19 : ORIGIN = 0xFFE4, LENGTH = 0x0002
VECT20 : ORIGIN = 0xFFE6, LENGTH = 0x0002
VECT21 : ORIGIN = 0xFFE8, LENGTH = 0x0002
VECT22 : ORIGIN = 0xFFEA, LENGTH = 0x0002
VECT23 : ORIGIN = 0xFFEC, LENGTH = 0x0002
VECT24 : ORIGIN = 0xFFEE, LENGTH = 0x0002
VECT25 : ORIGIN = 0xFFF0, LENGTH = 0x0002
VECT26 : ORIGIN = 0xFFF2, LENGTH = 0x0002
VECT27 : ORIGIN = 0xFFF4, LENGTH = 0x0002
VECT28 : ORIGIN = 0xFFF6, LENGTH = 0x0002
VECT29 : ORIGIN = 0xFFF8, LENGTH = 0x0002
VECT30 : ORIGIN = 0xFFFA, LENGTH = 0x0002
VECT31 : ORIGIN = 0xFFFC, LENGTH = 0x0002
RESETVEC : ORIGIN = 0xFFFE, LENGTH = 0x0002
}
SECTIONS
{
.bslsignature : {} > BSLSIGNATURE
__interrupt_vector_1 : { KEEP (*(__interrupt_vector_1 )) KEEP (*(__interrupt_vector_reserved0)) } > VECT1
__interrupt_vector_2 : { KEEP (*(__interrupt_vector_2 )) KEEP (*(__interrupt_vector_reserved1)) } > VECT2
__interrupt_vector_3 : { KEEP (*(__interrupt_vector_3 )) KEEP (*(__interrupt_vector_reserved2)) } > VECT3
__interrupt_vector_4 : { KEEP (*(__interrupt_vector_4 )) KEEP (*(__interrupt_vector_reserved3)) } > VECT4
__interrupt_vector_5 : { KEEP (*(__interrupt_vector_5 )) KEEP (*(__interrupt_vector_reserved4)) } > VECT5
__interrupt_vector_6 : { KEEP (*(__interrupt_vector_6 )) KEEP (*(__interrupt_vector_reserved5)) } > VECT6
__interrupt_vector_7 : { KEEP (*(__interrupt_vector_7 )) KEEP (*(__interrupt_vector_reserved6)) } > VECT7
__interrupt_vector_8 : { KEEP (*(__interrupt_vector_8 )) KEEP (*(__interrupt_vector_reserved7)) } > VECT8
__interrupt_vector_9 : { KEEP (*(__interrupt_vector_9 )) KEEP (*(__interrupt_vector_reserved8)) } > VECT9
__interrupt_vector_10 : { KEEP (*(__interrupt_vector_10)) KEEP (*(__interrupt_vector_reserved9)) } > VECT10
__interrupt_vector_11 : { KEEP (*(__interrupt_vector_11)) KEEP (*(__interrupt_vector_reserved10)) } > VECT11
__interrupt_vector_12 : { KEEP (*(__interrupt_vector_12)) KEEP (*(__interrupt_vector_reserved11)) } > VECT12
__interrupt_vector_13 : { KEEP (*(__interrupt_vector_13)) KEEP (*(__interrupt_vector_reserved12)) } > VECT13
__interrupt_vector_14 : { KEEP (*(__interrupt_vector_14)) KEEP (*(__interrupt_vector_reserved13)) } > VECT14
__interrupt_vector_15 : { KEEP (*(__interrupt_vector_15)) KEEP (*(__interrupt_vector_dac12)) } > VECT15
__interrupt_vector_16 : { KEEP (*(__interrupt_vector_16)) KEEP (*(__interrupt_vector_dma)) } > VECT16
__interrupt_vector_17 : { KEEP (*(__interrupt_vector_17)) KEEP (*(__interrupt_vector_usciab1tx)) } > VECT17
__interrupt_vector_18 : { KEEP (*(__interrupt_vector_18)) KEEP (*(__interrupt_vector_usciab1rx)) } > VECT18
__interrupt_vector_19 : { KEEP (*(__interrupt_vector_19)) KEEP (*(__interrupt_vector_port1)) } > VECT19
__interrupt_vector_20 : { KEEP (*(__interrupt_vector_20)) KEEP (*(__interrupt_vector_port2)) } > VECT20
__interrupt_vector_21 : { KEEP (*(__interrupt_vector_21)) KEEP (*(__interrupt_vector_reserved20)) } > VECT21
__interrupt_vector_22 : { KEEP (*(__interrupt_vector_22)) KEEP (*(__interrupt_vector_adc12)) } > VECT22
__interrupt_vector_23 : { KEEP (*(__interrupt_vector_23)) KEEP (*(__interrupt_vector_usciab0tx)) } > VECT23
__interrupt_vector_24 : { KEEP (*(__interrupt_vector_24)) KEEP (*(__interrupt_vector_usciab0rx)) } > VECT24
__interrupt_vector_25 : { KEEP (*(__interrupt_vector_25)) KEEP (*(__interrupt_vector_timera1)) } > VECT25
__interrupt_vector_26 : { KEEP (*(__interrupt_vector_26)) KEEP (*(__interrupt_vector_timera0)) } > VECT26
__interrupt_vector_27 : { KEEP (*(__interrupt_vector_27)) KEEP (*(__interrupt_vector_wdt)) } > VECT27
__interrupt_vector_28 : { KEEP (*(__interrupt_vector_28)) KEEP (*(__interrupt_vector_comparatora)) } > VECT28
__interrupt_vector_29 : { KEEP (*(__interrupt_vector_29)) KEEP (*(__interrupt_vector_timerb1)) } > VECT29
__interrupt_vector_30 : { KEEP (*(__interrupt_vector_30)) KEEP (*(__interrupt_vector_timerb0)) } > VECT30
__interrupt_vector_31 : { KEEP (*(__interrupt_vector_31)) KEEP (*(__interrupt_vector_nmi)) } > VECT31
__reset_vector :
{
KEEP (*(__interrupt_vector_32))
KEEP (*(__interrupt_vector_reset))
KEEP (*(.resetvec))
} > RESETVEC
.lower.rodata :
{
. = ALIGN(2);
*(.lower.rodata.* .lower.rodata)
} > ROM
.rodata :
{
. = ALIGN(2);
*(.plt)
. = ALIGN(2);
*(.rodata .rodata.* .gnu.linkonce.r.* .const .const:*)
*(.rodata1)
KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)
} > ROM
/* Note: This is a separate .rodata section for sections which are
read only but which older linkers treat as read-write.
This prevents older linkers from marking the entire .rodata
section as read-write. */
.rodata2 :
{
. = ALIGN(2);
PROVIDE (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE (__preinit_array_end = .);
. = ALIGN(2);
PROVIDE (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
PROVIDE (__init_array_end = .);
. = ALIGN(2);
PROVIDE (__fini_array_start = .);
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
PROVIDE (__fini_array_end = .);
. = ALIGN(2);
*(.eh_frame_hdr)
KEEP (*(.eh_frame))
/* gcc uses crtbegin.o to find the start of the constructors, so
we make sure it is first. Because this is a wildcard, it
doesn't matter if the user does not actually link against
crtbegin.o; the linker won't look for a file to match a
wildcard. The wildcard also means that it doesn't matter which
directory crtbegin.o is in. */
KEEP (*crtbegin*.o(.ctors))
/* We don't want to include the .ctor section from from the
crtend.o file until after the sorted ctors. The .ctor section
from the crtend file contains the end of ctors marker and it
must be last */
KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
KEEP (*crtbegin*.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
} > ROM
.upper.rodata :
{
*(.upper.rodata.* .upper.rodata)
} > HIROM
.data :
{
. = ALIGN(2);
PROVIDE (__datastart = .);
*(.lower.data.* .lower.data)
. = ALIGN(2);
*(.either.data.* .either.data)
. = ALIGN(2);
KEEP (*(.jcr))
*(.data.rel.ro.local) *(.data.rel.ro*)
*(.dynamic)
. = ALIGN(2);
*(.data .data.* .gnu.linkonce.d.*)
KEEP (*(.gnu.linkonce.d.*personality*))
SORT(CONSTRUCTORS)
*(.data1)
*(.got.plt) *(.got)
/* We want the small data sections together, so single-instruction offsets
can access them all, and initialized data all before uninitialized, so
we can shorten the on-disk segment size. */
. = ALIGN(2);
*(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1)
. = ALIGN(2);
_edata = .;
PROVIDE (edata = .);
PROVIDE (__dataend = .);
} > RAM AT> ROM
/* Note that crt0 assumes this is a multiple of two; all the
start/stop symbols are also assumed word-aligned. */
PROVIDE(__romdatastart = LOADADDR(.data));
PROVIDE (__romdatacopysize = SIZEOF(.data));
.bss :
{
. = ALIGN(2);
PROVIDE (__bssstart = .);
*(.lower.bss.* .lower.bss)
. = ALIGN(2);
*(.either.bss.* .either.bss)
*(.dynbss)
*(.sbss .sbss.*)
*(.bss .bss.* .gnu.linkonce.b.*)
. = ALIGN(2);
*(COMMON)
PROVIDE (__bssend = .);
} > RAM
PROVIDE (__bsssize = SIZEOF(.bss));
/* This section contains data that is not initialised during load
or application reset. */
.noinit (NOLOAD) :
{
. = ALIGN(2);
PROVIDE (__noinit_start = .);
*(.noinit)
. = ALIGN(2);
PROVIDE (__noinit_end = .);
} > RAM
/* We create this section so that "end" will always be in the
RAM region (matching .stack below), even if the .bss
section is empty. */
.heap (NOLOAD) :
{
. = ALIGN(2);
__heap_start__ = .;
_end = __heap_start__;
PROVIDE (end = .);
KEEP (*(.heap))
_end = .;
PROVIDE (end = .);
/* This word is here so that the section is not empty, and thus
not discarded by the linker. The actual value does not matter
and is ignored. */
LONG(0);
__heap_end__ = .;
__HeapLimit = __heap_end__;
} > RAM
/* WARNING: Do not place anything in RAM here.
The heap section must be the last section in RAM and the stack
section must be placed at the very end of the RAM region. */
.stack (ORIGIN (RAM) + LENGTH(RAM)) :
{
PROVIDE (__stack = .);
*(.stack)
}
/* This is just for crt0.S and interrupt handlers. */
.lowtext :
{
PROVIDE (_start = .);
. = ALIGN(2);
KEEP (*(SORT(.crt_*)))
KEEP (*(.lowtext))
} > ROM
.lower.text :
{
. = ALIGN(2);
*(.lower.text.* .lower.text)
} > ROM
.text :
{
. = ALIGN(2);
*(.text .stub .text.* .gnu.linkonce.t.* .text:*)
KEEP (*(.text.*personality*))
/* .gnu.warning sections are handled specially by elf32.em. */
*(.gnu.warning)
*(.interp .hash .dynsym .dynstr .gnu.version*)
PROVIDE (__etext = .);
PROVIDE (_etext = .);
PROVIDE (etext = .);
. = ALIGN(2);
KEEP (*(.init))
KEEP (*(.fini))
KEEP (*(.tm_clone_table))
} > ROM
.upper.text :
{
. = ALIGN(2);
*(.upper.text.* .upper.text)
} > HIROM
.infoA : {} > INFOA /* MSP430 INFO FLASH MEMORY SEGMENTS */
.infoB : {} > INFOB
.infoC : {} > INFOC
.infoD : {} > INFOD
/* Make sure that upper data sections are not used. */
.upper :
{
*(.upper.bss.* .upper.bss)
*(.upper.data.* .upper.data)
ASSERT (SIZEOF(.upper) == 0, "This MCU does not support placing read/write data into high memory");
} > HIROM
/* The rest are all not normally part of the runtime image. */
.MSP430.attributes 0 :
{
KEEP (*(.MSP430.attributes))
KEEP (*(.gnu.attributes))
KEEP (*(__TI_build_attributes))
}
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1. */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions. */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2. */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2. */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end ) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions. */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
/* DWARF 3 */
.debug_pubtypes 0 : { *(.debug_pubtypes) }
.debug_ranges 0 : { *(.debug_ranges) }
/* DWARF Extension. */
.debug_macro 0 : { *(.debug_macro) }
/DISCARD/ : { *(.note.GNU-stack) }
}
/****************************************************************************/
/* Include peripherals memory map */
/****************************************************************************/
INCLUDE msp430f2617_symbols.ld

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cpu/msp430_common/vendor/msp430-gcc-support-files/include/msp430f2617_symbols.ld vendored Normal file
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@ -0,0 +1,328 @@
/* ============================================================================ */
/* Copyright (c) 2020, Texas Instruments Incorporated */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following conditions */
/* are met: */
/* */
/* * Redistributions of source code must retain the above copyright */
/* notice, this list of conditions and the following disclaimer. */
/* */
/* * Redistributions in binary form must reproduce the above copyright */
/* notice, this list of conditions and the following disclaimer in the */
/* documentation and/or other materials provided with the distribution. */
/* */
/* * Neither the name of Texas Instruments Incorporated nor the names of */
/* its contributors may be used to endorse or promote products derived */
/* from this software without specific prior written permission. */
/* */
/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */
/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */
/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */
/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */
/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */
/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */
/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */
/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */
/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */
/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ============================================================================ */
/* This file supports MSP430F2617 devices. */
/* Version: 1.210 */
/************************************************************
* STANDARD BITS
************************************************************/
/************************************************************
* STATUS REGISTER BITS
************************************************************/
/************************************************************
* PERIPHERAL FILE MAP
************************************************************/
/************************************************************
* SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS
************************************************************/
PROVIDE(IE1 = 0x0000);
PROVIDE(IFG1 = 0x0002);
PROVIDE(IE2 = 0x0001);
PROVIDE(IFG2 = 0x0003);
PROVIDE(UC1IE = 0x0006);
PROVIDE(UC1IFG = 0x0007);
/************************************************************
* ADC12
************************************************************/
PROVIDE(ADC12CTL0 = 0x01A0);
PROVIDE(ADC12CTL1 = 0x01A2);
PROVIDE(ADC12IFG = 0x01A4);
PROVIDE(ADC12IE = 0x01A6);
PROVIDE(ADC12IV = 0x01A8);
PROVIDE(ADC12MEM0 = 0x0140);
PROVIDE(ADC12MEM1 = 0x0142);
PROVIDE(ADC12MEM2 = 0x0144);
PROVIDE(ADC12MEM3 = 0x0146);
PROVIDE(ADC12MEM4 = 0x0148);
PROVIDE(ADC12MEM5 = 0x014A);
PROVIDE(ADC12MEM6 = 0x014C);
PROVIDE(ADC12MEM7 = 0x014E);
PROVIDE(ADC12MEM8 = 0x0150);
PROVIDE(ADC12MEM9 = 0x0152);
PROVIDE(ADC12MEM10 = 0x0154);
PROVIDE(ADC12MEM11 = 0x0156);
PROVIDE(ADC12MEM12 = 0x0158);
PROVIDE(ADC12MEM13 = 0x015A);
PROVIDE(ADC12MEM14 = 0x015C);
PROVIDE(ADC12MEM15 = 0x015E);
PROVIDE(ADC12MCTL0 = 0x0080);
PROVIDE(ADC12MCTL1 = 0x0081);
PROVIDE(ADC12MCTL2 = 0x0082);
PROVIDE(ADC12MCTL3 = 0x0083);
PROVIDE(ADC12MCTL4 = 0x0084);
PROVIDE(ADC12MCTL5 = 0x0085);
PROVIDE(ADC12MCTL6 = 0x0086);
PROVIDE(ADC12MCTL7 = 0x0087);
PROVIDE(ADC12MCTL8 = 0x0088);
PROVIDE(ADC12MCTL9 = 0x0089);
PROVIDE(ADC12MCTL10 = 0x008A);
PROVIDE(ADC12MCTL11 = 0x008B);
PROVIDE(ADC12MCTL12 = 0x008C);
PROVIDE(ADC12MCTL13 = 0x008D);
PROVIDE(ADC12MCTL14 = 0x008E);
PROVIDE(ADC12MCTL15 = 0x008F);
/************************************************************
* Basic Clock Module
************************************************************/
PROVIDE(DCOCTL = 0x0056);
PROVIDE(BCSCTL1 = 0x0057);
PROVIDE(BCSCTL2 = 0x0058);
PROVIDE(BCSCTL3 = 0x0053);
/************************************************************
* Comparator A
************************************************************/
PROVIDE(CACTL1 = 0x0059);
PROVIDE(CACTL2 = 0x005A);
PROVIDE(CAPD = 0x005B);
/************************************************************
* DAC12
************************************************************/
PROVIDE(DAC12_0CTL = 0x01C0);
PROVIDE(DAC12_1CTL = 0x01C2);
PROVIDE(DAC12_0DAT = 0x01C8);
PROVIDE(DAC12_1DAT = 0x01CA);
/************************************************************
* DMA_X
************************************************************/
PROVIDE(DMACTL0 = 0x0122);
PROVIDE(DMACTL1 = 0x0124);
PROVIDE(DMAIV = 0x0126);
PROVIDE(DMA0CTL = 0x01D0);
PROVIDE(DMA1CTL = 0x01DC);
PROVIDE(DMA2CTL = 0x01E8);
PROVIDE(DMA0SA = 0x01D2);
PROVIDE(DMA0SAL = 0x01D2);
PROVIDE(DMA0DA = 0x01D6);
PROVIDE(DMA0DAL = 0x01D6);
PROVIDE(DMA0SZ = 0x01DA);
PROVIDE(DMA1SA = 0x01DE);
PROVIDE(DMA1SAL = 0x01DE);
PROVIDE(DMA1DA = 0x01E2);
PROVIDE(DMA1DAL = 0x01E2);
PROVIDE(DMA1SZ = 0x01E6);
PROVIDE(DMA2SA = 0x01EA);
PROVIDE(DMA2SAL = 0x01EA);
PROVIDE(DMA2DA = 0x01EE);
PROVIDE(DMA2DAL = 0x01EE);
PROVIDE(DMA2SZ = 0x01F2);
/*************************************************************
* Flash Memory
*************************************************************/
PROVIDE(FCTL1 = 0x0128);
PROVIDE(FCTL2 = 0x012A);
PROVIDE(FCTL3 = 0x012C);
PROVIDE(FCTL4 = 0x01BE);
/************************************************************
* HARDWARE MULTIPLIER
************************************************************/
PROVIDE(MPY = 0x0130);
PROVIDE(MPYS = 0x0132);
PROVIDE(MAC = 0x0134);
PROVIDE(MACS = 0x0136);
PROVIDE(OP2 = 0x0138);
PROVIDE(RESLO = 0x013A);
PROVIDE(RESHI = 0x013C);
PROVIDE(SUMEXT = 0x013E);
/************************************************************
* DIGITAL I/O Port1/2 Pull up / Pull down Resistors
************************************************************/
PROVIDE(P1IN = 0x0020);
PROVIDE(P1OUT = 0x0021);
PROVIDE(P1DIR = 0x0022);
PROVIDE(P1IFG = 0x0023);
PROVIDE(P1IES = 0x0024);
PROVIDE(P1IE = 0x0025);
PROVIDE(P1SEL = 0x0026);
PROVIDE(P1REN = 0x0027);
PROVIDE(P2IN = 0x0028);
PROVIDE(P2OUT = 0x0029);
PROVIDE(P2DIR = 0x002A);
PROVIDE(P2IFG = 0x002B);
PROVIDE(P2IES = 0x002C);
PROVIDE(P2IE = 0x002D);
PROVIDE(P2SEL = 0x002E);
PROVIDE(P2REN = 0x002F);
/************************************************************
* DIGITAL I/O Port3/4 Pull up / Pull down Resistors
************************************************************/
PROVIDE(P3IN = 0x0018);
PROVIDE(P3OUT = 0x0019);
PROVIDE(P3DIR = 0x001A);
PROVIDE(P3SEL = 0x001B);
PROVIDE(P3REN = 0x0010);
PROVIDE(P4IN = 0x001C);
PROVIDE(P4OUT = 0x001D);
PROVIDE(P4DIR = 0x001E);
PROVIDE(P4SEL = 0x001F);
PROVIDE(P4REN = 0x0011);
/************************************************************
* DIGITAL I/O Port5/6 Pull up / Pull down Resistors
************************************************************/
PROVIDE(P5IN = 0x0030);
PROVIDE(P5OUT = 0x0031);
PROVIDE(P5DIR = 0x0032);
PROVIDE(P5SEL = 0x0033);
PROVIDE(P5REN = 0x0012);
PROVIDE(P6IN = 0x0034);
PROVIDE(P6OUT = 0x0035);
PROVIDE(P6DIR = 0x0036);
PROVIDE(P6SEL = 0x0037);
PROVIDE(P6REN = 0x0013);
/************************************************************
* DIGITAL I/O Port7/8 Pull up / Pull down Resistors
************************************************************/
PROVIDE(P7IN = 0x0038);
PROVIDE(P7OUT = 0x003A);
PROVIDE(P7DIR = 0x003C);
PROVIDE(P7SEL = 0x003E);
PROVIDE(P7REN = 0x0014);
PROVIDE(P8IN = 0x0039);
PROVIDE(P8OUT = 0x003B);
PROVIDE(P8DIR = 0x003D);
PROVIDE(P8SEL = 0x003F);
PROVIDE(P8REN = 0x0015);
PROVIDE(PAIN = 0x0038);
PROVIDE(PAOUT = 0x003A);
PROVIDE(PADIR = 0x003C);
PROVIDE(PASEL = 0x003E);
PROVIDE(PAREN = 0x0014);
/************************************************************
* Brown-Out, Supply Voltage Supervision (SVS)
************************************************************/
PROVIDE(SVSCTL = 0x0055);
/************************************************************
* Timer A3
************************************************************/
PROVIDE(TAIV = 0x012E);
PROVIDE(TACTL = 0x0160);
PROVIDE(TACCTL0 = 0x0162);
PROVIDE(TACCTL1 = 0x0164);
PROVIDE(TACCTL2 = 0x0166);
PROVIDE(TAR = 0x0170);
PROVIDE(TACCR0 = 0x0172);
PROVIDE(TACCR1 = 0x0174);
PROVIDE(TACCR2 = 0x0176);
/************************************************************
* Timer B7
************************************************************/
PROVIDE(TBIV = 0x011E);
PROVIDE(TBCTL = 0x0180);
PROVIDE(TBCCTL0 = 0x0182);
PROVIDE(TBCCTL1 = 0x0184);
PROVIDE(TBCCTL2 = 0x0186);
PROVIDE(TBCCTL3 = 0x0188);
PROVIDE(TBCCTL4 = 0x018A);
PROVIDE(TBCCTL5 = 0x018C);
PROVIDE(TBCCTL6 = 0x018E);
PROVIDE(TBR = 0x0190);
PROVIDE(TBCCR0 = 0x0192);
PROVIDE(TBCCR1 = 0x0194);
PROVIDE(TBCCR2 = 0x0196);
PROVIDE(TBCCR3 = 0x0198);
PROVIDE(TBCCR4 = 0x019A);
PROVIDE(TBCCR5 = 0x019C);
PROVIDE(TBCCR6 = 0x019E);
/************************************************************
* USCI
************************************************************/
PROVIDE(UCA0CTL0 = 0x0060);
PROVIDE(UCA0CTL1 = 0x0061);
PROVIDE(UCA0BR0 = 0x0062);
PROVIDE(UCA0BR1 = 0x0063);
PROVIDE(UCA0MCTL = 0x0064);
PROVIDE(UCA0STAT = 0x0065);
PROVIDE(UCA0RXBUF = 0x0066);
PROVIDE(UCA0TXBUF = 0x0067);
PROVIDE(UCA0ABCTL = 0x005D);
PROVIDE(UCA0IRTCTL = 0x005E);
PROVIDE(UCA0IRRCTL = 0x005F);
PROVIDE(UCB0CTL0 = 0x0068);
PROVIDE(UCB0CTL1 = 0x0069);
PROVIDE(UCB0BR0 = 0x006A);
PROVIDE(UCB0BR1 = 0x006B);
PROVIDE(UCB0I2CIE = 0x006C);
PROVIDE(UCB0STAT = 0x006D);
PROVIDE(UCB0RXBUF = 0x006E);
PROVIDE(UCB0TXBUF = 0x006F);
PROVIDE(UCB0I2COA = 0x0118);
PROVIDE(UCB0I2CSA = 0x011A);
PROVIDE(UCA1CTL0 = 0x00D0);
PROVIDE(UCA1CTL1 = 0x00D1);
PROVIDE(UCA1BR0 = 0x00D2);
PROVIDE(UCA1BR1 = 0x00D3);
PROVIDE(UCA1MCTL = 0x00D4);
PROVIDE(UCA1STAT = 0x00D5);
PROVIDE(UCA1RXBUF = 0x00D6);
PROVIDE(UCA1TXBUF = 0x00D7);
PROVIDE(UCA1ABCTL = 0x00CD);
PROVIDE(UCA1IRTCTL = 0x00CE);
PROVIDE(UCA1IRRCTL = 0x00CF);
PROVIDE(UCB1CTL0 = 0x00D8);
PROVIDE(UCB1CTL1 = 0x00D9);
PROVIDE(UCB1BR0 = 0x00DA);
PROVIDE(UCB1BR1 = 0x00DB);
PROVIDE(UCB1I2CIE = 0x00DC);
PROVIDE(UCB1STAT = 0x00DD);
PROVIDE(UCB1RXBUF = 0x00DE);
PROVIDE(UCB1TXBUF = 0x00DF);
PROVIDE(UCB1I2COA = 0x017C);
PROVIDE(UCB1I2CSA = 0x017E);
/************************************************************
* WATCHDOG TIMER
************************************************************/
PROVIDE(WDTCTL = 0x0120);
/************************************************************
* Calibration Data in Info Mem
************************************************************/
PROVIDE(TLV_CHECKSUM = 0x10C0);
PROVIDE(TLV_DCO_30_TAG = 0x10F6);
PROVIDE(TLV_DCO_30_LEN = 0x10F7);
PROVIDE(TLV_ADC12_1_TAG = 0x10DA);
PROVIDE(TLV_ADC12_1_LEN = 0x10DB);
/************************************************************
* Calibration Data in Info Mem
************************************************************/
PROVIDE(CALDCO_16MHZ = 0x10F8);
PROVIDE(CALBC1_16MHZ = 0x10F9);
PROVIDE(CALDCO_12MHZ = 0x10FA);
PROVIDE(CALBC1_12MHZ = 0x10FB);
PROVIDE(CALDCO_8MHZ = 0x10FC);
PROVIDE(CALBC1_8MHZ = 0x10FD);
PROVIDE(CALDCO_1MHZ = 0x10FE);
PROVIDE(CALBC1_1MHZ = 0x10FF);
/************************************************************
* Interrupt Vectors (offset from 0xFFC0)
************************************************************/
/************************************************************
* End of Modules
************************************************************/

19
cpu/msp430_common/vendor/update.sh vendored Normal file
View File

@ -0,0 +1,19 @@
#!/bin/sh
# This script downloads downloads and extracts the msp430 support files,
# then removes currently unused headers and linker scripts.
set -e
URL="https://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/9_2_0_0/export/msp430-gcc-support-files-1.210.zip"
rm -Rf msp430-gcc-support-files
_CPUS="$(git -C ../../.. grep -o '^CPU_MODEL.=.*430.*$' | cut -d' ' -f 3 | sort -u)"
wget $URL
unzip $(basename $URL)
(
cd msp430-gcc-support-files/include
rm $(ls | grep -v -E '(msp430\.h|in430\.h|legacy\.h|iomacros\.h|devices.csv)' | \
grep -v -F "${_CPUS}" )
)

3
cpu/msp430fxyz/Makefile.dep
View File

@ -1,3 +1,2 @@
USEMODULE += periph stdio_uart
USEMODULE += periph
include $(RIOTCPU)/msp430_common/Makefile.dep

57
cpu/msp430fxyz/msp430_stdio.c
View File

@ -1,57 +0,0 @@
/*
* Copyright (C) 2015 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_msp430fxyz
* @{
*
* @file
* @brief Implementation of getchar and putchar for MSP430 CPUs
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
* @}
*/
#include <sys/types.h>
#include <unistd.h>
#include "stdio_uart.h"
/**
* @brief Get one character from STDIO - used by the libc
*/
int getchar(void)
{
char c;
stdio_read(&c, 1);
return c;
}
/**
* @brief Write one character to the STDIO UART interface - used by e.g.
* printf and puts
*/
int putchar(int c)
{
char _c = c;
return stdio_write(&_c, 1);
}
/**
* @brief Write nbyte characters to the STDIO UART interface
*/
ssize_t write(int fildes, const void *buf, size_t nbyte)
{
if (fildes == STDOUT_FILENO) {
return stdio_write(buf, nbyte);
}
else {
return -1;
}
}

3
dist/tools/ci/print_toolchain_versions.sh vendored
View File

@ -125,7 +125,7 @@ printf "%25s: %s\n" "native gcc" "$(get_cmd_version gcc)"
for p in \
arm-none-eabi \
avr mips-mti-elf \
msp430 \
msp430-elf \
riscv-none-embed \
xtensa-esp32-elf \
xtensa-esp8266-elf \
@ -140,6 +140,7 @@ printf "%s\n" "-----------------------"
for p in \
arm-none-eabi \
mips-mti-elf \
msp430-elf \
riscv-none-embed \
xtensa-esp32-elf \
xtensa-esp8266-elf \

1
examples/asymcute_mqttsn/Makefile.ci
View File

@ -7,7 +7,6 @@ BOARD_INSUFFICIENT_MEMORY := \
arduino-uno \
atmega1284p \
atmega328p \
chronos \
derfmega128 \
hifive1 \
hifive1b \

1
examples/cord_ep/Makefile.ci
View File

@ -6,7 +6,6 @@ BOARD_INSUFFICIENT_MEMORY := \
arduino-uno \
atmega1284p \
atmega328p \
chronos \
derfmega128 \
hifive1 \
hifive1b \

1
examples/cord_epsim/Makefile.ci
View File

@ -5,7 +5,6 @@ BOARD_INSUFFICIENT_MEMORY := \
arduino-nano \
arduino-uno \
atmega328p \
chronos \
hifive1 \
hifive1b \
i-nucleo-lrwan1 \

1
examples/emcute_mqttsn/Makefile.ci
View File

@ -6,7 +6,6 @@ BOARD_INSUFFICIENT_MEMORY := \
arduino-uno \
atmega1284p \
atmega328p \
chronos \
derfmega128 \
hifive1 \
hifive1b \

1
examples/gcoap/Makefile.ci
View File

@ -6,7 +6,6 @@ BOARD_INSUFFICIENT_MEMORY := \
arduino-uno \
atmega1284p \
atmega328p \
chronos \
derfmega128 \
i-nucleo-lrwan1 \
mega-xplained \

1
examples/gnrc_networking/Makefile.ci
View File

@ -9,7 +9,6 @@ BOARD_INSUFFICIENT_MEMORY := \
blackpill \
bluepill \
calliope-mini \
chronos \
derfmega128 \
hifive1 \
hifive1b \

1
examples/nanocoap_server/Makefile.ci
View File

@ -5,7 +5,6 @@ BOARD_INSUFFICIENT_MEMORY := \
arduino-nano \
arduino-uno \
atmega328p \
chronos \
derfmega128 \
i-nucleo-lrwan1 \
microduino-corerf \

1
examples/ndn-ping/Makefile.ci
View File

@ -6,7 +6,6 @@ BOARD_INSUFFICIENT_MEMORY := \
arduino-uno \
atmega1284p \
atmega328p \
chronos \
derfmega128 \
i-nucleo-lrwan1 \
mega-xplained \

1
examples/posix_sockets/Makefile.ci
View File

@ -7,7 +7,6 @@ BOARD_INSUFFICIENT_MEMORY := \
arduino-uno \
atmega1284p \
atmega328p \
chronos \
derfmega128 \
i-nucleo-lrwan1 \
im880b \

1
examples/suit_update/Makefile.ci
View File

@ -5,7 +5,6 @@ BOARD_INSUFFICIENT_MEMORY := \
arduino-uno \
atmega328p \
b-l072z-lrwan1 \
chronos \
lsn50 \
msb-430 \
msb-430h \

20
makefiles/arch/msp430.inc.mk
View File

@ -1,19 +1,19 @@
# Target architecture for the build. Use msp430 if you are unsure.
TARGET_ARCH ?= msp430
# Target architecture for the build. Use msp430-elf if you are unsure.
TARGET_ARCH ?= msp430-elf
MSP430_SUPPORT_FILES ?= $(RIOTCPU)/msp430_common/vendor/msp430-gcc-support-files
# define build specific options
CFLAGS_CPU = -mmcu=$(CPU_MODEL)
# default std set to gnu99 of not overwritten by user
ifeq (, $(filter -std=%, $(CFLAGS)))
CFLAGS += -std=gnu99
endif
CFLAGS_CPU = -mmcu=$(CPU_MODEL) -isystem $(MSP430_SUPPORT_FILES)/include
CFLAGS_LINK = -ffunction-sections -fdata-sections
CFLAGS_DBG ?= -gdwarf-2
CFLAGS_DBG ?= -g -gdwarf-2
CFLAGS_OPT ?= -Os
CFLAGS += $(CFLAGS_CPU) $(CFLAGS_LINK) $(CFLAGS_DBG) $(CFLAGS_OPT)
ASFLAGS += $(CFLAGS_CPU) --defsym $(CPU_MODEL)=1 $(CFLAGS_DBG)
# export linker flags
LINKFLAGS += $(CFLAGS_CPU) $(CFLAGS_DBG) $(CFLAGS_OPT) -Wl,--gc-sections -static -lgcc
LINKFLAGS += $(CFLAGS_CPU) $(CFLAGS_DBG) $(CFLAGS_OPT)
LINKFLAGS += -Wl,--gc-sections -Wl,-L$(MSP430_SUPPORT_FILES)/include
OPTIONAL_CFLAGS_BLACKLIST += -fdiagnostics-color
OPTIONAL_CFLAGS_BLACKLIST += -Wformat-overflow

3
pkg/tweetnacl/Makefile.dep
View File

@ -1 +1,4 @@
USEMODULE+=random
# the test takes ages and then reboots on msp430.
FEATURES_BLACKLIST += arch_msp430

2
sys/net/gnrc/transport_layer/tcp/gnrc_tcp_pkt.c
View File

@ -455,7 +455,7 @@ int _pkt_acknowledge(gnrc_tcp_tcb_t *tcb, const uint32_t ack)
/* If this is a subsequent sample */
else {
tcb->rtt_var = (tcb->rtt_var / CONFIG_GNRC_TCP_RTO_B_DIV) * (CONFIG_GNRC_TCP_RTO_B_DIV-1);
tcb->rtt_var += abs(tcb->srtt - rtt) / CONFIG_GNRC_TCP_RTO_B_DIV;
tcb->rtt_var += labs(tcb->srtt - rtt) / CONFIG_GNRC_TCP_RTO_B_DIV;
tcb->srtt = (tcb->srtt / CONFIG_GNRC_TCP_RTO_A_DIV) * (CONFIG_GNRC_TCP_RTO_A_DIV-1);
tcb->srtt += rtt / CONFIG_GNRC_TCP_RTO_A_DIV;
}

18
sys/newlib_syscalls_default/syscalls.c
View File

@ -60,11 +60,25 @@
#define NUM_HEAPS 1
#endif
#ifdef MODULE_MSP430_COMMON
/* the msp430 linker scripts define the end of all memory as __stack, which in
* turn is used as the initial stack. RIOT also uses __stack as SP on isr
* entry. This logic makes __stack - ISR_STACKSIZE the heap end.
*/
extern char __stack;
extern char __heap_start__;
#define _sheap __heap_start__
#define __eheap (char *)((uintptr_t)&__stack - ISR_STACKSIZE)
#else /* MODULE_MSP430_COMMON */
/**
* @brief manage the heap
*/
extern char _sheap; /* start of the heap */
extern char _eheap; /* end of the heap */
#define __eheap &_eheap
#endif
/**
* @brief Additional heap sections that may be defined in the linkerscript.
@ -108,7 +122,7 @@ static char *heap_top[NUM_HEAPS] = {
static const struct heap heaps[NUM_HEAPS] = {
{
.start = &_sheap,
.end = &_eheap
.end = __eheap
},
#if NUM_HEAPS > 1
{
@ -157,7 +171,7 @@ __attribute__((used)) void _fini(void)
*
* @param n the exit code, 0 for all OK, >0 for not OK
*/
void _exit(int n)
__attribute__((used)) void _exit(int n)
{
LOG_INFO("#! exit %i: powering off\n", n);
pm_off();

4
sys/posix/pthread/include/pthread_cond.h
View File

@ -21,10 +21,6 @@
#include "mutex.h"
#include "priority_queue.h"
#if defined(CPU_CC430) || defined(CPU_MSP430FXYZ)
# include "msp430_types.h"
#endif
#if defined(__WITH_AVRLIBC__)
/* avr-libc 'time.h' does not include 'sys/types.h' but we need 'clockid_t' */
# include <sys/types.h>

1
tests/bench_xtimer/Makefile
View File

@ -22,7 +22,6 @@ LOW_MEMORY_BOARDS += \
cc1352-launchpad \
cc2650-launchpad \
cc2650stk \
chronos \
derfmega128 \
feather-m0 \
hifive1 \

3
tests/bloom_bytes/Makefile.ci
View File

@ -4,9 +4,6 @@ BOARD_INSUFFICIENT_MEMORY := \
arduino-nano \
arduino-uno \
atmega328p \
chronos \
msb-430 \
msb-430h \
stm32f030f4-demo \
telosb \
z1 \

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