From 8fd8c8273f004e511eec1ba5c3ccc4e1458c0b1c Mon Sep 17 00:00:00 2001 From: Marian Buschsieweke Date: Sun, 8 Mar 2020 12:46:07 +0100 Subject: [PATCH] boards/{nucleo-f103rb,b*pill}: Expose JTAG pins as GPIOs The Nucleo-F103RB comes with an internal SWD programmer/debugger. Thus, the JTAG pins are not going to be used for debugging / programming anyway. The pins are exposed on the headers, so allowing them to be used as GPIOs make a lot of sense. The Bluepill / Blackpill boards only expose the SWD pins on the debug header, but the JTAG pins (not also used by SWD) are exposed on the GPIO pin headers. Hence, exposing them as regular GPIOs seems to be a reasonable choice. --- boards/common/blxxxpill/include/board_common.h | 8 ++++++++ boards/nucleo-f103rb/Makefile.include | 7 +++++++ 2 files changed, 15 insertions(+) diff --git a/boards/common/blxxxpill/include/board_common.h b/boards/common/blxxxpill/include/board_common.h index a405eadd8c..5305da7d14 100644 --- a/boards/common/blxxxpill/include/board_common.h +++ b/boards/common/blxxxpill/include/board_common.h @@ -67,6 +67,14 @@ void board_init(void); #define XTIMER_BACKOFF (19) /** @} */ +/* The boards debug header only exports SWD, so JTAG-only pins PA15, PB3(*), + * and PB4 can be remapped as regular GPIOs instead. (Note: PB3 is also used as + * SWO. The user needs to take care to not enable SWO with the debugger while + * at the same time PB3 is used as GPIO. But RIOT does not use SWO in any case, + * so if a user adds this feature in her/his own code, she/he should be well + * aware of this.) + */ +#define STM32F1_DISABLE_JTAG /**< Disable JTAG to allow pins being used as GPIOs */ #ifdef __cplusplus } #endif diff --git a/boards/nucleo-f103rb/Makefile.include b/boards/nucleo-f103rb/Makefile.include index 8db8eaed90..f0ba8bb233 100644 --- a/boards/nucleo-f103rb/Makefile.include +++ b/boards/nucleo-f103rb/Makefile.include @@ -1,2 +1,9 @@ # load the common Makefile.include for Nucleo boards include $(RIOTBOARD)/common/nucleo64/Makefile.include + +# On-board debugger uses SWD, so JTAG-only pins PA15, PB3(*), and PB4 can be +# remapped as regular GPIOs instead. (Note: PB3 is also used as SWO. The user +# needs to take care to not enable SWO with the debugger while at the same time +# PB3 is used as GPIO. But RIOT does not use SWO in any case, so if a user adds +# this feature in her/his own code, she/he should be well aware of this.) +CFLAGS += -DSTM32F1_DISABLE_JTAG