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Merge pull request #20747 from dylad/pr/cpu/sam0/avoid_bitfield_usage

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cpu/sam0_common: avoid bitfield usage
This commit is contained in:
Dylan Laduranty 2024-06-25 20:47:20 +00:00 committed by GitHub
commit 8f645a95a4
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GPG Key ID: B5690EEEBB952194
19 changed files with 294 additions and 200 deletions
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11
cpu/sam0_common/include/periph_cpu_common.h
View File

@ -681,8 +681,13 @@ typedef enum {
static inline void sam0_set_voltage_regulator(sam0_supc_t src)
{
#ifdef REG_SUPC_VREG
SUPC->VREG.bit.SEL = src;
while (!SUPC->STATUS.bit.VREGRDY) {}
if (src == SAM0_VREG_BUCK) {
SUPC->VREG.reg |= (1 << SUPC_VREG_SEL_Pos);
}
else {
SUPC->VREG.reg &= ~(1 << SUPC_VREG_SEL_Pos);
}
while (!(SUPC->STATUS.reg & SUPC_STATUS_VREGRDY)) {}
#else
(void) src;
assert(0);
@ -867,7 +872,7 @@ static inline void sercom_set_gen(void *sercom, uint8_t gclk)
static inline bool cpu_woke_from_backup(void)
{
#ifdef RSTC_RCAUSE_BACKUP
return RSTC->RCAUSE.bit.BACKUP;
return RSTC->RCAUSE.reg & RSTC_RCAUSE_BACKUP;
#else
return false;
#endif

13
cpu/sam0_common/periph/adc.c
View File

@ -190,10 +190,12 @@ static int _adc_configure(Adc *dev, adc_res_t res)
/* Set ADC resolution */
#ifdef ADC_CTRLC_RESSEL
/* Reset resolution bits in CTRLC */
dev->CTRLC.bit.RESSEL = res & 0x3;
uint32_t ctrlc = dev->CTRLC.reg;
dev->CTRLC.reg = ((ctrlc & ~ADC_CTRLC_RESSEL_Msk) | ADC_CTRLC_RESSEL(res));
#else
/* Reset resolution bits in CTRLB */
dev->CTRLB.bit.RESSEL = res & 0x3;
uint32_t ctrlb = dev->CTRLB.reg;
dev->CTRLB.reg = ((ctrlb & ~ADC_CTRLB_RESSEL_Msk) | ADC_CTRLB_RESSEL(res));
#endif
/* Set Voltage Reference */
@ -317,7 +319,12 @@ static int32_t _sample(adc_t line)
| adc_channels[line].inputctrl
| (diffmode ? 0 : ADC_NEG_INPUT);
#ifdef ADC_CTRLB_DIFFMODE
dev->CTRLB.bit.DIFFMODE = diffmode;
if (diffmode) {
dev->CTRLB.reg |= ADC_CTRLB_DIFFMODE;
}
else {
dev->CTRLB.reg &= ~ADC_CTRLB_DIFFMODE;
}
#endif
_wait_syncbusy(dev);

6
cpu/sam0_common/periph/dac.c
View File

@ -59,7 +59,7 @@ static inline void _sync(void)
#ifdef DAC_SYNCBUSY_MASK
while (DAC->SYNCBUSY.reg) {}
#else
while (DAC->STATUS.bit.SYNCBUSY) {}
while (DAC->STATUS.reg & DAC_STATUS_SYNCBUSY) {}
#endif
}
@ -110,7 +110,7 @@ int8_t dac_init(dac_t line)
_dac_init_clock(line);
/* Settings can only be changed when DAC is disabled */
DAC->CTRLA.bit.ENABLE = 0;
DAC->CTRLA.reg &= ~DAC_CTRLA_ENABLE;
_sync();
#ifdef DAC_DACCTRL_ENABLE
@ -125,7 +125,7 @@ int8_t dac_init(dac_t line)
#endif
;
DAC->CTRLA.bit.ENABLE = 1;
DAC->CTRLA.reg |= DAC_CTRLA_ENABLE;
_sync();
#ifdef DAC_STATUS_READY

14
cpu/sam0_common/periph/dma.c
View File

@ -90,7 +90,7 @@ void dma_init(void)
NVIC_EnableIRQ(DMAC_IRQn);
#endif
DMAC->CTRL.bit.DMAENABLE = 1;
DMAC->CTRL.reg |= DMAC_CTRL_DMAENABLE;
}
dma_t dma_acquire_channel(void)
@ -255,11 +255,11 @@ void dma_start(dma_t dma)
#ifdef REG_DMAC_CHID
unsigned state = irq_disable();
DMAC->CHID.bit.ID = dma;
DMAC->CHID.reg = DMAC_CHID_ID(dma);
DMAC->CHCTRLA.reg = DMAC_CHCTRLA_ENABLE;
irq_restore(state);
#else
DMAC->Channel[dma].CHCTRLA.bit.ENABLE = 1;
DMAC->Channel[dma].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
#endif
}
@ -274,15 +274,15 @@ void dma_cancel(dma_t dma)
DEBUG("[DMA]: Cancelling active transfer: %u\n", dma);
#ifdef REG_DMAC_CHID
unsigned state = irq_disable();
DMAC->CHID.bit.ID = dma;
DMAC->CHID.reg = DMAC_CHID_ID(dma);
/* Write zero to the enable bit */
DMAC->CHCTRLA.reg = 0;
/* Wait until the active beat is finished */
while (DMAC->CHCTRLA.bit.ENABLE) {}
while (DMAC->CHCTRLA.reg & DMAC_CHCTRLA_ENABLE) {}
irq_restore(state);
#else
DMAC->Channel[dma].CHCTRLA.bit.ENABLE = 0;
while (DMAC->Channel[dma].CHCTRLA.bit.ENABLE) {}
DMAC->Channel[dma].CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE;
while (DMAC->Channel[dma].CHCTRLA.reg & DMAC_CHCTRLA_ENABLE) {}
#endif
}

4
cpu/sam0_common/periph/eth.c
View File

@ -132,7 +132,7 @@ unsigned sam0_read_phy(uint8_t phy, uint8_t addr)
| GMAC_MAN_OP(PHY_READ_OP);
/* Wait for operation completion */
while (!GMAC->NSR.bit.IDLE) {}
while (!(GMAC->NSR.reg & GMAC_NSR_IDLE)) {}
/* return content of shift register */
return (GMAC->MAN.reg & GMAC_MAN_DATA_Msk);
}
@ -148,7 +148,7 @@ void sam0_write_phy(uint8_t phy, uint8_t addr, uint16_t data)
| GMAC_MAN_CLTTO | GMAC_MAN_DATA(data);
/* Wait for operation completion */
while (!GMAC->NSR.bit.IDLE) {}
while (!(GMAC->NSR.reg & GMAC_NSR_IDLE)) {}
}
void sam0_eth_poweron(void)

6
cpu/sam0_common/periph/flashpage.c
View File

@ -58,9 +58,9 @@
static inline void wait_nvm_is_ready(void)
{
#ifdef NVMCTRL_STATUS_READY
while (!_NVMCTRL->STATUS.bit.READY) {}
while (!(_NVMCTRL->STATUS.reg & NVMCTRL_STATUS_READY)) {}
#else
while (!_NVMCTRL->INTFLAG.bit.READY) {}
while (!(_NVMCTRL->INTFLAG.reg & NVMCTRL_INTFLAG_READY)) {}
#endif
}
@ -89,7 +89,7 @@ static void _lock(unsigned state)
/* cached flash contents may have changed - invalidate cache */
#ifdef CMCC
CMCC->MAINT0.bit.INVALL = 1;
CMCC->MAINT0.reg |= CMCC_MAINT0_INVALL;
#endif
irq_restore(state);

12
cpu/sam0_common/periph/gpio.c
View File

@ -242,9 +242,9 @@ void gpio_write(gpio_t pin, int value)
#ifdef MODULE_PERIPH_GPIO_IRQ
#ifdef CPU_COMMON_SAMD21
#define EIC_SYNC() while (_EIC->STATUS.bit.SYNCBUSY)
#define EIC_SYNC() while (_EIC->STATUS.reg & EIC_STATUS_SYNCBUSY)
#else
#define EIC_SYNC() while (_EIC->SYNCBUSY.bit.ENABLE)
#define EIC_SYNC() while (_EIC->SYNCBUSY.reg & EIC_SYNCBUSY_ENABLE)
#endif
static int _exti(gpio_t pin)
@ -349,7 +349,7 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
GCLK->CLKCTRL.reg = EIC_GCLK_ID
| GCLK_CLKCTRL_CLKEN
| GCLK_CLKCTRL_GEN(CONFIG_SAM0_GCLK_GPIO);
while (GCLK->STATUS.bit.SYNCBUSY) {}
while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
#else /* CPU_COMMON_SAML21 */
/* enable clocks for the EIC module */
MCLK->APBAMASK.reg |= MCLK_APBAMASK_EIC;
@ -403,7 +403,7 @@ inline static void reenable_eic(gpio_eic_clock_t clock) {
| GCLK_CLKCTRL_CLKEN
| GCLK_CLKCTRL_GEN(CONFIG_SAM0_GCLK_GPIO);
}
while (GCLK->STATUS.bit.SYNCBUSY) {}
while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
#else
uint32_t ctrla_reg = EIC_CTRLA_ENABLE;
@ -423,7 +423,7 @@ void gpio_pm_cb_enter(int deep)
{
#if defined(PM_SLEEPCFG_SLEEPMODE_STANDBY)
(void) deep;
unsigned mode = PM->SLEEPCFG.bit.SLEEPMODE;
unsigned mode = PM->SLEEPCFG.reg & PM_SLEEPCFG_SLEEPMODE_Msk;
if (mode == PM_SLEEPCFG_SLEEPMODE_STANDBY) {
DEBUG_PUTS("gpio: switching EIC to slow clock");
@ -447,7 +447,7 @@ void gpio_pm_cb_leave(int deep)
#if defined(PM_SLEEPCFG_SLEEPMODE_STANDBY)
(void) deep;
if (PM->SLEEPCFG.bit.SLEEPMODE == PM_SLEEPCFG_SLEEPMODE_STANDBY) {
if ((PM->SLEEPCFG.reg & PM_SLEEPCFG_SLEEPMODE_Msk) == PM_SLEEPCFG_SLEEPMODE_STANDBY) {
DEBUG_PUTS("gpio: switching EIC to fast clock");
reenable_eic(_EIC_CLOCK_FAST);
}

4
cpu/sam0_common/periph/gpio_ll.c
View File

@ -62,12 +62,12 @@ void gpio_ll_mux(gpio_port_t port, uint8_t pin, gpio_mux_t mux)
unsigned irq_state = irq_disable();
if (mux == GPIO_MUX_DISABLED) {
apb->PINCFG[pin].bit.PMUXEN = 0;
apb->PINCFG[pin].reg &= ~PORT_PINCFG_PMUXEN;
}
else {
unsigned pmux_reg = pin >> 1;
unsigned pmux_pos = (pin & 0x01) << 2;
apb->PINCFG[pin].bit.PMUXEN = 1;
apb->PINCFG[pin].reg |= PORT_PINCFG_PMUXEN;
unsigned pmux = apb->PMUX[pmux_reg].reg;
pmux &= ~(PORT_PMUX_PMUXE_Msk << pmux_pos);
pmux |= (unsigned)mux << pmux_pos;

6
cpu/sam0_common/periph/gpio_ll_irq.c
View File

@ -121,10 +121,10 @@ static void disable_trigger(unsigned exti_num)
static void eic_sync(void)
{
#ifdef EIC_STATUS_SYNCBUSY
while (EIC_SEC->STATUS.bit.SYNCBUSY) { }
while (EIC_SEC->STATUS.reg & EIC_STATUS_SYNCBUSY) {}
#endif
#ifdef EIC_SYNCBUSY_ENABLE
while (EIC_SEC->SYNCBUSY.bit.ENABLE) { }
while (EIC_SEC->SYNCBUSY.reg & EIC_SYNCBUSY_ENABLE) {}
#endif
}
@ -136,7 +136,7 @@ static void eic_enable_clock(void)
GCLK->CLKCTRL.reg = EIC_GCLK_ID
| GCLK_CLKCTRL_CLKEN
| GCLK_CLKCTRL_GEN(CONFIG_SAM0_GCLK_GPIO);
while (GCLK->STATUS.bit.SYNCBUSY) {}
while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
#endif
#ifdef MCLK_APBAMASK_EIC
MCLK->APBAMASK.reg |= MCLK_APBAMASK_EIC;

7
cpu/sam0_common/periph/hwrng.c
View File

@ -26,15 +26,16 @@
void hwrng_init(void)
{
/* Enable the MCLK */
MCLK->APBCMASK.bit.TRNG_ = 1;
MCLK->APBCMASK.reg |= MCLK_APBCMASK_TRNG;
/* Enable the TRNG */
TRNG->CTRLA.bit.ENABLE = 1;
TRNG->CTRLA.reg |= TRNG_CTRLA_ENABLE;
}
uint32_t hwrand(void)
{
while (!TRNG->INTFLAG.bit.DATARDY) {}
while (!(TRNG->INTFLAG.reg & TRNG_INTFLAG_DATARDY)) {}
return TRNG->DATA.reg;
}

10
cpu/sam0_common/periph/i2c.c
View File

@ -76,7 +76,7 @@ static inline SercomI2cm *bus(i2c_t dev)
static void _syncbusy(SercomI2cm *dev)
{
#ifdef SERCOM_I2CM_STATUS_SYNCBUSY
while (dev->STATUS.bit.SYNCBUSY) {}
while (dev->STATUS.reg & SERCOM_I2CM_STATUS_SYNCBUSY) {}
#else
while (dev->SYNCBUSY.reg) {}
#endif
@ -88,9 +88,9 @@ static void _reset(SercomI2cm *dev)
while (dev->CTRLA.reg & SERCOM_SPI_CTRLA_SWRST) {}
#ifdef SERCOM_I2CM_STATUS_SYNCBUSY
while (dev->STATUS.bit.SYNCBUSY) {}
while (dev->STATUS.reg & SERCOM_I2CM_STATUS_SYNCBUSY) {}
#else
while (dev->SYNCBUSY.bit.SWRST) {}
while (dev->SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SWRST) {}
#endif
}
@ -311,7 +311,7 @@ void _i2c_poweron(i2c_t dev)
if (bus(dev) == NULL) {
return;
}
bus(dev)->CTRLA.bit.ENABLE = 1;
bus(dev)->CTRLA.reg |= SERCOM_I2CM_CTRLA_ENABLE;
_syncbusy(bus(dev));
}
@ -322,7 +322,7 @@ void _i2c_poweroff(i2c_t dev)
if (bus(dev) == NULL) {
return;
}
bus(dev)->CTRLA.bit.ENABLE = 0;
bus(dev)->CTRLA.reg &= ~SERCOM_I2CM_CTRLA_ENABLE;
_syncbusy(bus(dev));
}

11
cpu/sam0_common/periph/pwm.c
View File

@ -42,6 +42,7 @@
typedef TcCount8 Tcc;
#define TCC_CTRLA_ENABLE TC_CTRLA_ENABLE
#define TCC_SYNCBUSY_CC0 TC_SYNCBUSY_CC0
#define TCC_STATUS_SYNCBUSY TC_STATUS_SYNCBUSY
#ifdef TC_SYNCBUSY_MASK
#define TCC_SYNCBUSY_MASK TC_SYNCBUSY_MASK
#endif
@ -216,8 +217,8 @@ static void poweroff(pwm_t dev)
static void _tc_init(Tc *tc, pwm_mode_t mode, uint8_t prescaler, uint8_t res)
{
/* reset TC module */
tc->COUNT8.CTRLA.bit.SWRST = 1;
while (tc->COUNT8.CTRLA.bit.SWRST) {}
tc->COUNT8.CTRLA.reg |= TC_CTRLA_SWRST;
while (tc->COUNT8.CTRLA.reg & TC_CTRLA_SWRST) {}
/* set PWM mode */
switch (mode) {
@ -250,7 +251,7 @@ static void _tc_init(Tc *tc, pwm_mode_t mode, uint8_t prescaler, uint8_t res)
tc->COUNT8.PER.reg = (res - 1);
#ifdef TC_STATUS_SYNCBUSY
while (tc->COUNT8.STATUS.bit.SYNCBUSY) {}
while (tc->COUNT8.STATUS.reg & TC_STATUS_SYNCBUSY) {}
#else
while (tc->COUNT8.SYNCBUSY.reg) {}
#endif
@ -361,7 +362,7 @@ static void _tc_set(Tc *tc, uint8_t chan, uint16_t value)
tc->COUNT8.CC[chan].reg = value;
#ifdef TC_STATUS_SYNCBUSY
while (tc->COUNT8.STATUS.bit.SYNCBUSY) {}
while (tc->COUNT8.STATUS.reg & TC_STATUS_SYNCBUSY) {}
#else
while (tc->COUNT8.SYNCBUSY.reg & (TC_SYNCBUSY_CC0 << chan)) {}
#endif
@ -375,7 +376,7 @@ static void _tcc_set(Tcc *tcc, uint8_t chan, uint16_t value)
#ifdef TCC_SYNCBUSY_MASK
while (tcc->SYNCBUSY.reg & (TCC_SYNCBUSY_CC0 << chan)) {}
#else
while (tcc->STATUS.bit.SYNCBUSY) {}
while (tcc->STATUS.reg & TCC_STATUS_SYNCBUSY) {}
#endif
}

90
cpu/sam0_common/periph/rtc_rtt.c
View File

@ -113,13 +113,13 @@ static void _wait_syncbusy(void)
#ifdef REG_RTC_MODE0_SYNCBUSY
while (RTC->MODE0.SYNCBUSY.reg) {}
#else
while (RTC->MODE0.STATUS.bit.SYNCBUSY) {}
while (RTC->MODE0.STATUS.reg & RTC_STATUS_SYNCBUSY) {}
#endif
} else {
#ifdef REG_RTC_MODE2_SYNCBUSY
while (RTC->MODE2.SYNCBUSY.reg) {}
#else
while (RTC->MODE2.STATUS.bit.SYNCBUSY) {}
while (RTC->MODE2.STATUS.reg & RTC_STATUS_SYNCBUSY) {}
#endif
}
}
@ -164,12 +164,23 @@ static void _poweroff(void)
}
MAYBE_UNUSED
static inline void _rtc_set_enabled(bool on)
static inline void _rtc_enable(void)
{
#ifdef REG_RTC_MODE2_CTRLA
RTC->MODE2.CTRLA.bit.ENABLE = on;
RTC->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_ENABLE;
#else
RTC->MODE2.CTRL.bit.ENABLE = on;
RTC->MODE2.CTRL.reg |= RTC_MODE2_CTRL_ENABLE;
#endif
_wait_syncbusy();
}
MAYBE_UNUSED
static inline void _rtc_disable(void)
{
#ifdef REG_RTC_MODE2_CTRLA
RTC->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_ENABLE;
#else
RTC->MODE2.CTRL.reg &= ~RTC_MODE2_CTRL_ENABLE;
#endif
_wait_syncbusy();
}
@ -178,10 +189,10 @@ static inline void _rtt_reset(void)
{
#ifdef RTC_MODE0_CTRL_SWRST
RTC->MODE0.CTRL.reg = RTC_MODE0_CTRL_SWRST;
while (RTC->MODE0.CTRL.bit.SWRST) {}
while (RTC->MODE0.CTRL.reg & RTC_MODE0_CTRL_SWRST) {}
#else
RTC->MODE0.CTRLA.reg = RTC_MODE2_CTRLA_SWRST;
while (RTC->MODE0.CTRLA.bit.SWRST) {}
while (RTC->MODE0.CTRLA.reg & RTC_MODE0_CTRLA_SWRST) {}
#endif
}
@ -193,7 +204,7 @@ static void _rtc_clock_setup(void)
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN
| GCLK_CLKCTRL_GEN(SAM0_GCLK_1KHZ)
| GCLK_CLKCTRL_ID_RTC;
while (GCLK->STATUS.bit.SYNCBUSY) {}
while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
}
#endif /* MODULE_PERIPH_RTC */
@ -204,7 +215,7 @@ static void _rtt_clock_setup(void)
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN
| GCLK_CLKCTRL_GEN(SAM0_GCLK_32KHZ)
| GCLK_CLKCTRL_ID_RTC;
while (GCLK->STATUS.bit.SYNCBUSY) {}
while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
}
#endif /* MODULE_PERIPH_RTT */
@ -215,12 +226,12 @@ static void _rtc_clock_setup(void)
{
/* RTC source clock is external oscillator at 1kHz */
#if EXTERNAL_OSC32_SOURCE
OSC32KCTRL->XOSC32K.bit.EN1K = 1;
OSC32KCTRL->XOSC32K.reg |= OSC32KCTRL_XOSC32K_EN1K;
OSC32KCTRL->RTCCTRL.reg = OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K;
/* RTC uses internal 32,768KHz Oscillator */
#elif INTERNAL_OSC32_SOURCE
OSC32KCTRL->OSC32K.bit.EN1K = 1;
OSC32KCTRL->OSC32K.reg |= OSC32KCTRL_OSC32K_EN1K;
OSC32KCTRL->RTCCTRL.reg = OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K;
/* RTC uses Ultra Low Power internal 32,768KHz Oscillator */
@ -238,7 +249,7 @@ static void _rtt_clock_setup(void)
{
/* RTC source clock is external oscillator at 32kHz */
#if EXTERNAL_OSC32_SOURCE
OSC32KCTRL->XOSC32K.bit.EN32K = 1;
OSC32KCTRL->XOSC32K.reg |= OSC32KCTRL_XOSC32K_EN32K;
OSC32KCTRL->RTCCTRL.reg = OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K;
/* RTC uses internal 32,768KHz Oscillator */
@ -319,8 +330,10 @@ void rtc_mem_write(unsigned offset, void *data, size_t len)
static void _rtc_init(void)
{
#ifdef REG_RTC_MODE2_CTRLA
uint32_t mode = ((RTC->MODE2.CTRLA.reg & RTC_MODE2_CTRLA_MODE_Msk)
>> RTC_MODE2_CTRLA_MODE_Pos);
/* skip reset if already in RTC mode */
if (RTC->MODE2.CTRLA.bit.MODE == RTC_MODE2_CTRLA_MODE_CLOCK_Val) {
if (mode == RTC_MODE2_CTRLA_MODE_CLOCK_Val) {
return;
}
@ -343,7 +356,9 @@ static void _rtc_init(void)
RTC->MODE2.CTRLB.reg = RTC_MODE2_CTRLB_GP2EN;
#endif
#else
if (RTC->MODE2.CTRL.bit.MODE == RTC_MODE2_CTRL_MODE_CLOCK_Val) {
uint32_t mode = ((RTC->MODE2.CTRL.reg & RTC_MODE2_CTRL_MODE_Msk)
>> RTC_MODE2_CTRL_MODE_Pos);
if (mode == RTC_MODE2_CTRL_MODE_CLOCK_Val) {
return;
}
@ -371,7 +386,7 @@ void rtc_init(void)
/* Clear interrupt flags */
RTC->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0;
_rtc_set_enabled(1);
_rtc_enable();
NVIC_EnableIRQ(RTC_IRQn);
}
@ -443,9 +458,9 @@ static int _rtc_pin(gpio_t pin)
static void _set_tampctrl(uint32_t reg)
{
_rtc_set_enabled(0);
_rtc_disable();
RTC->MODE0.TAMPCTRL.reg = reg;
_rtc_set_enabled(1);
_rtc_enable();
}
void rtc_tamper_init(void)
@ -512,10 +527,10 @@ void rtc_tamper_enable(void)
NVIC_DisableIRQ(RTC_IRQn);
/* enable tamper detect as wake-up source */
RTC->MODE0.INTENSET.bit.TAMPER = 1;
RTC->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_TAMPER;
/* wait for first tamper event */
while (!RTC->MODE0.INTFLAG.bit.TAMPER && --timeout) {}
while (!(RTC->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_TAMPER) && --timeout) {}
/* clear tamper flag flag */
RTC->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_TAMPER;
@ -524,7 +539,7 @@ void rtc_tamper_enable(void)
NVIC_EnableIRQ(RTC_IRQn);
} else {
/* no spurious event on falling edge */
RTC->MODE0.INTENSET.bit.TAMPER = 1;
RTC->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_TAMPER;
}
DEBUG("tamper enabled\n");
@ -560,17 +575,18 @@ int rtc_get_alarm(struct tm *time)
/* Read alarm register in one time */
alarm.reg = RTC->MODE2.Mode2Alarm[0].ALARM.reg;
time->tm_year = alarm.bit.YEAR + reference_year;
time->tm_year = ((alarm.reg & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos)
+ reference_year;
if ((time->tm_year < reference_year) ||
(time->tm_year > (reference_year + 63))) {
return -1;
}
time->tm_mon = alarm.bit.MONTH - 1;
time->tm_mday = alarm.bit.DAY;
time->tm_hour = alarm.bit.HOUR;
time->tm_min = alarm.bit.MINUTE;
time->tm_sec = alarm.bit.SECOND;
time->tm_mon = ((alarm.reg & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos) - 1;
time->tm_mday = ((alarm.reg & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos);
time->tm_hour = ((alarm.reg & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos);
time->tm_min = ((alarm.reg & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos);
time->tm_sec = ((alarm.reg & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos);
return 0;
}
@ -583,18 +599,18 @@ int rtc_get_time(struct tm *time)
_read_req();
clock.reg = RTC->MODE2.CLOCK.reg;
time->tm_year = clock.bit.YEAR + reference_year;
time->tm_year = ((clock.reg & RTC_MODE2_CLOCK_YEAR_Msk) >> RTC_MODE2_CLOCK_YEAR_Pos)
+ reference_year;
if ((time->tm_year < reference_year) ||
(time->tm_year > (reference_year + 63))) {
return -1;
}
time->tm_mon = clock.bit.MONTH - 1;
time->tm_mday = clock.bit.DAY;
time->tm_hour = clock.bit.HOUR;
time->tm_min = clock.bit.MINUTE;
time->tm_sec = clock.bit.SECOND;
time->tm_mon = ((clock.reg & RTC_MODE2_CLOCK_MONTH_Msk) >> RTC_MODE2_CLOCK_MONTH_Pos) - 1;
time->tm_mday = ((clock.reg & RTC_MODE2_CLOCK_DAY_Msk) >> RTC_MODE2_CLOCK_DAY_Pos);
time->tm_hour = ((clock.reg & RTC_MODE2_CLOCK_HOUR_Msk) >> RTC_MODE2_CLOCK_HOUR_Pos);
time->tm_min = ((clock.reg & RTC_MODE2_CLOCK_MINUTE_Msk) >> RTC_MODE2_CLOCK_MINUTE_Pos);
time->tm_sec = ((clock.reg & RTC_MODE2_CLOCK_SECOND_Msk) >> RTC_MODE2_CLOCK_SECOND_Pos);
return 0;
}
@ -781,7 +797,7 @@ static void _isr_rtc(void)
return;
}
if (RTC->MODE2.INTFLAG.bit.ALARM0) {
if (RTC->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) {
/* clear flag */
RTC->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0;
@ -797,13 +813,13 @@ static void _isr_rtt(void)
return;
}
if (RTC->MODE0.INTFLAG.bit.OVF) {
if (RTC->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) {
RTC->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF;
if (overflow_cb.cb) {
overflow_cb.cb(overflow_cb.arg);
}
}
if (RTC->MODE0.INTFLAG.bit.CMP0) {
if (RTC->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) {
/* clear flag */
RTC->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0;
/* disable interrupt */
@ -818,7 +834,7 @@ static void _isr_rtt(void)
static void _isr_tamper(void)
{
#ifdef RTC_MODE0_INTFLAG_TAMPER
if (RTC->MODE0.INTFLAG.bit.TAMPER) {
if (RTC->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_TAMPER) {
RTC->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_TAMPER;
if (tamper_cb.cb) {
tamper_cb.cb(tamper_cb.arg);

40
cpu/sam0_common/periph/spi.c
View File

@ -73,20 +73,26 @@ static inline bool _is_qspi(spi_t bus)
#endif
}
static inline void _qspi_clk(unsigned on)
static inline void _qspi_clk_enable(void)
{
#ifdef QSPI
/* enable/disable QSPI clock */
MCLK->APBCMASK.bit.QSPI_ = on;
#else
(void)on;
/* enable QSPI clock */
MCLK->APBCMASK.reg |= MCLK_APBCMASK_QSPI;
#endif
}
static inline void _qspi_clk_disable(void)
{
#ifdef QSPI
/* disable QSPI clock */
MCLK->APBCMASK.reg &= ~MCLK_APBCMASK_QSPI;
#endif
}
static inline void poweron(spi_t bus)
{
if (_is_qspi(bus)) {
_qspi_clk(1);
_qspi_clk_enable();
} else {
sercom_clk_en(dev(bus));
}
@ -95,7 +101,7 @@ static inline void poweron(spi_t bus)
static inline void poweroff(spi_t bus)
{
if (_is_qspi(bus)) {
_qspi_clk(0);
_qspi_clk_disable();
} else {
sercom_clk_dis(dev(bus));
}
@ -107,9 +113,9 @@ static inline void _reset(SercomSpi *dev)
while (dev->CTRLA.reg & SERCOM_SPI_CTRLA_SWRST) {}
#ifdef SERCOM_SPI_STATUS_SYNCBUSY
while (dev->STATUS.bit.SYNCBUSY) {}
while (dev->STATUS.reg & SERCOM_SPI_STATUS_SYNCBUSY) {}
#else
while (dev->SYNCBUSY.bit.SWRST) {}
while (dev->SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_SWRST) {}
#endif
}
@ -118,7 +124,7 @@ static inline void _disable(SercomSpi *dev)
dev->CTRLA.reg = 0;
#ifdef SERCOM_SPI_STATUS_SYNCBUSY
while (dev->STATUS.bit.SYNCBUSY) {}
while (dev->STATUS.reg & SERCOM_SPI_STATUS_SYNCBUSY) {}
#else
while (dev->SYNCBUSY.reg) {}
#endif
@ -126,10 +132,10 @@ static inline void _disable(SercomSpi *dev)
static inline void _enable(SercomSpi *dev)
{
dev->CTRLA.bit.ENABLE = 1;
dev->CTRLA.reg |= SERCOM_SPI_CTRLA_ENABLE;
#ifdef SERCOM_SPI_STATUS_SYNCBUSY
while (dev->STATUS.bit.SYNCBUSY) {}
while (dev->STATUS.reg & SERCOM_SPI_STATUS_SYNCBUSY) {}
#else
while (dev->SYNCBUSY.reg) {}
#endif
@ -179,7 +185,7 @@ static inline void _init_dma(spi_t bus, const volatile void *reg_rx, volatile vo
static void _init_qspi(spi_t bus)
{
/* reset the peripheral */
QSPI->CTRLA.bit.SWRST = 1;
QSPI->CTRLA.reg |= QSPI_CTRLA_SWRST;
QSPI->CTRLB.reg = QSPI_CTRLB_MODE_SPI
| QSPI_CTRLB_CSMODE_LASTXFER
@ -202,13 +208,13 @@ static void _qspi_acquire(spi_mode_t mode, spi_clk_t clk)
| (mode << 1);
_mode &= 0x3;
QSPI->CTRLA.bit.ENABLE = 1;
QSPI->CTRLA.reg |= QSPI_CTRLA_ENABLE;
QSPI->BAUD.reg = QSPI_BAUD_BAUD(baud) | _mode;
}
static inline void _qspi_release(void)
{
QSPI->CTRLA.bit.ENABLE = 0;
QSPI->CTRLA.reg &= ~QSPI_CTRLA_ENABLE;
}
static void _qspi_blocking_transfer(const void *out, void *in, size_t len)
@ -223,7 +229,7 @@ static void _qspi_blocking_transfer(const void *out, void *in, size_t len)
QSPI->TXDATA.reg = tmp;
/* wait until byte has been sampled on MISO */
while (QSPI->INTFLAG.bit.RXC == 0) {}
while (!(QSPI->INTFLAG.reg & QSPI_INTFLAG_RXC)) {}
/* consume the byte */
tmp = QSPI->RXDATA.reg;
@ -320,7 +326,7 @@ static void _spi_blocking_transfer(spi_t bus, const void *out, void *in, size_t
dev(bus)->DATA.reg = tmp;
/* wait until byte has been sampled on MISO */
while (dev(bus)->INTFLAG.bit.RXC == 0) {}
while (!(dev(bus)->INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC)) {}
/* consume the byte */
tmp = dev(bus)->DATA.reg;

32
cpu/sam0_common/periph/timer.c
View File

@ -125,7 +125,9 @@ static inline void _set_mfrq(tim_t tim)
#ifdef TC_WAVE_WAVEGEN_MFRQ
dev(tim)->WAVE.reg = TC_WAVE_WAVEGEN_MFRQ;
#else
dev(tim)->CTRLA.bit.WAVEGEN = TC_CTRLA_WAVEGEN_MFRQ_Val;
uint32_t reg = dev(tim)->CTRLA.reg;
dev(tim)->CTRLA.reg = ((reg & ~TC_CTRLA_WAVEGEN_Msk) |
TC_CTRLA_WAVEGEN(TC_CTRLA_WAVEGEN_MFRQ_Val));
#endif
}
@ -135,7 +137,9 @@ static inline void _set_nfrq(tim_t tim)
#ifdef TC_WAVE_WAVEGEN_NFRQ
dev(tim)->WAVE.reg = TC_WAVE_WAVEGEN_NFRQ;
#else
dev(tim)->CTRLA.bit.WAVEGEN = TC_CTRLA_WAVEGEN_NFRQ_Val;
uint32_t reg = dev(tim)->CTRLA.reg;
dev(tim)->CTRLA.reg = ((reg & ~TC_CTRLA_WAVEGEN_Msk) |
TC_CTRLA_WAVEGEN(TC_CTRLA_WAVEGEN_NFRQ_Val));
#endif
}
@ -188,8 +192,8 @@ int timer_init(tim_t tim, uint32_t freq, timer_cb_t cb, void *arg)
timer_stop(tim);
/* reset the timer */
dev(tim)->CTRLA.bit.SWRST = 1;
while (dev(tim)->CTRLA.bit.SWRST) {}
dev(tim)->CTRLA.reg |= TC_CTRLA_SWRST;
while (dev(tim)->CTRLA.reg & TC_CTRLA_SWRST) {}
dev(tim)->CTRLA.reg = cfg->flags
#ifdef TC_CTRLA_WAVEGEN_NFRQ
@ -332,12 +336,13 @@ int timer_clear(tim_t tim, int channel)
unsigned int timer_read(tim_t tim)
{
/* WORKAROUND to prevent being stuck there if timer not init */
if (!dev(tim)->CTRLA.bit.ENABLE) {
if (!(dev(tim)->CTRLA.reg & TC_CTRLA_ENABLE)) {
return 0;
}
/* request synchronisation */
#ifdef TC_CTRLBSET_CMD_READSYNC_Val
uint32_t cmd;
dev(tim)->CTRLBSET.reg = TC_CTRLBSET_CMD_READSYNC;
/* work around a possible hardware bug where it takes some
cycles for the timer peripheral to set the SYNCBUSY/READSYNC bit
@ -345,7 +350,10 @@ unsigned int timer_read(tim_t tim)
The problem was observed on SAME54.
*/
while(dev(tim)->CTRLBSET.bit.CMD == TC_CTRLBSET_CMD_READSYNC_Val) {}
do {
cmd = ((dev(tim)->CTRLBSET.reg & TC_CTRLBSET_CMD_Msk) >> TC_CTRLBSET_CMD_Pos);
} while(cmd == TC_CTRLBSET_CMD_READSYNC_Val);
#else
dev(tim)->READREQ.reg = TC_READREQ_RREQ | TC_READREQ_ADDR(TC_COUNT32_COUNT_OFFSET);
#endif
@ -359,13 +367,13 @@ void timer_stop(tim_t tim)
{
#if IS_ACTIVE(MODULE_PM_LAYERED) && defined(SAM0_TIMER_PM_BLOCK)
/* unblock power mode if the timer is running */
if (dev(tim)->CTRLA.bit.ENABLE) {
if (dev(tim)->CTRLA.reg & TC_CTRLA_ENABLE) {
DEBUG("[timer %d] pm_unblock\n", tim);
pm_unblock(SAM0_TIMER_PM_BLOCK);
}
#endif
dev(tim)->CTRLA.bit.ENABLE = 0;
dev(tim)->CTRLA.reg &= ~TC_CTRLA_ENABLE;
wait_synchronization(tim);
}
@ -375,13 +383,13 @@ void timer_start(tim_t tim)
#if IS_ACTIVE(MODULE_PM_LAYERED) && defined(SAM0_TIMER_PM_BLOCK)
/* block power mode if the timer is not running, yet */
if (!dev(tim)->CTRLA.bit.ENABLE) {
if (!(dev(tim)->CTRLA.reg & TC_CTRLA_ENABLE)) {
DEBUG("[timer %d] pm_block\n", tim);
pm_block(SAM0_TIMER_PM_BLOCK);
}
#endif
dev(tim)->CTRLA.bit.ENABLE = 1;
dev(tim)->CTRLA.reg |= TC_CTRLA_ENABLE;
}
static inline void timer_isr(tim_t tim)
@ -392,7 +400,7 @@ static inline void timer_isr(tim_t tim)
/* Acknowledge all interrupts */
tc->INTFLAG.reg = status;
if ((status & TC_INTFLAG_MC0) && tc->INTENSET.bit.MC0) {
if ((status & TC_INTFLAG_MC0) && (tc->INTENSET.reg & TC_INTENSET_MC0)) {
if (is_oneshot(tim, 0)) {
tc->INTENCLR.reg = TC_INTENCLR_MC0;
@ -403,7 +411,7 @@ static inline void timer_isr(tim_t tim)
}
}
if ((status & TC_INTFLAG_MC1) && tc->INTENSET.bit.MC1) {
if ((status & TC_INTFLAG_MC1) && (tc->INTENSET.reg & TC_INTENSET_MC1)) {
if (is_oneshot(tim, 1)) {
tc->INTENCLR.reg = TC_INTENCLR_MC1;

89
cpu/sam0_common/periph/uart.c
View File

@ -82,7 +82,7 @@ static inline void _syncbusy(SercomUsart *dev)
#ifdef SERCOM_USART_SYNCBUSY_MASK
while (dev->SYNCBUSY.reg) {}
#else
while (dev->STATUS.bit.SYNCBUSY) {}
while (dev->STATUS.reg & SERCOM_USART_STATUS_SYNCBUSY) {}
#endif
}
@ -92,9 +92,9 @@ static inline void _reset(SercomUsart *dev)
while (dev->CTRLA.reg & SERCOM_SPI_CTRLA_SWRST) {}
#ifdef SERCOM_USART_SYNCBUSY_MASK
while (dev->SYNCBUSY.bit.SWRST) {}
while (dev->SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_SWRST) {}
#else
while (dev->STATUS.bit.SYNCBUSY) {}
while (dev->STATUS.reg & SERCOM_USART_STATUS_SYNCBUSY) {}
#endif
}
@ -187,13 +187,13 @@ int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
#if IS_ACTIVE(MODULE_PM_LAYERED) && defined(SAM0_UART_PM_BLOCK)
/* clear previously blocked power modes */
if (dev(uart)->CTRLA.bit.ENABLE) {
if (dev(uart)->CTRLA.reg & SERCOM_USART_CTRLA_ENABLE) {
/* RX IRQ is enabled */
if (dev(uart)->INTENSET.bit.RXC) {
if (dev(uart)->INTENSET.reg & SERCOM_USART_INTENSET_RXC) {
pm_unblock(SAM0_UART_PM_BLOCK);
}
/* data reg empty IRQ is enabled -> sending data was in progress */
if (dev(uart)->INTENSET.bit.DRE) {
if (dev(uart)->INTENSET.reg & SERCOM_USART_INTENSET_DRE) {
pm_unblock(SAM0_UART_PM_BLOCK);
}
}
@ -363,7 +363,7 @@ void uart_write(uart_t uart, const uint8_t *data, size_t len)
return;
}
if (!dev(uart)->CTRLA.bit.ENABLE) {
if (!(dev(uart)->CTRLA.reg & SERCOM_USART_CTRLA_ENABLE)) {
return;
}
@ -372,7 +372,7 @@ void uart_write(uart_t uart, const uint8_t *data, size_t len)
if (irq_is_in() || __get_PRIMASK()) {
/* if ring buffer is full free up a spot */
if (tsrb_full(&uart_tx_rb[uart])) {
while (!dev(uart)->INTFLAG.bit.DRE) {}
while (!(dev(uart)->INTFLAG.reg & SERCOM_USART_INTFLAG_DRE)) {}
dev(uart)->DATA.reg = tsrb_get_one(&uart_tx_rb[uart]);
}
tsrb_add_one(&uart_tx_rb[uart], *data);
@ -386,7 +386,7 @@ void uart_write(uart_t uart, const uint8_t *data, size_t len)
/* tsrb_add_one() is blocking the thread. It may happen that
* the corresponding ISR has turned off DRE IRQs and, thus,
* unblocked the corresponding power mode. */
if (!dev(uart)->INTENSET.bit.DRE) {
if (!(dev(uart)->INTENSET.reg & SERCOM_USART_INTENSET_DRE)) {
pm_block(SAM0_UART_PM_BLOCK);
}
dev(uart)->INTENSET.reg = SERCOM_USART_INTENSET_DRE;
@ -397,10 +397,10 @@ void uart_write(uart_t uart, const uint8_t *data, size_t len)
}
#else
for (const void* end = data + len; data != end; ++data) {
while (!dev(uart)->INTFLAG.bit.DRE) {}
while (!(dev(uart)->INTFLAG.reg & SERCOM_USART_INTFLAG_DRE)) {}
dev(uart)->DATA.reg = *data;
}
while (!dev(uart)->INTFLAG.bit.TXC) {}
while (!(dev(uart)->INTFLAG.reg & SERCOM_USART_INTFLAG_TXC)) {}
#endif
}
@ -412,13 +412,13 @@ void uart_poweron(uart_t uart)
unsigned state = irq_disable();
#if IS_ACTIVE(MODULE_PM_LAYERED) && defined(SAM0_UART_PM_BLOCK)
/* block required power modes */
if (!dev(uart)->CTRLA.bit.ENABLE) {
if (!(dev(uart)->CTRLA.reg & SERCOM_USART_CTRLA_ENABLE)) {
/* RX IRQ is enabled */
if (dev(uart)->INTENSET.bit.RXC) {
if (dev(uart)->INTENSET.reg & SERCOM_USART_INTENSET_RXC) {
pm_block(SAM0_UART_PM_BLOCK);
}
/* data reg empty IRQ is enabled -> sending data was in progress */
if (dev(uart)->INTENSET.bit.DRE) {
if (dev(uart)->INTENSET.reg & SERCOM_USART_INTENSET_DRE) {
pm_block(SAM0_UART_PM_BLOCK);
}
}
@ -435,13 +435,13 @@ void uart_poweroff(uart_t uart)
unsigned state = irq_disable();
#if IS_ACTIVE(MODULE_PM_LAYERED) && defined(SAM0_UART_PM_BLOCK)
/* clear blocked power modes */
if (dev(uart)->CTRLA.bit.ENABLE) {
if (dev(uart)->CTRLA.reg & SERCOM_USART_CTRLA_ENABLE) {
/* RX IRQ is enabled */
if (dev(uart)->INTENSET.bit.RXC) {
if (dev(uart)->INTENSET.reg & SERCOM_USART_INTENSET_RXC) {
pm_unblock(SAM0_UART_PM_BLOCK);
}
/* data reg empty IRQ is enabled -> sending data is in progress */
if (dev(uart)->INTENSET.bit.DRE) {
if (dev(uart)->INTENSET.reg & SERCOM_USART_INTENSET_DRE) {
pm_unblock(SAM0_UART_PM_BLOCK);
}
}
@ -461,7 +461,7 @@ bool uart_collision_detected(uart_t uart)
*/
_syncbusy(dev(uart));
bool collision = dev(uart)->STATUS.bit.COLL;
bool collision = dev(uart)->STATUS.reg & SERCOM_USART_STATUS_COLL;
dev(uart)->STATUS.reg = SERCOM_USART_STATUS_COLL;
return collision;
}
@ -469,20 +469,20 @@ bool uart_collision_detected(uart_t uart)
void uart_collision_detect_enable(uart_t uart)
{
/* CTRLB is enable protected */
dev(uart)->CTRLA.bit.ENABLE = 0;
dev(uart)->CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE;
_syncbusy(dev(uart));
/* clear stale collision flag */
dev(uart)->STATUS.reg = SERCOM_USART_STATUS_COLL;
/* enable collision detection */
dev(uart)->CTRLB.bit.COLDEN = 1;
dev(uart)->CTRLB.reg |= SERCOM_USART_CTRLB_COLDEN;
/* disable RX interrupt */
dev(uart)->INTENCLR.bit.RXC = 1;
dev(uart)->INTENCLR.reg = SERCOM_USART_INTENCLR_RXC;
/* re-enable UART */
dev(uart)->CTRLA.bit.ENABLE = 1;
dev(uart)->CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE;
/* wait for config to be applied */
_syncbusy(dev(uart));
@ -491,7 +491,7 @@ void uart_collision_detect_enable(uart_t uart)
static void _drain_rxbuf(SercomUsart *dev)
{
/* clear readback bytes from receive buffer */
while (dev->INTFLAG.bit.RXC) {
while (dev->INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) {
dev->DATA.reg;
}
}
@ -507,13 +507,13 @@ void uart_collision_detect_disable(uart_t uart)
ctrlb &= ~SERCOM_USART_CTRLB_COLDEN;
/* CTRLB is enable protected */
dev(uart)->CTRLA.bit.ENABLE = 0;
dev(uart)->CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE;
_syncbusy(dev(uart));
dev(uart)->CTRLB.reg = ctrlb;
/* re-enable UART */
dev(uart)->CTRLA.bit.ENABLE = 1;
dev(uart)->CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE;
/* wait for config to be applied */
_syncbusy(dev(uart));
@ -523,7 +523,7 @@ void uart_collision_detect_disable(uart_t uart)
/* re-enable RX complete IRQ */
if (uart_ctx[uart].rx_cb) {
dev(uart)->INTENSET.bit.RXC = 1;
dev(uart)->INTENSET.reg = SERCOM_USART_INTENSET_RXC;
}
}
#endif
@ -546,23 +546,36 @@ int uart_mode(uart_t uart, uart_data_bits_t data_bits, uart_parity_t parity,
}
/* Disable UART first to remove write protect */
dev(uart)->CTRLA.bit.ENABLE = 0;
dev(uart)->CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE;
_syncbusy(dev(uart));
dev(uart)->CTRLB.bit.CHSIZE = data_bits;
uint32_t ctrlb = dev(uart)->CTRLB.reg;
if (parity == UART_PARITY_NONE) {
dev(uart)->CTRLA.bit.FORM = 0x0;
dev(uart)->CTRLA.reg &= ~SERCOM_USART_CTRLA_FORM_Msk;
}
else {
dev(uart)->CTRLA.bit.FORM = 0x1;
dev(uart)->CTRLB.bit.PMODE = (parity == UART_PARITY_ODD) ? 1 : 0;
dev(uart)->CTRLA.reg |= SERCOM_USART_CTRLA_FORM(1);
if (parity == UART_PARITY_ODD) {
ctrlb |= SERCOM_USART_CTRLB_PMODE;
}
else {
ctrlb &= ~SERCOM_USART_CTRLB_PMODE;
}
}
dev(uart)->CTRLB.bit.SBMODE = (stop_bits == UART_STOP_BITS_1) ? 0 : 1;
if (stop_bits == UART_STOP_BITS_1) {
ctrlb &= ~SERCOM_USART_CTRLB_SBMODE;
}
else {
ctrlb |= SERCOM_USART_CTRLB_SBMODE;
}
dev(uart)->CTRLB.reg = ((ctrlb & ~SERCOM_USART_CTRLB_CHSIZE_Msk) |
SERCOM_USART_CTRLB_CHSIZE(data_bits));
/* Enable UART again */
dev(uart)->CTRLA.bit.ENABLE = 1;
dev(uart)->CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE;
_syncbusy(dev(uart));
return UART_OK;
@ -573,7 +586,7 @@ int uart_mode(uart_t uart, uart_data_bits_t data_bits, uart_parity_t parity,
void uart_rxstart_irq_configure(uart_t uart, uart_rxstart_cb_t cb, void *arg)
{
/* CTRLB is enable-proteced */
dev(uart)->CTRLA.bit.ENABLE = 0;
dev(uart)->CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE;
/* set start of frame detection enable */
dev(uart)->CTRLB.reg |= SERCOM_USART_CTRLB_SFDE;
@ -582,7 +595,7 @@ void uart_rxstart_irq_configure(uart_t uart, uart_rxstart_cb_t cb, void *arg)
uart_ctx[uart].rxs_arg = arg;
/* enable UART again */
dev(uart)->CTRLA.bit.ENABLE = 1;
dev(uart)->CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE;
}
void uart_rxstart_irq_enable(uart_t uart)
@ -628,13 +641,15 @@ static inline void irq_handler(unsigned uartnum)
dev(uartnum)->INTFLAG.reg = status & ~SERCOM_USART_INTFLAG_TXC;
#if !defined(UART_HAS_TX_ISR) && defined(MODULE_PERIPH_UART_NONBLOCKING)
if ((status & SERCOM_USART_INTFLAG_DRE) && dev(uartnum)->INTENSET.bit.DRE) {
if ((status & SERCOM_USART_INTFLAG_DRE) &&
(dev(uartnum)->INTENSET.reg & SERCOM_USART_INTENSET_DRE)) {
irq_handler_tx(uartnum);
}
#endif
#ifdef MODULE_PERIPH_UART_RXSTART_IRQ
if (status & SERCOM_USART_INTFLAG_RXS && dev(uartnum)->INTENSET.bit.RXS) {
if ((status & SERCOM_USART_INTFLAG_RXS) &&
(dev(uartnum)->INTENSET.reg & SERCOM_USART_INTENSET_RXS)) {
uart_ctx[uartnum].rxs_cb(uart_ctx[uartnum].rxs_arg);
}
#endif

67
cpu/sam0_common/periph/usbdev.c
View File

@ -179,7 +179,9 @@ static int _bank_set_size(usbdev_ep_t *ep)
default:
return -1;
}
bank->PCKSIZE.bit.SIZE = val;
uint32_t reg = bank->PCKSIZE.reg;
bank->PCKSIZE.reg = ((reg & ~USB_DEVICE_PCKSIZE_SIZE_Msk) | USB_DEVICE_PCKSIZE_SIZE(val));
return val;
}
@ -210,19 +212,27 @@ static bool _ep_in_flags_set(UsbDeviceEndpoint *ep_reg)
static void _set_address(sam0_common_usb_t *dev, uint8_t addr)
{
dev->config->device->DADD.bit.DADD = addr;
uint32_t dadd = dev->config->device->DADD.reg;
/* Only enable the address if it is nonzero */
dev->config->device->DADD.bit.ADDEN = addr ? 1 : 0;
if (addr) {
dadd |= USB_DEVICE_DADD_ADDEN;
}
else {
dadd &= ~USB_DEVICE_DADD_ADDEN;
}
dev->config->device->DADD.reg = (dadd & ~USB_DEVICE_DADD_DADD_Msk)
| USB_DEVICE_DADD_DADD(addr);
}
static bool _syncbusy_enable(sam0_common_usb_t *dev)
{
return dev->config->device->SYNCBUSY.bit.ENABLE;
return dev->config->device->SYNCBUSY.reg & USB_SYNCBUSY_ENABLE;
}
static bool _syncbusy_swrst(sam0_common_usb_t *dev)
{
return dev->config->device->SYNCBUSY.bit.SWRST;
return dev->config->device->SYNCBUSY.reg & USB_SYNCBUSY_SWRST;
}
static inline void _poweron(sam0_common_usb_t *dev)
@ -306,7 +316,7 @@ static void _usbdev_init(usbdev_t *dev)
sam0_common_usb_t *usbdev = (sam0_common_usb_t *)dev;
/* clear previously set pm blockers */
if (usbdev->config->device->CTRLA.bit.ENABLE) {
if (usbdev->config->device->CTRLA.reg & USB_CTRLA_ENABLE) {
#if IS_ACTIVE(MODULE_PM_LAYERED) && defined(SAM0_USB_IDLE_PM_BLOCK)
pm_unblock(SAM0_USB_IDLE_PM_BLOCK);
#endif
@ -342,7 +352,10 @@ static void _usbdev_init(usbdev_t *dev)
USB_PADCAL_TRIM((*(uint32_t *)USB_FUSES_TRIM_ADDR >>
USB_FUSES_TRIM_Pos));
usbdev->config->device->CTRLB.bit.SPDCONF = USB_DEVICE_CTRLB_SPDCONF_FS;
uint32_t ctrlb = usbdev->config->device->CTRLB.reg;
usbdev->config->device->CTRLB.reg = (ctrlb & ~USB_DEVICE_CTRLB_SPDCONF_Msk)
| USB_DEVICE_CTRLB_SPDCONF_FS;
_enable_irq(usbdev);
#if IS_ACTIVE(MODULE_PM_LAYERED) && defined(SAM0_USB_IDLE_PM_BLOCK)
@ -437,10 +450,10 @@ static void _ep_disable(usbdev_ep_t *ep)
UsbDeviceEndpoint *ep_reg = _ep_reg_from_ep(ep);
if (ep->dir == USB_EP_DIR_OUT) {
ep_reg->EPCFG.bit.EPTYPE0 = 0;
ep_reg->EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE0_Msk;
}
else {
ep_reg->EPCFG.bit.EPTYPE1 = 0;
ep_reg->EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE1_Msk;
}
}
@ -450,6 +463,7 @@ static void _ep_enable(usbdev_ep_t *ep)
ep->dir == USB_EP_DIR_OUT ? "OUT" : "IN");
UsbDeviceEndpoint *ep_reg = _ep_reg_from_ep(ep);
uint8_t type = 0;
uint32_t epcfg;
switch (ep->type) {
case USB_EP_TYPE_CONTROL:
@ -469,10 +483,14 @@ static void _ep_enable(usbdev_ep_t *ep)
assert(false);
}
if (ep->dir == USB_EP_DIR_OUT) {
ep_reg->EPCFG.bit.EPTYPE0 = type;
epcfg = ep_reg->EPCFG.reg;
ep_reg->EPCFG.reg = (epcfg & ~USB_DEVICE_EPCFG_EPTYPE0_Msk)
| USB_DEVICE_EPCFG_EPTYPE0(type);
}
else {
ep_reg->EPCFG.bit.EPTYPE1 = type;
epcfg = ep_reg->EPCFG.reg;
ep_reg->EPCFG.reg = (epcfg & ~USB_DEVICE_EPCFG_EPTYPE1_Msk)
| USB_DEVICE_EPCFG_EPTYPE1(type);
}
}
@ -534,13 +552,13 @@ static void _usbdev_esr(usbdev_t *dev)
sam0_common_usb_t *usbdev = (sam0_common_usb_t *)dev;
if (usbdev->config->device->INTFLAG.reg) {
if (usbdev->config->device->INTFLAG.bit.EORST) {
if (usbdev->config->device->INTFLAG.reg & USB_DEVICE_INTFLAG_EORST) {
/* Clear flag */
usbdev->config->device->INTFLAG.reg = USB_DEVICE_INTFLAG_EORST;
usbdev->usbdev.cb(&usbdev->usbdev, USBDEV_EVENT_RESET);
usbdev->config->device->INTFLAG.reg = USB_DEVICE_INTFLAG_EORST;
}
else if (usbdev->config->device->INTFLAG.bit.SUSPEND &&
else if ((usbdev->config->device->INTFLAG.reg & USB_DEVICE_INTFLAG_SUSPEND) &&
!usbdev->suspended) {
usbdev->config->device->INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP |
USB_DEVICE_INTFLAG_SUSPEND;
@ -551,7 +569,7 @@ static void _usbdev_esr(usbdev_t *dev)
pm_unblock(SAM0_USB_ACTIVE_PM_BLOCK);
#endif
}
else if (usbdev->config->device->INTFLAG.bit.WAKEUP &&
else if ((usbdev->config->device->INTFLAG.reg & USB_DEVICE_INTFLAG_WAKEUP) &&
usbdev->suspended) {
usbdev->config->device->INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP |
USB_DEVICE_INTFLAG_SUSPEND;
@ -619,12 +637,12 @@ usbopt_enable_t _ep_get_stall(usbdev_ep_t *ep)
UsbDeviceEndpoint *ep_reg = _ep_reg_from_ep(ep);
if (ep->dir == USB_EP_DIR_IN) {
res = ep_reg->EPSTATUSSET.bit.STALLRQ1
res = (ep_reg->EPSTATUSSET.reg & USB_DEVICE_EPSTATUSSET_STALLRQ1)
? USBOPT_ENABLE
: USBOPT_DISABLE;
}
else {
res = ep_reg->EPSTATUSSET.bit.STALLRQ0
res = (ep_reg->EPSTATUSSET.reg & USB_DEVICE_EPSTATUSSET_STALLRQ0)
? USBOPT_ENABLE
: USBOPT_DISABLE;
}
@ -644,7 +662,8 @@ static void _usbdev_ep_init(usbdev_ep_t *ep)
static size_t _ep_get_available(usbdev_ep_t *ep)
{
return _bank_from_ep(ep)->PCKSIZE.bit.BYTE_COUNT;
return ((_bank_from_ep(ep)->PCKSIZE.reg & USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk)
>> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos);
}
static int _usbdev_ep_get(usbdev_ep_t *ep, usbopt_ep_t opt,
@ -710,7 +729,9 @@ static int _usbdev_ep_xmit(usbdev_ep_t *ep, uint8_t *buf, size_t len)
_bank_from_ep(ep)->ADDR.reg = (uint32_t)(intptr_t)buf;
if (ep->dir == USB_EP_DIR_IN) {
_disable_ep_stall_in(ep_reg);
_bank_from_ep(ep)->PCKSIZE.bit.BYTE_COUNT = len;
uint32_t reg = _bank_from_ep(ep)->PCKSIZE.reg;
_bank_from_ep(ep)->PCKSIZE.reg = (reg & ~USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk)
| USB_DEVICE_PCKSIZE_BYTE_COUNT(len);
ep_reg->EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK1RDY;
}
else {
@ -731,15 +752,15 @@ static void _usbdev_ep_esr(usbdev_ep_t *ep)
signed event = -1;
if (ep->dir == USB_EP_DIR_OUT) {
if (ep_reg->EPINTFLAG.bit.TRCPT0) {
if (ep_reg->EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) {
ep_reg->EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
event = USBDEV_EVENT_TR_COMPLETE;
}
else if (ep_reg->EPINTFLAG.bit.RXSTP) {
else if (ep_reg->EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) {
ep_reg->EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP;
event = USBDEV_EVENT_TR_COMPLETE;
}
else if (ep_reg->EPINTFLAG.bit.STALL0) {
else if (ep_reg->EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) {
ep_reg->EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0;
event = USBDEV_EVENT_TR_STALL;
}
@ -749,12 +770,12 @@ static void _usbdev_ep_esr(usbdev_ep_t *ep)
}
}
else {
if (ep_reg->EPINTFLAG.bit.TRCPT1) {
if (ep_reg->EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) {
DEBUG("sam_usb: Transfer IN complete\n");
ep_reg->EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
event = USBDEV_EVENT_TR_COMPLETE;
}
else if (ep_reg->EPINTFLAG.bit.STALL1) {
else if (ep_reg->EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) {
ep_reg->EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1;
event = USBDEV_EVENT_TR_STALL;
}

41
cpu/sam0_common/periph/wdt.c
View File

@ -41,26 +41,33 @@
#define WDT_CONFIG_PER_16K_Val WDT_CONFIG_PER_CYC16384_Val
#endif
static inline void _set_enable(bool on)
static inline void _wdt_enable(void)
{
/* work around strange watchdog behaviour if IDLE2 is used on samd21 */
#ifdef CPU_COMMON_SAMD21
if (on) {
pm_block(1);
}
#endif
#ifdef WDT_CTRLA_ENABLE
WDT->CTRLA.bit.ENABLE = on;
WDT->CTRLA.reg |= WDT_CTRLA_ENABLE;
#else
WDT->CTRL.bit.ENABLE = on;
WDT->CTRL.reg |= WDT_CTRL_ENABLE;
#endif
}
static inline void _wdt_disable(void)
{
#ifdef WDT_CTRLA_ENABLE
WDT->CTRLA.reg &= ~WDT_CTRLA_ENABLE;
#else
WDT->CTRL.reg &= ~WDT_CTRL_ENABLE;
#endif
}
static inline void _wait_syncbusy(void)
{
#ifdef WDT_STATUS_SYNCBUSY
while (WDT->STATUS.bit.SYNCBUSY) {}
while (WDT->STATUS.reg & WDT_STATUS_SYNCBUSY) {}
#else
while (WDT->SYNCBUSY.reg) {}
#endif
@ -98,12 +105,12 @@ void wdt_init(void)
{
_wdt_clock_setup();
#ifdef MCLK
MCLK->APBAMASK.bit.WDT_ = 1;
MCLK->APBAMASK.reg |= MCLK_APBAMASK_WDT;
#else
PM->APBAMASK.bit.WDT_ = 1;
PM->APBAMASK.reg |= PM_APBAMASK_WDT;
#endif
_set_enable(0);
_wdt_disable();
NVIC_EnableIRQ(WDT_IRQn);
}
@ -136,16 +143,16 @@ void wdt_setup_reboot(uint32_t min_time, uint32_t max_time)
}
#ifdef WDT_CTRLA_WEN
WDT->CTRLA.bit.WEN = 1;
WDT->CTRLA.reg |= WDT_CTRLA_WEN;
#else
WDT->CTRL.bit.WEN = 1;
WDT->CTRL.reg |= WDT_CTRL_WEN;
#endif
} else {
win = 0;
#ifdef WDT_CTRLA_WEN
WDT->CTRLA.bit.WEN = 0;
WDT->CTRLA.reg &= ~WDT_CTRLA_WEN;
#else
WDT->CTRL.bit.WEN = 0;
WDT->CTRL.reg &= ~WDT_CTRL_WEN;
#endif
}
@ -159,13 +166,13 @@ void wdt_setup_reboot(uint32_t min_time, uint32_t max_time)
void wdt_stop(void)
{
_set_enable(0);
_wdt_disable();
_wait_syncbusy();
}
void wdt_start(void)
{
_set_enable(1);
_wdt_enable();
_wait_syncbusy();
}
@ -203,7 +210,9 @@ void wdt_setup_reboot_with_callback(uint32_t min_time, uint32_t max_time,
}
WDT->INTENSET.reg = WDT_INTENSET_EW;
WDT->EWCTRL.bit.EWOFFSET = per - warning_offset;
uint32_t reg = WDT->EWCTRL.reg;
WDT->EWCTRL.reg = (reg & ~WDT_EWCTRL_EWOFFSET_Msk)
| WDT_EWCTRL_EWOFFSET(per - warning_offset);
} else {
WDT->INTENCLR.reg = WDT_INTENCLR_EW;
}

31
cpu/sam0_common/sam0_sdhc/sdhc.c
View File

@ -106,14 +106,19 @@ static bool sdio_test_type(sdhc_state_t *state);
static bool _card_detect(sdhc_state_t *state)
{
return state->dev->PSR.bit.CARDINS;
return state->dev->PSR.reg & SDHC_PSR_CARDINS;
}
static inline void _clock_sdcard(sdhc_state_t *state, bool on)
{
(void)state;
SDHC_DEV->CCR.bit.SDCLKEN = on;
if (on) {
SDHC_DEV->CCR.reg |= SDHC_CCR_SDCLKEN;
}
else {
SDHC_DEV->CCR.reg &= ~SDHC_CCR_SDCLKEN;
}
}
static bool _check_mask(uint32_t val, uint32_t mask)
@ -230,7 +235,7 @@ static void _init_clocks(sdhc_state_t *state)
| GCLK_PCHCTRL_GEN(SDHC_CLOCK);
GCLK->PCHCTRL[SDHC0_GCLK_ID_SLOW].reg = GCLK_PCHCTRL_CHEN
| GCLK_PCHCTRL_GEN(SDHC_CLOCK_SLOW);
MCLK->AHBMASK.bit.SDHC0_ = 1;
MCLK->AHBMASK.reg |= MCLK_AHBMASK_SDHC0;
isr_ctx_0 = state;
NVIC_EnableIRQ(SDHC0_IRQn);
}
@ -249,7 +254,7 @@ static void _init_clocks(sdhc_state_t *state)
| GCLK_PCHCTRL_GEN(SDHC_CLOCK);
GCLK->PCHCTRL[SDHC1_GCLK_ID_SLOW].reg = GCLK_PCHCTRL_CHEN
| GCLK_PCHCTRL_GEN(SDHC_CLOCK_SLOW);
MCLK->AHBMASK.bit.SDHC1_ = 1;
MCLK->AHBMASK.reg |= MCLK_AHBMASK_SDHC1;
isr_ctx_1 = state;
NVIC_EnableIRQ(SDHC1_IRQn);
}
@ -370,7 +375,7 @@ int sdhc_init(sdhc_state_t *state)
_set_hc(state);
/* if it is high speed capable, (well it is) */
if (IS_USED(SDHC_ENABLE_HS) && SDHC_DEV->CA0R.bit.HSSUP) {
if (IS_USED(SDHC_ENABLE_HS) && (SDHC_DEV->CA0R.reg & SDHC_CA0R_HSSUP)) {
if (!_test_high_speed(state)) {
res = -EIO;
goto out;
@ -441,7 +446,7 @@ bool sdhc_send_cmd(sdhc_state_t *state, uint32_t cmd, uint32_t arg)
do {
if (--timeout == 0) {
SDHC_DEV->SRR.reg = SDHC_SRR_SWRSTCMD; /* reset command */
while (SDHC_DEV->SRR.bit.SWRSTCMD) {}
while (SDHC_DEV->SRR.reg & SDHC_SRR_SWRSTCMD) {}
return false;
}
} while (!(SDHC_DEV->PSR.reg & SDHC_PSR_DATLL(1))); /* DAT[0] is busy bit */
@ -454,7 +459,7 @@ static void _set_speed(sdhc_state_t *state, uint32_t fsdhc)
{
(void)state;
if (SDHC_DEV->CCR.bit.SDCLKEN) {
if (SDHC_DEV->CCR.reg & SDHC_CCR_SDCLKEN) {
/* wait for command/data to go inactive */
while (SDHC_DEV->PSR.reg & (SDHC_PSR_CMDINHC | SDHC_PSR_CMDINHD)) {}
/* disable the clock */
@ -469,8 +474,8 @@ static void _set_speed(sdhc_state_t *state, uint32_t fsdhc)
/* write the 10 bit clock divider */
SDHC_DEV->CCR.reg = SDHC_CCR_SDCLKFSEL(div) | SDHC_CCR_USDCLKFSEL(div >> 8)
| SDHC_CCR_CLKGSEL | SDHC_CCR_INTCLKEN;
while (!SDHC_DEV->CCR.bit.INTCLKS) {} /* wait for clock to be stable */
SDHC_DEV->CCR.bit.SDCLKEN = 1; /* enable clock to card */
while (!(SDHC_DEV->CCR.reg & SDHC_CCR_INTCLKS)) {} /* wait for clock to be stable */
SDHC_DEV->CCR.reg |= SDHC_CCR_SDCLKEN; /* enable clock to card */
}
/**
@ -487,7 +492,7 @@ static void _set_hc(sdhc_state_t *state)
else {
SDHC_DEV->HC1R.reg &= ~SDHC_HC1R_HSEN;
}
if (!SDHC_DEV->HC2R.bit.PVALEN) { /* PVALEN is probably always low */
if (!(SDHC_DEV->HC2R.reg & SDHC_HC2R_PVALEN)) { /* PVALEN is probably always low */
_set_speed(state, state->clock);
}
if (state->bus_width == 4) {
@ -755,7 +760,7 @@ static bool _init_transfer(sdhc_state_t *state, uint32_t cmd, uint32_t arg, uint
do {
if (--timeout == 0) {
SDHC_DEV->SRR.reg = SDHC_SRR_SWRSTCMD; /* reset command */
while (SDHC_DEV->SRR.bit.SWRSTCMD) {}
while (SDHC_DEV->SRR.reg & SDHC_SRR_SWRSTCMD) {}
return false;
}
} while (!(SDHC_DEV->PSR.reg & SDHC_PSR_DATLL(1))); /* DAT[0] is busy bit */
@ -830,7 +835,7 @@ int sdhc_read_blocks(sdhc_state_t *state, uint32_t address, void *dst, uint16_t
int num_words = (num_blocks * SD_MMC_BLOCK_SIZE) / 4;
for (int words = 0; words < num_words; words++) {
while (!SDHC_DEV->PSR.bit.BUFRDEN) {}
while (!(SDHC_DEV->PSR.reg & SDHC_PSR_BUFRDEN)) {}
*p++ = SDHC_DEV->BDPR.reg;
}
@ -916,7 +921,7 @@ int sdhc_write_blocks(sdhc_state_t *state, uint32_t address, const void *src,
/* Write data */
int num_words = (num_blocks * SD_MMC_BLOCK_SIZE) / 4;
for (int words = 0; words < num_words; words++) {
while (!SDHC_DEV->PSR.bit.BUFWREN) {}
while (!(SDHC_DEV->PSR.reg & SDHC_PSR_BUFWREN)) {}
SDHC_DEV->BDPR.reg = *p++;
}