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cpu/esp_common: move periph/spi to cpu/esp8266
periph/spi implementation can be used for ESP8266 only from now. An implementation using the ESP-IDF spi HAL interface is required for ESP32x SoCs.
This commit is contained in:
Gunar Schorcht
parent
94e9116c04
commit
8f3df0eee6
@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2018 Gunar Schorcht
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* Copyright (C) 2022 Gunar Schorcht
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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@ -7,12 +7,12 @@
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*/
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/**
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* @ingroup cpu_esp_common
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* @ingroup cpu_esp8266
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* @ingroup drivers_periph_spi
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* @{
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*
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* @file
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* @brief Low-level SPI driver implementation for ESP SoCs
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* @brief Low-level SPI driver implementation for ESP8266
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*
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* @author Gunar Schorcht <gunar@schorcht.net>
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*
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@ -28,6 +28,7 @@
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#include "cpu.h"
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#include "mutex.h"
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#include "periph/spi.h"
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#include "macros/units.h"
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#include "esp_attr.h"
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#include "gpio_arch.h"
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@ -35,67 +36,30 @@
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#define ENABLE_DEBUG 0
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#include "debug.h"
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#ifdef MCU_ESP32
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#include "driver/periph_ctrl.h"
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#include "rom/ets_sys.h"
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#include "soc/gpio_reg.h"
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#include "soc/gpio_sig_map.h"
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#include "soc/gpio_struct.h"
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#include "soc/io_mux_reg.h"
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#include "soc/rtc.h"
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#include "soc/spi_reg.h"
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#include "soc/spi_struct.h"
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#else /* MCU_ESP32 */
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#include "esp/iomux_regs.h"
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#include "esp8266/spi_register.h"
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#include "esp8266/spi_struct.h"
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#define SPI_DOUTDIN (BIT(0))
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#endif /* MCU_ESP32 */
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#define KHZ (1000)
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#define SPI_BLOCK_SIZE 64 /* number of bytes per SPI transfer */
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/* pins of FSI are fixed */
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#define FSPI_SCK GPIO6
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#define FSPI_MISO GPIO7
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#define FSPI_MOSI GPIO8
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/** structure which describes all properties of one SPI bus */
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struct _spi_bus_t {
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spi_dev_t* regs; /* pointer to register data struct of the SPI device */
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mutex_t lock; /* mutex for each possible SPI interface */
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bool initialized; /* interface already initialized */
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bool pins_initialized; /* pins interface initialized */
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#ifdef MCU_ESP32
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uint8_t mod; /* peripheral hardware module of the SPI interface */
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uint8_t int_src; /* peripheral interrupt source used by the SPI device */
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uint8_t signal_sck; /* SCK signal from the controller */
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uint8_t signal_mosi; /* MOSI signal from the controller */
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uint8_t signal_miso; /* MISO signal to the controller */
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#endif /* MCU_ESP32 */
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};
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static struct _spi_bus_t _spi[] = {
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#ifdef SPI0_CTRL
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#ifdef SPI0_CTRL
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{
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.initialized = false,
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.pins_initialized = false,
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.lock = MUTEX_INIT
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},
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#endif
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#ifdef SPI1_CTRL
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{
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.initialized = false,
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.pins_initialized = false,
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.lock = MUTEX_INIT
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},
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#endif
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#endif
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};
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/*
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@ -107,34 +71,17 @@ static struct _spi_bus_t _spi[] = {
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* the *spi_init_cs* function or the *spi_acquire* function when the interface
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* is used for the first time.
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*/
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void IRAM_ATTR spi_init (spi_t bus)
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void IRAM_ATTR spi_init(spi_t bus)
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{
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assert(bus < SPI_NUMOF_MAX);
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assert(bus < SPI_NUMOF);
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switch (spi_config[bus].ctrl) {
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#ifdef MCU_ESP32
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case HSPI: _spi[bus].regs = &SPI2;
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_spi[bus].mod = PERIPH_HSPI_MODULE;
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_spi[bus].int_src = ETS_SPI2_INTR_SOURCE;
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_spi[bus].signal_sck = HSPICLK_OUT_IDX;
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_spi[bus].signal_mosi = HSPID_OUT_IDX;
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_spi[bus].signal_miso = HSPIQ_IN_IDX;
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break;
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case VSPI: _spi[bus].regs = &SPI3;
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_spi[bus].mod = PERIPH_VSPI_MODULE;
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_spi[bus].int_src = ETS_SPI3_INTR_SOURCE;
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_spi[bus].signal_sck = VSPICLK_OUT_IDX;
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_spi[bus].signal_mosi = VSPID_OUT_IDX;
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_spi[bus].signal_miso = VSPIQ_IN_IDX;
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break;
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#else /* MCU_ESP32 */
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case HSPI: _spi[bus].regs = &SPI1;
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break;
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#endif /* MCU_ESP32 */
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default: LOG_TAG_ERROR("spi", "invalid SPI interface controller "
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"used for SPI_DEV(%d)\n", bus);
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break;
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if (spi_config[bus].ctrl == HSPI) {
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_spi[bus].regs = &SPI1;
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}
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else {
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LOG_TAG_ERROR("spi", "invalid SPI interface controller "
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"used for SPI_DEV(%d)\n", bus);
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}
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return;
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}
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@ -164,11 +111,6 @@ static void IRAM_ATTR _spi_init_internal(spi_t bus)
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return;
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}
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#ifdef MCU_ESP32
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/* enable (power on) the according SPI module */
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periph_module_enable(_spi[bus].mod);
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#endif /* MCU_ESP32 */
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/* bring the bus into a defined state */
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_spi[bus].regs->user.val = SPI_USR_MOSI | SPI_CK_I_EDGE | SPI_DOUTDIN |
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SPI_CS_SETUP | SPI_CS_HOLD;
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@ -189,9 +131,6 @@ static void IRAM_ATTR _spi_init_internal(spi_t bus)
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/* disable fast read mode and write protection */
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_spi[bus].regs->ctrl.fastrd_mode = 0;
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#ifdef MCU_ESP32
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_spi[bus].regs->ctrl.wp = 0;
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#endif /* MCU_ESP32 */
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/* acquire and release to set default parameters */
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spi_acquire(bus, GPIO_UNDEF, SPI_MODE_0, SPI_CLK_1MHZ);
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@ -215,9 +154,9 @@ void spi_init_pins(spi_t bus)
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DEBUG("%s bus=%u\n", __func__, bus);
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if (gpio_init (spi_config[bus].sck, GPIO_OUT) ||
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gpio_init (spi_config[bus].mosi, GPIO_OUT) ||
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gpio_init (spi_config[bus].miso, GPIO_IN)) {
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if (gpio_init(spi_config[bus].sck, GPIO_OUT) ||
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gpio_init(spi_config[bus].mosi, GPIO_OUT) ||
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gpio_init(spi_config[bus].miso, GPIO_IN)) {
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LOG_TAG_ERROR("spi",
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"SPI_DEV(%d) pins could not be initialized\n", bus);
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return;
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@ -234,15 +173,6 @@ void spi_init_pins(spi_t bus)
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gpio_set_pin_usage(spi_config[bus].mosi, _SPI);
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gpio_set_pin_usage(spi_config[bus].miso, _SPI);
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#ifdef MCU_ESP32
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/* connect SCK and MOSI pins to the output signal through the GPIO matrix */
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GPIO.func_out_sel_cfg[spi_config[bus].sck].func_sel = _spi[bus].signal_sck;
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GPIO.func_out_sel_cfg[spi_config[bus].mosi].func_sel = _spi[bus].signal_mosi;
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/* connect MISO input signal to the MISO pin through the GPIO matrix */
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GPIO.func_in_sel_cfg[_spi[bus].signal_miso].sig_in_sel = 1;
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GPIO.func_in_sel_cfg[_spi[bus].signal_miso].sig_in_inv = 0;
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GPIO.func_in_sel_cfg[_spi[bus].signal_miso].func_sel = spi_config[bus].miso;
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#else /* MCU_ESP32 */
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/*
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* CS is handled as normal GPIO output. Due to the small number of GPIOs
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* we have, we do not initialize the default CS pin here. Either the app
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@ -258,7 +188,6 @@ void spi_init_pins(spi_t bus)
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IOMUX.PIN[_gpio_to_iomux[spi_config[bus].miso]] |= iomux_func;
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IOMUX.PIN[_gpio_to_iomux[spi_config[bus].mosi]] |= iomux_func;
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IOMUX.PIN[_gpio_to_iomux[spi_config[bus].sck]] |= iomux_func;
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#endif /* MCU_ESP32 */
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}
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int spi_init_cs(spi_t bus, spi_cs_t cs)
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@ -319,7 +248,7 @@ void IRAM_ATTR spi_acquire(spi_t bus, spi_cs_t cs, spi_mode_t mode, spi_clk_t cl
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/*
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* set SPI mode
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* see ESP32 Technical Reference, Table 25 and Section 7.4.2
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* see ESP32 Technical Reference, Table 27 and Section 7.4.1
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*/
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_spi[bus].regs->pin.ck_idle_edge = (mode == SPI_MODE_2 || mode == SPI_MODE_3);
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_spi[bus].regs->user.ck_out_edge = (mode == SPI_MODE_1 || mode == SPI_MODE_2);
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@ -336,23 +265,6 @@ void IRAM_ATTR spi_acquire(spi_t bus, spi_cs_t cs, spi_mode_t mode, spi_clk_t cl
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uint32_t spi_clkdiv_pre;
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uint32_t spi_clkcnt_N;
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#ifdef MCU_ESP32
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uint32_t apb_clk = rtc_clk_apb_freq_get();
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spi_clkcnt_N = 2;
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switch (clk) {
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case SPI_CLK_10MHZ: spi_clkdiv_pre = apb_clk / (10 * MHZ) / 2;
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break;
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case SPI_CLK_5MHZ: spi_clkdiv_pre = apb_clk / (5 * MHZ) / 2;
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break;
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case SPI_CLK_1MHZ: spi_clkdiv_pre = apb_clk / MHZ / 2;
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break;
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case SPI_CLK_400KHZ: spi_clkdiv_pre = apb_clk / (400 * KHZ) / 2;
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break;
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case SPI_CLK_100KHZ: /* fallthrough intentionally */
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default: spi_clkdiv_pre = apb_clk / (100 * KHZ) / 2;
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}
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assert(spi_clkdiv_pre > 0);
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#else
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switch (clk) {
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case SPI_CLK_10MHZ: spi_clkdiv_pre = 2; /* predivides 80 MHz to 40 MHz */
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spi_clkcnt_N = 4; /* 4 cycles results into 10 MHz */
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@ -372,7 +284,6 @@ void IRAM_ATTR spi_acquire(spi_t bus, spi_cs_t cs, spi_mode_t mode, spi_clk_t cl
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default: spi_clkdiv_pre = 20; /* predivides 80 MHz to 4 MHz */
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spi_clkcnt_N = 40; /* 20 cycles results into 100 kHz */
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}
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#endif
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/* register values are set to deviders-1 */
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spi_clkdiv_pre--;
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@ -381,9 +292,7 @@ void IRAM_ATTR spi_acquire(spi_t bus, spi_cs_t cs, spi_mode_t mode, spi_clk_t cl
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DEBUG("%s spi_clkdiv_prev=%u spi_clkcnt_N=%u\n",
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__func__, spi_clkdiv_pre, spi_clkcnt_N);
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#ifdef MCU_ESP8266
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IOMUX.CONF &= ~IOMUX_CONF_SPI1_CLOCK_EQU_SYS_CLOCK;
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#endif
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/* SPI clock is derived from APB clock by dividers */
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_spi[bus].regs->clock.clk_equ_sysclk = 0;
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@ -408,11 +317,7 @@ void IRAM_ATTR spi_release(spi_t bus)
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mutex_unlock(&_spi[bus].lock);
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}
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#ifdef MCU_ESP32
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static const char* _spi_names[] = { "CSPI", "FSPI", "HSPI", "VSPI" };
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#else /* MCU_ESP32 */
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static const char* _spi_names[] = { "FSPI", "HSPI" };
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#endif /* MCU_ESP32 */
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void spi_print_config(void)
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{
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@ -438,13 +343,8 @@ inline static void IRAM_ATTR _set_size(uint8_t bus, uint8_t bytes)
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{
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uint32_t bits = ((uint32_t)bytes << 3) - 1;
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#ifdef MCU_ESP32
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_spi[bus].regs->mosi_dlen.val = bits;
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_spi[bus].regs->miso_dlen.val = bits;
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#else /* MCU_ESP32 */
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_spi[bus].regs->user1.usr_mosi_bitlen = bits;
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_spi[bus].regs->user1.usr_miso_bitlen = bits;
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#endif /* MCU_ESP32 */
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}
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inline static void IRAM_ATTR _wait(uint8_t bus)
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