mirror of
https://github.com/RIOT-OS/RIOT.git
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Merge pull request #2911 from neumodisch/driver_i2c_stm32f3
boards: Implemented i2c functionality for the stm32f3discovery board
This commit is contained in:
commit
8e5541757d
@ -2,6 +2,7 @@ FEATURES_PROVIDED += cpp
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FEATURES_PROVIDED += periph_uart
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FEATURES_PROVIDED += periph_gpio
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FEATURES_PROVIDED += periph_pwm
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FEATURES_PROVIDED += periph_i2c
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FEATURES_PROVIDED += periph_spi
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FEATURES_PROVIDED += periph_cpuid
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FEATURES_MCU_GROUP = cortex_m4
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@ -197,6 +197,53 @@ extern "C" {
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#define SPI_1_MOSI_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOCEN)
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/** @} */
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/**
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* @name I2C configuration
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* @{
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*/
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#define I2C_NUMOF (2U)
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#define I2C_0_EN 1
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#define I2C_1_EN 1
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#define I2C_IRQ_PRIO 1
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#define I2C_APBCLK (36000000U)
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/* I2C 0 device configuration */
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#define I2C_0_DEV I2C1
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#define I2C_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_I2C1EN)
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#define I2C_0_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
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#define I2C_0_EVT_IRQ I2C1_EV_IRQn
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#define I2C_0_EVT_ISR isr_i2c1_ev
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#define I2C_0_ERR_IRQ I2C1_ER_IRQn
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#define I2C_0_ERR_ISR isr_i2c1_er
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/* I2C 0 pin configuration */
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#define I2C_0_SCL_PORT GPIOB
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#define I2C_0_SCL_PIN 6
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#define I2C_0_SCL_AF 4
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#define I2C_0_SCL_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOBEN)
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#define I2C_0_SDA_PORT GPIOB
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#define I2C_0_SDA_PIN 7
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#define I2C_0_SDA_AF 4
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#define I2C_0_SDA_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOBEN)
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/* I2C 1 device configuration */
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#define I2C_1_DEV I2C2
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#define I2C_1_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_I2C2EN)
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#define I2C_1_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
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#define I2C_1_EVT_IRQ I2C2_EV_IRQn
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#define I2C_1_EVT_ISR isr_i2c2_ev
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#define I2C_1_ERR_IRQ I2C2_ER_IRQn
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#define I2C_1_ERR_ISR isr_i2c2_er
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/* I2C 1 pin configuration */
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#define I2C_1_SCL_PORT GPIOF
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#define I2C_1_SCL_PIN 1
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#define I2C_1_SCL_AF 4
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#define I2C_1_SCL_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOFEN)
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#define I2C_1_SDA_PORT GPIOF
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#define I2C_1_SDA_PIN 0
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#define I2C_1_SDA_AF 4
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#define I2C_1_SDA_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOFEN)
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/** @} */
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/**
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* @brief GPIO configuration
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* @{
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@ -4264,7 +4264,7 @@ typedef struct
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#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
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#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
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#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
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#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
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#define I2C_CR1_DNF ((uint32_t)0x00000F00) /*!< Digital noise filter */
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#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
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#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
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#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
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546
cpu/stm32f3/periph/i2c.c
Normal file
546
cpu/stm32f3/periph/i2c.c
Normal file
@ -0,0 +1,546 @@
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/*
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* Copyright (C) 2015 Jan Pohlmann <jan-pohlmann@gmx.de>
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @addtogroup driver_periph
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* @{
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*
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* @file
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* @brief Low-level I2C driver implementation
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*
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* @note This implementation only implements the 7-bit addressing mode.
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*
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* @author Peter Kietzmann <peter.kietzmann@haw-hamburg.de>
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @auhtor Thomas Eichinger <thomas.eichinger@fu-berlin.de>
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* @author Jan Pohlmann <jan-pohlmann@gmx.de>
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*
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* @}
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*/
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#include <stdint.h>
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#include "cpu.h"
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#include "panic.h"
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#include "irq.h"
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#include "mutex.h"
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#include "periph_conf.h"
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#include "periph/i2c.h"
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#define ENABLE_DEBUG (0)
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#include "debug.h"
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/* guard file in case no I2C device is defined */
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#if I2C_NUMOF
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/* static function definitions */
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static void _i2c_init(I2C_TypeDef *i2c, uint32_t presc, uint32_t scll,
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uint32_t sclh, uint32_t sdadel, uint32_t scldel,
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uint32_t timing);
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static void _pin_config(GPIO_TypeDef *port_scl, GPIO_TypeDef *port_sda,
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int pin_scl, int pin_sda);
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static void _start(I2C_TypeDef *dev, uint8_t address, uint8_t length,
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uint8_t rw_flag);
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static inline void _read(I2C_TypeDef *dev, char *data, int length);
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static inline void _write(I2C_TypeDef *dev, char *data, int length);
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static inline void _stop(I2C_TypeDef *dev);
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/**
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* @brief Array holding one pre-initialized mutex for each I2C device
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*/
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static mutex_t locks[] = {
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#if I2C_0_EN
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[I2C_0] = MUTEX_INIT,
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#endif
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#if I2C_1_EN
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[I2C_1] = MUTEX_INIT,
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#endif
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#if I2C_2_EN
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[I2C_2] = MUTEX_INIT
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#endif
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#if I2C_3_EN
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[I2C_3] = MUTEX_INIT
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#endif
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};
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int i2c_init_master(i2c_t dev, i2c_speed_t speed)
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{
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I2C_TypeDef *i2c;
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GPIO_TypeDef *port_scl;
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GPIO_TypeDef *port_sda;
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int pin_scl = 0, pin_sda = 0;
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uint32_t presc, scll, sclh, sdadel, scldel, timing;
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/*
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* Speed configuration:
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* Example values can be found in the STM32F3xx Reference manual RM0316
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* Chapter 28.4.9: Table 148 Examples of timings settings for f_I2CCLK = 8MHz
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* t_SCLL: SCL low level counter
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* t_SCLH: SCL high level counter
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* t_SDADEL: Delay before sending SDA output
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* t_SCLDEL: SCL low level during setup-time
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*/
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switch (speed) {
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case I2C_SPEED_NORMAL:
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presc = 1;
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scll = 0x13; /* t_SCLL = 5.0us */
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sclh = 0xF; /* t_SCLH = 4.0us */
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sdadel = 0x2; /* t_SDADEL = 500ns */
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scldel = 0x4; /* t_SCLDEL = 1250ns */
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break;
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case I2C_SPEED_FAST:
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presc = 0;
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scll = 0x9; /* t_SCLL = 1250ns */
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sclh = 0x3; /* t_SCLH = 500ns */
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sdadel = 0x1; /* t_SDADEL = 125ns */
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scldel = 0x3; /* t_SCLDEL = 500ns */
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break;
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case I2C_SPEED_FAST_PLUS:
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presc = 0;
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scll = 0x6; /* t_SCLL = 875ns */
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sclh = 0x3; /* t_SCLH = 500ns */
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sdadel = 0x0; /* t_SDADEL = 0ns */
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scldel = 0x1; /* t_SCLDEL = 250ns */
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break;
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default:
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return -2;
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}
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/* prepare the timing register value */
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timing = ((presc << 28) | (scldel << 20) | (sdadel << 16) | (sclh << 8) | scll);
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/* read static device configuration */
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switch (dev) {
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#if I2C_0_EN
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case I2C_0:
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i2c = I2C_0_DEV;
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port_scl = I2C_0_SCL_PORT;
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pin_scl = I2C_0_SCL_PIN;
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port_sda = I2C_0_SDA_PORT;
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pin_sda = I2C_0_SDA_PIN;
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I2C_0_CLKEN();
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I2C_0_SCL_CLKEN();
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I2C_0_SDA_CLKEN();
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NVIC_SetPriority(I2C_0_ERR_IRQ, I2C_IRQ_PRIO);
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NVIC_EnableIRQ(I2C_0_ERR_IRQ);
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break;
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#endif
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#if I2C_1_EN
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case I2C_1:
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i2c = I2C_1_DEV;
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port_scl = I2C_1_SCL_PORT;
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pin_scl = I2C_1_SCL_PIN;
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port_sda = I2C_1_SDA_PORT;
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pin_sda = I2C_1_SDA_PIN;
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I2C_1_CLKEN();
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I2C_1_SCL_CLKEN();
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I2C_1_SDA_CLKEN();
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NVIC_SetPriority(I2C_1_ERR_IRQ, I2C_IRQ_PRIO);
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NVIC_EnableIRQ(I2C_1_ERR_IRQ);
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break;
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#endif
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default:
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return -1;
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}
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/* configure pins */
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_pin_config(port_scl, port_sda, pin_scl, pin_sda);
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/* configure device */
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_i2c_init(i2c, presc, scll, sclh, sdadel, scldel, timing);
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return 0;
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}
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static void _i2c_init(I2C_TypeDef *i2c, uint32_t presc, uint32_t scll,
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uint32_t sclh, uint32_t sdadel, uint32_t scldel,
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uint32_t timing)
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{
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/* disable device */
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i2c->CR1 &= ~(I2C_CR1_PE);
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/* configure analog noise filter */
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i2c->CR1 |= I2C_CR1_ANFOFF;
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/* configure digital noise filter */
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i2c->CR1 |= I2C_CR1_DNF;
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/* set timing registers */
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i2c->TIMINGR = timing;
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/* configure clock stretching */
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i2c->CR1 &= ~(I2C_CR1_NOSTRETCH);
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/* enable device */
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i2c->CR1 |= I2C_CR1_PE;
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}
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static void _pin_config(GPIO_TypeDef *port_scl, GPIO_TypeDef *port_sda,
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int pin_scl, int pin_sda)
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{
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/* Set GPIOs to AF mode */
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port_scl->MODER &= ~(3 << (2 * pin_scl));
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port_scl->MODER |= (2 << (2 * pin_scl));
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port_sda->MODER &= ~(3 << (2 * pin_sda));
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port_sda->MODER |= (2 << (2 * pin_sda));
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/* Set speed high*/
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port_scl->OSPEEDR |= (3 << (2 * pin_scl));
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port_sda->OSPEEDR |= (3 << (2 * pin_sda));
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/* Set to push-pull configuration open drain*/
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port_scl->OTYPER |= (1 << pin_scl);
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port_sda->OTYPER |= (1 << pin_sda);
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/* Enable pull-up resistors */
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port_scl->PUPDR &= ~(3 << (2 * pin_scl));
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port_scl->PUPDR |= (1 << (2 * pin_scl));
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port_sda->PUPDR &= ~(3 << (2 * pin_sda));
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port_sda->PUPDR |= (1 << (2 * pin_sda));
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/* Configure GPIOs to for the I2C alternate function */
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if (pin_scl < 8) {
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port_scl->AFR[0] &= ~(0xf << (4 * pin_scl));
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port_scl->AFR[0] |= (I2C_0_SCL_AF << (4 * pin_scl));
|
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}
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else {
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port_scl->AFR[1] &= ~(0xf << (4 * (pin_scl - 8)));
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port_scl->AFR[1] |= (I2C_0_SCL_AF << (4 * (pin_scl - 8)));
|
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}
|
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|
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if (pin_sda < 8) {
|
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port_sda->AFR[0] &= ~(0xf << (4 * pin_sda));
|
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port_sda->AFR[0] |= (I2C_0_SDA_AF << (4 * pin_sda));
|
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}
|
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else {
|
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port_sda->AFR[1] &= ~(0xf << (4 * (pin_sda - 8)));
|
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port_sda->AFR[1] |= (I2C_0_SDA_AF << (4 * (pin_sda - 8)));
|
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}
|
||||
}
|
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|
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int i2c_init_slave(i2c_t dev, uint8_t address)
|
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{
|
||||
/* TODO: implement slave mode */
|
||||
return -1;
|
||||
}
|
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|
||||
int i2c_acquire(i2c_t dev)
|
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{
|
||||
if (dev >= I2C_NUMOF) {
|
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return -1;
|
||||
}
|
||||
mutex_lock(&locks[dev]);
|
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return 0;
|
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}
|
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|
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int i2c_release(i2c_t dev)
|
||||
{
|
||||
if (dev >= I2C_NUMOF) {
|
||||
return -1;
|
||||
}
|
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mutex_unlock(&locks[dev]);
|
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return 0;
|
||||
}
|
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|
||||
int i2c_read_byte(i2c_t dev, uint8_t address, char *data)
|
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{
|
||||
return i2c_read_bytes(dev, address, data, 1);
|
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}
|
||||
|
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int i2c_read_bytes(i2c_t dev, uint8_t address, char *data, int length)
|
||||
{
|
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I2C_TypeDef *i2c;
|
||||
|
||||
switch (dev) {
|
||||
#if I2C_0_EN
|
||||
case I2C_0:
|
||||
i2c = I2C_0_DEV;
|
||||
break;
|
||||
#endif
|
||||
#if I2C_1_EN
|
||||
case I2C_1:
|
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i2c = I2C_1_DEV;
|
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break;
|
||||
#endif
|
||||
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* start reception and send slave address */
|
||||
_start(i2c, address, length, I2C_FLAG_READ);
|
||||
|
||||
/* read the data bytes */
|
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_read(i2c, data, length);
|
||||
|
||||
/* end transmission */
|
||||
_stop(i2c);
|
||||
|
||||
return length;
|
||||
}
|
||||
|
||||
int i2c_read_reg(i2c_t dev, uint8_t address, uint8_t reg, char *data)
|
||||
{
|
||||
return i2c_read_regs(dev, address, reg, data, 1);
|
||||
}
|
||||
|
||||
int i2c_read_regs(i2c_t dev, uint8_t address, uint8_t reg, char *data, int length)
|
||||
{
|
||||
I2C_TypeDef *i2c;
|
||||
|
||||
switch (dev) {
|
||||
#if I2C_0_EN
|
||||
case I2C_0:
|
||||
i2c = I2C_0_DEV;
|
||||
break;
|
||||
#endif
|
||||
#if I2C_1_EN
|
||||
case I2C_1:
|
||||
i2c = I2C_1_DEV;
|
||||
break;
|
||||
#endif
|
||||
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* send start sequence and slave address */
|
||||
_start(i2c, address, length, I2C_FLAG_WRITE);
|
||||
|
||||
/* wait for ack */
|
||||
DEBUG("Waiting for ACK\n");
|
||||
while (!(i2c->ISR & I2C_ISR_TXIS));
|
||||
|
||||
/* send register number */
|
||||
DEBUG("ACK received, write reg into DR\n");
|
||||
i2c->TXDR = reg;
|
||||
|
||||
/* send repeated start sequence, read registers and end transmission */
|
||||
DEBUG("ACK received, send repeated start sequence\n");
|
||||
return i2c_read_bytes(dev, address, data, length);
|
||||
}
|
||||
|
||||
int i2c_write_byte(i2c_t dev, uint8_t address, char data)
|
||||
{
|
||||
return i2c_write_bytes(dev, address, &data, 1);
|
||||
}
|
||||
|
||||
int i2c_write_bytes(i2c_t dev, uint8_t address, char *data, int length)
|
||||
{
|
||||
I2C_TypeDef *i2c;
|
||||
|
||||
switch (dev) {
|
||||
#if I2C_0_EN
|
||||
case I2C_0:
|
||||
i2c = I2C_0_DEV;
|
||||
break;
|
||||
#endif
|
||||
#if I2C_1_EN
|
||||
case I2C_1:
|
||||
i2c = I2C_1_DEV;
|
||||
break;
|
||||
#endif
|
||||
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* start transmission and send slave address */
|
||||
_start(i2c, address, length, I2C_FLAG_WRITE);
|
||||
|
||||
/* send out data bytes */
|
||||
_write(i2c, data, length);
|
||||
|
||||
/* end transmission */
|
||||
_stop(i2c);
|
||||
|
||||
return length;
|
||||
}
|
||||
|
||||
int i2c_write_reg(i2c_t dev, uint8_t address, uint8_t reg, char data)
|
||||
{
|
||||
return i2c_write_regs(dev, address, reg, &data, 1);
|
||||
}
|
||||
|
||||
int i2c_write_regs(i2c_t dev, uint8_t address, uint8_t reg, char *data, int length)
|
||||
{
|
||||
I2C_TypeDef *i2c;
|
||||
|
||||
switch (dev) {
|
||||
#if I2C_0_EN
|
||||
case I2C_0:
|
||||
i2c = I2C_0_DEV;
|
||||
break;
|
||||
#endif
|
||||
#if I2C_1_EN
|
||||
case I2C_1:
|
||||
i2c = I2C_1_DEV;
|
||||
break;
|
||||
#endif
|
||||
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* start transmission and send slave address */
|
||||
/* increase length because our data is register+data */
|
||||
_start(i2c, address, length+1, I2C_FLAG_WRITE);
|
||||
|
||||
/* wait for ack */
|
||||
DEBUG("Waiting for ACK\n");
|
||||
while (!(i2c->ISR & I2C_ISR_TXIS));
|
||||
|
||||
/* send register number */
|
||||
DEBUG("ACK received, write reg into DR\n");
|
||||
i2c->TXDR = reg;
|
||||
|
||||
/* write out data bytes */
|
||||
_write(i2c, data, length);
|
||||
|
||||
/* end transmission */
|
||||
_stop(i2c);
|
||||
|
||||
return length;
|
||||
}
|
||||
|
||||
void i2c_poweron(i2c_t dev)
|
||||
{
|
||||
switch (dev) {
|
||||
#if I2C_0_EN
|
||||
case I2C_0:
|
||||
I2C_0_CLKEN();
|
||||
break;
|
||||
#endif
|
||||
#if I2C_1_EN
|
||||
case I2C_1:
|
||||
I2C_1_CLKEN();
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
void i2c_poweroff(i2c_t dev)
|
||||
{
|
||||
switch (dev) {
|
||||
#if I2C_0_EN
|
||||
case I2C_0:
|
||||
while (I2C_0_DEV->ISR & I2C_ISR_BUSY);
|
||||
|
||||
I2C_0_CLKDIS();
|
||||
break;
|
||||
#endif
|
||||
#if I2C_1_EN
|
||||
case I2C_1:
|
||||
while (I2C_1_DEV->ISR & I2C_ISR_BUSY);
|
||||
|
||||
I2C_0_CLKDIS();
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
static void _start(I2C_TypeDef *dev, uint8_t address, uint8_t length, uint8_t rw_flag)
|
||||
{
|
||||
/* set address mode to 7-bit */
|
||||
dev->CR2 &= ~(I2C_CR2_ADD10);
|
||||
|
||||
/* set slave address */
|
||||
dev->CR2 &= ~(I2C_CR2_SADD);
|
||||
dev->CR2 |= (address << 1);
|
||||
|
||||
/* set transfer direction */
|
||||
dev->CR2 &= ~(I2C_CR2_RD_WRN);
|
||||
dev->CR2 |= (rw_flag << 10);
|
||||
|
||||
/* set number of bytes */
|
||||
dev->CR2 &= ~(I2C_CR2_NBYTES);
|
||||
dev->CR2 |= (length << 16);
|
||||
|
||||
/* configure autoend configuration */
|
||||
dev->CR2 &= ~(I2C_CR2_AUTOEND);
|
||||
|
||||
/* generate start condition */
|
||||
DEBUG("Generate start condition\n");
|
||||
dev->CR2 |= I2C_CR2_START;
|
||||
}
|
||||
|
||||
static inline void _read(I2C_TypeDef *dev, char *data, int length)
|
||||
{
|
||||
for (int i = 0; i < length; i++) {
|
||||
/* wait for transfer to finish */
|
||||
DEBUG("Waiting for DR to be full\n");
|
||||
while (!(dev->ISR & I2C_ISR_RXNE));
|
||||
DEBUG("DR is now full\n");
|
||||
|
||||
/* read data from data register */
|
||||
data[i] = (uint8_t)dev->RXDR;
|
||||
DEBUG("Read byte %i from DR\n", i);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void _write(I2C_TypeDef *dev, char *data, int length)
|
||||
{
|
||||
for (int i = 0; i < length; i++) {
|
||||
/* wait for ack */
|
||||
DEBUG("Waiting for ACK\n");
|
||||
while (!(dev->ISR & I2C_ISR_TXIS));
|
||||
|
||||
/* write data to data register */
|
||||
DEBUG("Write byte %i to DR\n", i);
|
||||
dev->TXDR = (uint8_t)data[i];
|
||||
DEBUG("Sending data\n");
|
||||
}
|
||||
}
|
||||
|
||||
static inline void _stop(I2C_TypeDef *dev)
|
||||
{
|
||||
/* make sure transfer is complete */
|
||||
DEBUG("Wait for transfer to be complete\n");
|
||||
while (!(dev->ISR & I2C_ISR_TC));
|
||||
|
||||
/* send STOP condition */
|
||||
DEBUG("Generate stop condition\n");
|
||||
dev->CR2 |= I2C_CR2_STOP;
|
||||
}
|
||||
|
||||
#if I2C_0_EN
|
||||
void I2C_0_ERR_ISR(void)
|
||||
{
|
||||
unsigned state = I2C_0_DEV->ISR;
|
||||
DEBUG("\n\n### I2C ERROR OCCURED ###\n");
|
||||
DEBUG("status: %08x\n", state);
|
||||
if (state & I2C_ISR_OVR) {
|
||||
DEBUG("OVR\n");
|
||||
}
|
||||
if (state & I2C_ISR_NACKF) {
|
||||
DEBUG("AF\n");
|
||||
}
|
||||
if (state & I2C_ISR_ARLO) {
|
||||
DEBUG("ARLO\n");
|
||||
}
|
||||
if (state & I2C_ISR_BERR) {
|
||||
DEBUG("BERR\n");
|
||||
}
|
||||
if (state & I2C_ISR_PECERR) {
|
||||
DEBUG("PECERR\n");
|
||||
}
|
||||
if (state & I2C_ISR_TIMEOUT) {
|
||||
DEBUG("TIMEOUT\n");
|
||||
}
|
||||
if (state & I2C_ISR_ALERT) {
|
||||
DEBUG("SMBALERT\n");
|
||||
}
|
||||
core_panic(0x0,"I2C FAULT");
|
||||
}
|
||||
#endif /* I2C_0_EN */
|
||||
|
||||
#endif /* I2C_NUMOF */
|
Loading…
Reference in New Issue
Block a user