From a322200582c2dc1226952c6b09a378bd773780da Mon Sep 17 00:00:00 2001 From: DipSwitch Date: Mon, 28 Dec 2015 00:07:11 +0100 Subject: [PATCH] cpu: remove superfluous SystemCoreClockUpdate --- boards/mbed_lpc1768/system.c | 56 --------- boards/mulle/board.c | 3 - boards/mulle/include/periph_conf.h | 44 +++---- cpu/k60/cpu.c | 181 ----------------------------- cpu/k60/include/system_MK60D10.h | 80 ------------- cpu/k60/include/vendor/MK60D10.h | 1 - cpu/k60/include/vendor/MK60DZ10.h | 1 - 7 files changed, 23 insertions(+), 343 deletions(-) delete mode 100644 cpu/k60/include/system_MK60D10.h diff --git a/boards/mbed_lpc1768/system.c b/boards/mbed_lpc1768/system.c index 38363cb68d..dcfdf3d139 100644 --- a/boards/mbed_lpc1768/system.c +++ b/boards/mbed_lpc1768/system.c @@ -406,62 +406,6 @@ #endif #endif -/* - * Clock Variable definitions - */ -uint32_t system_clock = CORE_CLK;/*!< System Clock Frequency (Core Clock)*/ - - -/* - * Clock functions - */ -void SystemCoreClockUpdate(void) /* Get Core Clock Frequency */ -{ - /* Determine clock frequency according to clock register values */ - if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */ - switch (LPC_SC->CLKSRCSEL & 0x03) { - case 0: /* Int. RC oscillator => PLL0 */ - case 3: /* Reserved, default to Int. RC */ - system_clock = (IRC_OSC * - ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / - (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / - ((LPC_SC->CCLKCFG & 0xFF) + 1)); - break; - - case 1: /* Main oscillator => PLL0 */ - system_clock = (OSC_CLK * - ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / - (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / - ((LPC_SC->CCLKCFG & 0xFF) + 1)); - break; - - case 2: /* RTC oscillator => PLL0 */ - system_clock = (RTC_CLK * - ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / - (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / - ((LPC_SC->CCLKCFG & 0xFF) + 1)); - break; - } - } - else { - switch (LPC_SC->CLKSRCSEL & 0x03) { - case 0: /* Int. RC oscillator => PLL0 */ - case 3: /* Reserved, default to Int. RC */ - system_clock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF) + 1); - break; - - case 1: /* Main oscillator => PLL0 */ - system_clock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF) + 1); - break; - - case 2: /* RTC oscillator => PLL0 */ - system_clock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF) + 1); - break; - } - } - -} - /** * Initialize the system * diff --git a/boards/mulle/board.c b/boards/mulle/board.c index e1b1e27d32..3800b03d02 100644 --- a/boards/mulle/board.c +++ b/boards/mulle/board.c @@ -140,9 +140,6 @@ void board_init(void) __asm__ volatile("nop\n"); } - /* Update SystemCoreClock global var */ - SystemCoreClockUpdate(); - /* initialize the CPU */ cpu_init(); diff --git a/boards/mulle/include/periph_conf.h b/boards/mulle/include/periph_conf.h index 444f6b886b..12035939a6 100644 --- a/boards/mulle/include/periph_conf.h +++ b/boards/mulle/include/periph_conf.h @@ -43,7 +43,6 @@ extern "C" #define KINETIS_MCG_ERC_RANGE 0 #define KINETIS_MCG_ERC_FREQ (32768U) -/* Base clocks, used by SystemCoreClockUpdate */ /** Value of the external crystal or oscillator clock frequency in Hz */ #define CPU_XTAL_CLK_HZ 8000000u /** Value of the external 32k crystal or oscillator clock frequency in Hz */ @@ -56,7 +55,8 @@ extern "C" #define DEFAULT_SYSTEM_CLOCK (CPU_XTAL32k_CLK_HZ * 2929u) /* bus clock for the peripherals */ -#define CLOCK_BUSCLOCK (DEFAULT_SYSTEM_CLOCK / 2) +#define CLOCK_CORECLOCK (DEFAULT_SYSTEM_CLOCK) +#define CLOCK_BUSCLOCK (CLOCK_CORECLOCK / 2) /** @} */ /** @@ -108,7 +108,7 @@ extern "C" #define UART_0_DEV UART1 #define UART_0_CLKEN() (BITBAND_REG32(SIM->SCGC4, SIM_SCGC4_UART1_SHIFT) = 1) #define UART_0_CLKDIS() (BITBAND_REG32(SIM->SCGC4, SIM_SCGC4_UART1_SHIFT) = 0) -#define UART_0_CLK (SystemSysClock) +#define UART_0_CLK (CLOCK_CORECLOCK) #define UART_0_IRQ_CHAN UART1_RX_TX_IRQn #define UART_0_ISR isr_uart1_status /* UART 0 pin configuration */ @@ -126,7 +126,7 @@ extern "C" #define UART_1_DEV UART0 #define UART_1_CLKEN() (BITBAND_REG32(SIM->SCGC4, SIM_SCGC4_UART0_SHIFT) = 1) #define UART_1_CLKDIS() (BITBAND_REG32(SIM->SCGC4, SIM_SCGC4_UART0_SHIFT) = 0) -#define UART_1_CLK (SystemSysClock) +#define UART_1_CLK (CLOCK_CORECLOCK) #define UART_1_IRQ_CHAN UART0_RX_TX_IRQn #define UART_1_ISR isr_uart0_status /* UART 1 pin configuration */ @@ -293,22 +293,6 @@ static const spi_conf_t spi_config[] = { #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0])) /** @} */ -/** - * @name I2C baud rate configuration - * @{ - */ -/* Low (10 kHz): MUL = 4, SCL divider = 2560, total: 10240 */ -#define KINETIS_I2C_F_ICR_LOW (0x3D) -#define KINETIS_I2C_F_MULT_LOW (2) -/* Normal (100 kHz): MUL = 2, SCL divider = 240, total: 480 */ -#define KINETIS_I2C_F_ICR_NORMAL (0x1F) -#define KINETIS_I2C_F_MULT_NORMAL (1) -/* Fast (400 kHz): MUL = 1, SCL divider = 128, total: 128 */ -#define KINETIS_I2C_F_ICR_FAST (0x17) -#define KINETIS_I2C_F_MULT_FAST (0) -/* Fast plus (1000 kHz): MUL = 1, SCL divider = 48, total: 48 */ -#define KINETIS_I2C_F_ICR_FAST_PLUS (0x10) -#define KINETIS_I2C_F_MULT_FAST_PLUS (0) /** @} */ /** @@ -316,7 +300,7 @@ static const spi_conf_t spi_config[] = { * @{ */ #define I2C_NUMOF (1U) -#define I2C_CLK SystemBusClock +#define I2C_CLK CLOCK_BUSCLOCK #define I2C_0_EN 1 #define I2C_1_EN 0 #define I2C_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO @@ -336,6 +320,24 @@ static const spi_conf_t spi_config[] = { #define I2C_0_PORT_CFG (PORT_PCR_MUX(I2C_0_PIN_AF) | PORT_PCR_ODE_MASK) /** @} */ +/** + * @name I2C baud rate configuration + * @{ + */ +/* Low (10 kHz): MUL = 4, SCL divider = 2560, total: 10240 */ +#define KINETIS_I2C_F_ICR_LOW (0x3D) +#define KINETIS_I2C_F_MULT_LOW (2) +/* Normal (100 kHz): MUL = 2, SCL divider = 240, total: 480 */ +#define KINETIS_I2C_F_ICR_NORMAL (0x1F) +#define KINETIS_I2C_F_MULT_NORMAL (1) +/* Fast (400 kHz): MUL = 1, SCL divider = 128, total: 128 */ +#define KINETIS_I2C_F_ICR_FAST (0x17) +#define KINETIS_I2C_F_MULT_FAST (0) +/* Fast plus (1000 kHz): MUL = 1, SCL divider = 48, total: 48 */ +#define KINETIS_I2C_F_ICR_FAST_PLUS (0x10) +#define KINETIS_I2C_F_MULT_FAST_PLUS (0) +/** @} */ + /** * @name GPIO configuration * @{ diff --git a/cpu/k60/cpu.c b/cpu/k60/cpu.c index 327100e9b1..3768f8374d 100644 --- a/cpu/k60/cpu.c +++ b/cpu/k60/cpu.c @@ -21,19 +21,6 @@ * @author Joakim Nohlgård */ -/** @brief Current core clock frequency */ -uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; -/** @brief Current system clock frequency */ -uint32_t SystemSysClock = DEFAULT_SYSTEM_CLOCK; -/** @brief Current bus clock frequency */ -uint32_t SystemBusClock = DEFAULT_SYSTEM_CLOCK; -/** @brief Current FlexBus clock frequency */ -uint32_t SystemFlexBusClock = DEFAULT_SYSTEM_CLOCK; -/** @brief Current flash clock frequency */ -uint32_t SystemFlashClock = DEFAULT_SYSTEM_CLOCK; -/** @brief Number of full PIT ticks in one microsecond. */ -uint32_t PIT_ticks_per_usec = (DEFAULT_SYSTEM_CLOCK / 1000000ul); - /** * @brief Check the running CPU identification to find if we are running on the * wrong hardware. @@ -73,172 +60,4 @@ static void check_running_cpu_revision(void) } } -void SystemCoreClockUpdate(void) -{ - /* Variable to store output clock frequency of the MCG module */ - uint32_t MCGOUT_clock; - - if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) { - /* Output of FLL or PLL is selected */ - if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { - /* FLL is selected */ - if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) { - /* External reference clock is selected */ -#if K60_CPU_REV == 1 - /* rev.1 silicon */ - if ((SIM->SOPT2 & SIM_SOPT2_MCGCLKSEL_MASK) == 0x0u) { - /* System oscillator drives MCG clock */ - MCGOUT_clock = CPU_XTAL_CLK_HZ; - } - else { - /* RTC 32 kHz oscillator drives MCG clock */ - MCGOUT_clock = CPU_XTAL32k_CLK_HZ; - } - -#else /* K60_CPU_REV */ - - /* rev.2 silicon */ - if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) { - /* System oscillator drives MCG clock */ - MCGOUT_clock = CPU_XTAL_CLK_HZ; - } - else { - /* RTC 32 kHz oscillator drives MCG clock */ - MCGOUT_clock = CPU_XTAL32k_CLK_HZ; - } - -#endif /* K60_CPU_REV */ - uint8_t divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); - /* Calculate the divided FLL reference clock */ - MCGOUT_clock /= divider; - - if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) { - /* If high range is enabled, additional 32 divider is active */ - MCGOUT_clock /= 32u; - } - } - else { - /* The slow internal reference clock is selected */ - MCGOUT_clock = CPU_INT_SLOW_CLK_HZ; - } - - /* Select correct multiplier to calculate the MCG output clock */ - switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { - case (0x0u): - MCGOUT_clock *= 640u; - break; - - case (MCG_C4_DRST_DRS(0b01)): /* 0x20u */ - MCGOUT_clock *= 1280u; - break; - - case (MCG_C4_DRST_DRS(0b10)): /* 0x40u */ - MCGOUT_clock *= 1920u; - break; - - case (MCG_C4_DRST_DRS(0b11)): /* 0x60u */ - MCGOUT_clock *= 2560u; - break; - - case (MCG_C4_DMX32_MASK): /* 0x80u */ - MCGOUT_clock *= 732u; - break; - - case (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0b01)): /* 0xA0u */ - MCGOUT_clock *= 1464u; - break; - - case (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0b10)): /* 0xC0u */ - MCGOUT_clock *= 2197u; - break; - - case (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0b11)): /* 0xE0u */ - MCGOUT_clock *= 2929u; - break; - - default: - break; - } - } - else { - /* PLL is selected */ - /* Calculate the PLL reference clock */ - uint8_t divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK)); - MCGOUT_clock = (uint32_t)(CPU_XTAL_CLK_HZ / divider); - /* Calculate the MCG output clock */ - divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u); - MCGOUT_clock *= divider; - } - } - else if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0b01)) { /* 0x40u */ - /* Internal reference clock is selected */ - if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) { - /* Slow internal reference clock selected */ - MCGOUT_clock = CPU_INT_SLOW_CLK_HZ; - } - else { - /* Fast internal reference clock selected */ -#if K60_CPU_REV == 1 - /* rev.1 silicon */ - MCGOUT_clock = CPU_INT_FAST_CLK_HZ; -#else /* K60_CPU_REV */ - /* rev.2 silicon */ - MCGOUT_clock = CPU_INT_FAST_CLK_HZ / - (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); -#endif /* K60_CPU_REV */ - } - } - else if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0b10)) { /* 0x80u */ - /* External reference clock is selected */ -#if K60_CPU_REV == 1 - /* rev.1 silicon */ - if ((SIM->SOPT2 & SIM_SOPT2_MCGCLKSEL_MASK) == 0x0u) { - /* System oscillator drives MCG clock */ - MCGOUT_clock = CPU_XTAL_CLK_HZ; - } - else { - /* RTC 32 kHz oscillator drives MCG clock */ - MCGOUT_clock = CPU_XTAL32k_CLK_HZ; - } - -#else /* K60_CPU_REV */ - - /* rev.2 silicon */ - if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) { - /* System oscillator drives MCG clock */ - MCGOUT_clock = CPU_XTAL_CLK_HZ; - } - else { - /* RTC 32 kHz oscillator drives MCG clock */ - MCGOUT_clock = CPU_XTAL32k_CLK_HZ; - } - -#endif /* K60_CPU_REV */ - } - else { - /* Reserved value */ - return; - } - - /* Core clock and system clock use the same divider setting */ - SystemCoreClock = SystemSysClock = (MCGOUT_clock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) - >> SIM_CLKDIV1_OUTDIV1_SHIFT))); - SystemBusClock = (MCGOUT_clock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV2_MASK) >> - SIM_CLKDIV1_OUTDIV2_SHIFT))); - SystemFlexBusClock = (MCGOUT_clock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV3_MASK) >> - SIM_CLKDIV1_OUTDIV3_SHIFT))); - SystemFlashClock = (MCGOUT_clock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> - SIM_CLKDIV1_OUTDIV4_SHIFT))); - - /* Module helper variables */ - if (SystemBusClock >= 1000000) { - /* PIT module clock_delay_usec scale factor */ - PIT_ticks_per_usec = (SystemBusClock + 500000) / 1000000; /* Rounded to nearest integer */ - } - else { - /* less than 1 MHz clock frequency on the PIT module, round up. */ - PIT_ticks_per_usec = 1; - } -} - /** @} */ diff --git a/cpu/k60/include/system_MK60D10.h b/cpu/k60/include/system_MK60D10.h deleted file mode 100644 index e5df6b3f76..0000000000 --- a/cpu/k60/include/system_MK60D10.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (C) 2015 Eistec AB - * - * This file is subject to the terms and conditions of the GNU Lesser General - * Public License v2.1. See the file LICENSE in the top level directory for more - * details. - */ - -#ifndef SYSTEM_MK60D10_H -#define SYSTEM_MK60D10_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/** - * @ingroup cpu_k60 - * @{ - * - * @file - * @brief Device specific configuration file for MK60D10 (header file) - */ - - -/** - * \brief Current core clock frequency - * - * MCGOUTCLK divided by OUTDIV1 clocks the ARM Cortex-M4 core. - */ -extern uint32_t SystemCoreClock; - -/** - * \brief Current system clock frequency - * - * MCGOUTCLK divided by OUTDIV1 clocks the crossbar switch and bus masters - * directly connected to the crossbar. In addition, this clock is used for UART0 - * and UART1. - */ -extern uint32_t SystemSysClock; - -/** - * \brief Current bus clock frequency - * - * MCGOUTCLK divided by OUTDIV2 clocks the bus slaves and peripheral (excluding - * memories). - */ -extern uint32_t SystemBusClock; - -/** - * \brief Current FlexBus clock frequency - * - * MCGOUTCLK divided by OUTDIV3 clocks the external FlexBus interface. - */ -extern uint32_t SystemFlexBusClock; - -/** - * \brief Current flash clock frequency - * - * MCGOUTCLK divided by OUTDIV4 clocks the flash memory. - */ -extern uint32_t SystemFlashClock; - -/** - * \brief Updates all of the SystemCoreClock variables. - * - * It must be called whenever the core clock is changed during program - * execution. SystemCoreClockUpdate() evaluates the clock register settings and - * calculates the current core clock. - */ -void SystemCoreClockUpdate(void); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* #if !defined(SYSTEM_MK60D10_H) */ diff --git a/cpu/k60/include/vendor/MK60D10.h b/cpu/k60/include/vendor/MK60D10.h index 1f4267a0c2..fa77a49f28 100644 --- a/cpu/k60/include/vendor/MK60D10.h +++ b/cpu/k60/include/vendor/MK60D10.h @@ -302,7 +302,6 @@ typedef enum IRQn { #define __FPU_PRESENT 0 /**< Defines if an FPU is present or not */ #include "core_cm4.h" /* Core Peripheral Access Layer */ -#include "system_MK60D10.h" /* Device specific configuration file */ /*! * @} diff --git a/cpu/k60/include/vendor/MK60DZ10.h b/cpu/k60/include/vendor/MK60DZ10.h index 1bc57fc016..4188c2f279 100644 --- a/cpu/k60/include/vendor/MK60DZ10.h +++ b/cpu/k60/include/vendor/MK60DZ10.h @@ -257,7 +257,6 @@ typedef enum IRQn { #define __FPU_PRESENT 0 /**< FPU present or not */ #include "core_cm4.h" /* Core Peripheral Access Layer */ -#include "system_MK60DZ10.h" /* Device specific configuration file */ /** * @}