mirror of
https://github.com/RIOT-OS/RIOT.git
synced 2024-12-29 04:50:03 +01:00
Merge pull request #1512 from cgundogan/remove_tabs_boards
converting tabs to spaces in boards (#1439)
This commit is contained in:
Oleg Hahm
commit
8a337f3566
@ -61,7 +61,7 @@ void init_clks1(void)
|
||||
CLKSRCSEL = 0x0001;
|
||||
|
||||
// Setting Multiplier and Divider values
|
||||
PLLCFG = 0x0008; // M=9 N=1 Fcco = 288 MHz
|
||||
PLLCFG = 0x0008; // M=9 N=1 Fcco = 288 MHz
|
||||
pllfeed();
|
||||
|
||||
// Enabling the PLL */
|
||||
@ -72,7 +72,7 @@ void init_clks1(void)
|
||||
CCLKCFG = CL_CPU_DIV - 1; // Fcpu = 72 MHz
|
||||
|
||||
#if USE_USB
|
||||
USBCLKCFG = USBCLKDivValue; /* usbclk = 288 MHz/6 = 48 MHz */
|
||||
USBCLKCFG = USBCLKDivValue; /* usbclk = 288 MHz/6 = 48 MHz */
|
||||
#endif
|
||||
}
|
||||
|
||||
@ -88,41 +88,41 @@ void bl_init_ports(void)
|
||||
//PTTU:
|
||||
|
||||
/*Turn Board on*/
|
||||
// PINMODE0 |= BIT1;
|
||||
// FIO0DIR |= BIT27;
|
||||
// FIO0CLR = BIT27;
|
||||
// 0.27
|
||||
// PINMODE0 |= BIT1;
|
||||
// FIO0DIR |= BIT27;
|
||||
// FIO0CLR = BIT27;
|
||||
// 0.27
|
||||
|
||||
/* 5V*/
|
||||
// FIO1DIR |= BIT28; // Synch
|
||||
// FIO1SET = BIT28; // No Powersave
|
||||
// 1.28
|
||||
// FIO1DIR |= BIT28; // Synch
|
||||
// FIO1SET = BIT28; // No Powersave
|
||||
// 1.28
|
||||
|
||||
// FIO1DIR |= BIT27; // 5V off
|
||||
// FIO1CLR = BIT27;
|
||||
// 1.27
|
||||
// FIO1DIR |= BIT27; // 5V off
|
||||
// FIO1CLR = BIT27;
|
||||
// 1.27
|
||||
|
||||
/* Disable Resistors on Buttons */
|
||||
// PINMODE4 |= BIT9 + BIT11;
|
||||
// PINMODE4 |= BIT9 + BIT11;
|
||||
//
|
||||
|
||||
/* Disable Resistors on LED - and Ports to output*/
|
||||
PINMODE7 |= BIT19 + BIT21; //3.25 + 3.26
|
||||
PINMODE2 |= BIT1; //1.0
|
||||
PINMODE2 |= BIT1; //1.0
|
||||
FIO1DIR |= BIT0;
|
||||
FIO3DIR |= BIT25 + BIT26;
|
||||
FIO1SET = BIT0; //all off
|
||||
FIO1SET = BIT0; //all off
|
||||
FIO3SET = BIT25 + BIT26;
|
||||
|
||||
// Config and Disable PA
|
||||
// FIO1DIR |= BIT25 + BIT26 + BIT22;
|
||||
// FIO1SET = BIT26;
|
||||
// FIO1CLR = BIT25;
|
||||
// FIO1CLR = BIT22; // PA /Shutdown
|
||||
// FIO1DIR |= BIT25 + BIT26 + BIT22;
|
||||
// FIO1SET = BIT26;
|
||||
// FIO1CLR = BIT25;
|
||||
// FIO1CLR = BIT22; // PA /Shutdown
|
||||
// Important: First put this Port as DA 2.0V and then turn on PA!!
|
||||
// FIO0DIR |= BIT26;
|
||||
// FIO0SET = BIT26;
|
||||
// 1.22 + 1.25 + 1.26
|
||||
// FIO0DIR |= BIT26;
|
||||
// FIO0SET = BIT26;
|
||||
// 1.22 + 1.25 + 1.26
|
||||
|
||||
// Configure GPS
|
||||
PINMODE3 |= BIT3 + BIT7; // No Pullup on 1.17 & 1.19
|
||||
@ -134,44 +134,44 @@ void bl_init_ports(void)
|
||||
PINSEL9 |= BIT24 + BIT25 + BIT26 + BIT27; //4.28 & 4.29 as Uart3
|
||||
|
||||
// Nanotron
|
||||
FIO2DIR &= ~BIT8; // nanotron uC IRQ as input
|
||||
FIO1DIR |= BIT15; // nanotron power on reset
|
||||
FIO1DIR &= ~BIT14; // nanotron uC RESET as input
|
||||
FIO1DIR &= ~BIT10; // nanotron uC Vcc as input
|
||||
FIO1DIR |= BIT9; // nanotron ENABLE as output
|
||||
FIO1DIR &= ~BIT4; // nanotron Rx/Tx as input
|
||||
FIO2DIR &= ~BIT8; // nanotron uC IRQ as input
|
||||
FIO1DIR |= BIT15; // nanotron power on reset
|
||||
FIO1DIR &= ~BIT14; // nanotron uC RESET as input
|
||||
FIO1DIR &= ~BIT10; // nanotron uC Vcc as input
|
||||
FIO1DIR |= BIT9; // nanotron ENABLE as output
|
||||
FIO1DIR &= ~BIT4; // nanotron Rx/Tx as input
|
||||
|
||||
FIO1CLR = BIT15;
|
||||
FIO1CLR = BIT9; // Enable power
|
||||
FIO1CLR = BIT9; // Enable power
|
||||
|
||||
PINMODE1 |= BIT1; // No Pullup for CS
|
||||
FIO0DIR |= BIT16; // CS as output
|
||||
FIO0SET = BIT16; // drive cs inactive
|
||||
FIO0SET = BIT16; // drive cs inactive
|
||||
FIO0DIR |= BIT18 + BIT15; // SPi Output
|
||||
|
||||
// RFID
|
||||
// FIO1DIR |= BIT1; // RFID Power
|
||||
// FIO1CLR = BIT1;
|
||||
// FIO1DIR |= BIT1; // RFID Power
|
||||
// FIO1CLR = BIT1;
|
||||
//
|
||||
// FIO0DIR |= BIT1; // RFID Reset
|
||||
// FIO0SET = BIT1; // Hold in Reset
|
||||
// FIO0DIR |= BIT1; // RFID Reset
|
||||
// FIO0SET = BIT1; // Hold in Reset
|
||||
//
|
||||
// FIO0DIR &= ~BIT10; // LED as INPUT
|
||||
// FIO0DIR &= ~BIT11; // DATA as INPUT
|
||||
// PINMODE0 |= BIT19 + BIT21; // No Pullups
|
||||
// 1.1 + 0.1 + 0.10 + 0.11
|
||||
// FIO0DIR &= ~BIT10; // LED as INPUT
|
||||
// FIO0DIR &= ~BIT11; // DATA as INPUT
|
||||
// PINMODE0 |= BIT19 + BIT21; // No Pullups
|
||||
// 1.1 + 0.1 + 0.10 + 0.11
|
||||
|
||||
// LTC4150 ARM
|
||||
FIO0DIR |= BIT5;
|
||||
FIO0CLR = BIT5;
|
||||
|
||||
// LTC4150 System
|
||||
// FIO0DIR |= BIT24;
|
||||
// FIO0CLR = BIT24;
|
||||
// 0.23 + 0.24
|
||||
// FIO0DIR |= BIT24;
|
||||
// FIO0CLR = BIT24;
|
||||
// 0.23 + 0.24
|
||||
|
||||
// Battery Voltage (AD)
|
||||
PINMODE1 |= BIT19; //0.25
|
||||
PINMODE1 |= BIT19; //0.25
|
||||
PINSEL1 &= ~BIT19;
|
||||
PINSEL1 |= BIT18;
|
||||
|
||||
@ -186,7 +186,7 @@ void bl_init_ports(void)
|
||||
FIO1SET = BIT20 + 24;
|
||||
|
||||
//SHT11
|
||||
FIO1DIR |= BIT25; //1.25
|
||||
FIO1DIR |= BIT25; //1.25
|
||||
PINSEL3 &= ~(BIT12 | BIT13 | BIT18 | BIT19);
|
||||
|
||||
//SD
|
||||
|
||||
@ -10,8 +10,8 @@
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @ingroup LPC2387
|
||||
* @brief CC1100 LPC2387 dependend functions
|
||||
* @ingroup LPC2387
|
||||
* @brief CC1100 LPC2387 dependend functions
|
||||
*
|
||||
* @author Heiko Will <hwill@inf.fu-berlin.de>
|
||||
* @author Thomas Hillebrandt <hillebra@inf.fu-berlin.de>
|
||||
@ -32,7 +32,7 @@
|
||||
|
||||
#define CC1100_GDO0 (FIO2PIN & BIT6) // read serial I/O (GDO0)
|
||||
#define CC1100_GDO1 (FIO0PIN & BIT8) // read serial I/O (GDO1)
|
||||
#define CC1100_GDO2 (FIO0PIN & BIT28) // read serial I/O (GDO2)
|
||||
#define CC1100_GDO2 (FIO0PIN & BIT28) // read serial I/O (GDO2)
|
||||
|
||||
#define SPI_TX_EMPTY (SSP1SR & SSPSR_TFE)
|
||||
#define SPI_BUSY (SSP1SR & SSPSR_BSY)
|
||||
@ -114,7 +114,7 @@ void cc110x_spi_init(void)
|
||||
|
||||
// Clear RxFIFO:
|
||||
while (SPI_RX_AVAIL) { // while RNE (Receive FIFO Not Empty)...
|
||||
dummy = SSP1DR; // read data
|
||||
dummy = SSP1DR; // read data
|
||||
}
|
||||
|
||||
/* to suppress unused-but-set-variable */
|
||||
|
||||
@ -72,7 +72,7 @@ typedef struct {
|
||||
* in Float-mode
|
||||
*/
|
||||
uint8_t countRange;
|
||||
uint8_t range; //current range
|
||||
uint8_t range; //current range
|
||||
} settingsSMB380;
|
||||
|
||||
settingsSMB380 settings;
|
||||
@ -204,7 +204,7 @@ uint8_t SMB380_init(uint8_t (*func)(int16_t *))
|
||||
smb380function = smb380emptyfunction;
|
||||
}
|
||||
|
||||
//smb380function = SMB380_HystereseFunctionSample; //placeholder
|
||||
//smb380function = SMB380_HystereseFunctionSample; //placeholder
|
||||
|
||||
SMB380_softReset();
|
||||
hwtimer_wait(HWTIMER_TICKS(100000));
|
||||
@ -266,12 +266,12 @@ static void SMB380_extIntHandler(void)
|
||||
|
||||
writeRingBuff(accInt);
|
||||
|
||||
// printf("SMB380 acc x,y,z: [%i|%i|%i|%2.3f]\r\n", accInt[0], accInt[1],
|
||||
// printf("SMB380 acc x,y,z: [%i|%i|%i|%2.3f]\r\n", accInt[0], accInt[1],
|
||||
// accInt[2], acc[3]);
|
||||
// printf("SMB380 acc x,y,z: [%2.3f|%2.3f|%2.3f|%2.3f]\r\n\n\n", acc[0],
|
||||
// printf("SMB380 acc x,y,z: [%2.3f|%2.3f|%2.3f|%2.3f]\r\n\n\n", acc[0],
|
||||
// acc[1], acc[2], acc[3]);
|
||||
// printf("Nach Interrupt Reset:\n");
|
||||
// SMB380_ShowMemory();
|
||||
// printf("Nach Interrupt Reset:\n");
|
||||
// SMB380_ShowMemory();
|
||||
}
|
||||
|
||||
void SMB380_setSampleRate(uint16_t rate)
|
||||
@ -397,7 +397,7 @@ uint8_t readRingBuff(int16_t *value)
|
||||
//TODO: more read-pointer
|
||||
uint8_t writeRingBuff(int16_t *value)
|
||||
{
|
||||
if (smb380_mode == SMB380_FALSEALERT) {
|
||||
if (smb380_mode == SMB380_FALSEALERT) {
|
||||
smb380_mode = SMB380_THRESHOLD;
|
||||
return 0;
|
||||
}
|
||||
@ -578,7 +578,7 @@ int16_t SMB380_getTemperature(void)
|
||||
SMB380_Prepare();
|
||||
SMB380_ssp_write(SMB380_TEMP, 0, SMB380_READ_REGISTER);
|
||||
|
||||
// t = (SMB380_ssp_read() & 0xFF) / 2.0 + SMB380_TEMP_OFFSET;
|
||||
// t = (SMB380_ssp_read() & 0xFF) / 2.0 + SMB380_TEMP_OFFSET;
|
||||
t = (SMB380_ssp_read() & 0xFF);
|
||||
t = (t >> 1) + SMB380_TEMP_OFFSET;
|
||||
SMB380_Unprepare();
|
||||
@ -848,7 +848,7 @@ void SMB380_Selftest_1(void)
|
||||
uReg &= ~SMB380_CONTROL1_SELF_TEST_1_MASK;
|
||||
uReg |= 0x01 << 3;
|
||||
SMB380_ssp_write(SMB380_CONTROL1, uReg, SMB380_WRITE_REGISTER);
|
||||
// SSP0Init();
|
||||
// SSP0Init();
|
||||
SMB380_ssp_read();
|
||||
SMB380_Unprepare();
|
||||
restoreIRQ(cpsr);
|
||||
|
||||
@ -46,10 +46,10 @@ uint32_t SSP0Init(void)
|
||||
//TODO: configure CLK, MISO, MOSI by default as GPIOs.
|
||||
#if USE_CS
|
||||
// P1.20 1.21 1.23 1.24
|
||||
// PINSEL3 |= BIT8 | BIT9 | BIT10 | BIT11 | BIT14 | BIT15 | BIT16 | BIT17;
|
||||
// PINSEL3 |= BIT8 | BIT9 | BIT10 | BIT11 | BIT14 | BIT15 | BIT16 | BIT17;
|
||||
#else
|
||||
// No SSEL0
|
||||
// PINSEL3 |= BIT8 | BIT9 | BIT14 | BIT15 | BIT16 | BIT17; //1.20 1.23 1.24
|
||||
// PINSEL3 |= BIT8 | BIT9 | BIT14 | BIT15 | BIT16 | BIT17; //1.20 1.23 1.24
|
||||
#endif
|
||||
|
||||
#if SSP1_INTERRUPT_MODE
|
||||
@ -81,7 +81,7 @@ uint8_t SSP0Prepare(uint8_t chip, uint8_t datasize, uint8_t cpol, uint8_t cpha,
|
||||
case SMB380_ACC: {
|
||||
#if USE_CS
|
||||
PINSEL3 |= BIT8 | BIT9 | BIT10 | BIT11 | BIT14 | BIT15 | BIT16 |
|
||||
BIT17; //P1.20 1.21 1.23 1.24
|
||||
BIT17; //P1.20 1.21 1.23 1.24
|
||||
#else
|
||||
// 1.20 1.23 1.24 are not configured as SSEL0
|
||||
PINSEL3 |= BIT8 | BIT9 | BIT14 | BIT15 | BIT16 | BIT17;
|
||||
@ -186,7 +186,7 @@ uint8_t SSP0Prepare(uint8_t chip, uint8_t datasize, uint8_t cpol, uint8_t cpha,
|
||||
|
||||
SSP0CR1 = 0x00; // SSP0 disabled
|
||||
|
||||
// Setting xx-Bit Datasize, CPOL and CPHA
|
||||
// Setting xx-Bit Datasize, CPOL and CPHA
|
||||
SSP0CR0 = SSP0CR0tmp;
|
||||
|
||||
// Clock Setup
|
||||
@ -221,8 +221,8 @@ uint8_t SSP0Unprepare(uint8_t chip)
|
||||
PINSEL3 &= ~(BIT8 | BIT9 | BIT10 | BIT11 | BIT14 | BIT15 | BIT16 |
|
||||
BIT17);
|
||||
FIO1DIR |= BIT20 | BIT21 | BIT24;
|
||||
FIO1DIR &= ~BIT23; // MISO as Input
|
||||
FIO1SET = BIT20 | BIT24; /*
|
||||
FIO1DIR &= ~BIT23; // MISO as Input
|
||||
FIO1SET = BIT20 | BIT24; /*
|
||||
* CLK + SSEL + MOSI GPIO as Output
|
||||
* TODO: depends on CPOL+CPHA Settings
|
||||
*/
|
||||
|
||||
@ -26,7 +26,7 @@
|
||||
#include "bitarithm.h"
|
||||
#include "msba2_common.h"
|
||||
|
||||
#define FEUERWARE_CONF_BOARD_NAME "FU Berlin AVSEXTREM BOARD"
|
||||
#define FEUERWARE_CONF_BOARD_NAME "FU Berlin AVSEXTREM BOARD"
|
||||
|
||||
#define LED_RED_PIN (BIT25)
|
||||
#define LED_GREEN_PIN (BIT26)
|
||||
@ -42,19 +42,19 @@
|
||||
|
||||
|
||||
#ifdef MODULE_CC110X
|
||||
#define FEUERWARE_CONF_NUM_RADIOS 1
|
||||
#define FEUERWARE_CONF_NUM_RADIOS 1
|
||||
#else
|
||||
#define FEUERWARE_CONF_NUM_RADIOS 0
|
||||
#define FEUERWARE_CONF_NUM_RADIOS 0
|
||||
#endif
|
||||
|
||||
// if FAT is enabled this board supports files
|
||||
#define FEUERWARE_CONF_CORE_SUPPORTS_FILES defined(MODULE_FAT)
|
||||
|
||||
#ifdef MODULE_FAT
|
||||
#define CFG_CONF_MEM_SIZE 0x7FFFFFFF
|
||||
#define SYSLOG_CONF_NUM_INTERFACES 2
|
||||
#define CFG_CONF_MEM_SIZE 0x7FFFFFFF
|
||||
#define SYSLOG_CONF_NUM_INTERFACES 2
|
||||
#else
|
||||
#define SYSLOG_CONF_NUM_INTERFACES 1
|
||||
#define SYSLOG_CONF_NUM_INTERFACES 1
|
||||
#endif
|
||||
|
||||
void init_clks1(void);
|
||||
|
||||
@ -42,7 +42,7 @@
|
||||
|
||||
#ifdef MODULE_SYSMON
|
||||
#ifndef TRACELOG_CONF_NUM_ENTRIES
|
||||
#define TRACELOG_CONF_NUM_ENTRIES 10
|
||||
#define TRACELOG_CONF_NUM_ENTRIES 10
|
||||
#endif
|
||||
#else
|
||||
#undef TRACELOG_CONF_NUM_ENTRIES
|
||||
@ -56,17 +56,17 @@
|
||||
|
||||
/**
|
||||
* @def FEUERWARE_CONF_BOARD_NAME
|
||||
* @brief Defines the name of the board as a string
|
||||
* @brief Defines the name of the board as a string
|
||||
*/
|
||||
|
||||
/**
|
||||
* @def FEUERWARE_CONF_CPU_NAME
|
||||
* @brief Defines the name of the cpu as a string
|
||||
* @brief Defines the name of the cpu as a string
|
||||
*/
|
||||
|
||||
/**
|
||||
* @def FEUERWARE_CONF_SUPPORTS_FILES
|
||||
* @brief Defines if standard library file functions are available
|
||||
* @brief Defines if standard library file functions are available
|
||||
*/
|
||||
#ifndef FEUERWARE_CONF_SUPPORTS_FILES
|
||||
#define FEUERWARE_CONF_SUPPORTS_FILES 0
|
||||
|
||||
@ -27,13 +27,13 @@
|
||||
|
||||
#define SMB380_DEBUG_MESSAGE "SMB380 Driver Error: "
|
||||
|
||||
#define MSG_TYPE_SMB380_WAKEUP 814
|
||||
#define MSG_TYPE_SMB380_WAKEUP 814
|
||||
|
||||
#define SMB380_X_AXIS 0 //X Axis-Name
|
||||
#define SMB380_Y_AXIS 1 //Y Axis-Name
|
||||
#define SMB380_Z_AXIS 2 //Z Axis-Name
|
||||
#define SMB380_X_AXIS 0 //X Axis-Name
|
||||
#define SMB380_Y_AXIS 1 //Y Axis-Name
|
||||
#define SMB380_Z_AXIS 2 //Z Axis-Name
|
||||
|
||||
#define LPM_PREVENT_SLEEP_ACCSENSOR BIT2
|
||||
#define LPM_PREVENT_SLEEP_ACCSENSOR BIT2
|
||||
|
||||
enum SMB380_MODE {
|
||||
SMB380_POLL,
|
||||
@ -52,125 +52,125 @@ volatile enum SMB380_MODE smb380_mode;// = SMB380_POLL;
|
||||
registers 0x14 and 34h are especially critical.
|
||||
*/
|
||||
|
||||
#define SMB380_EEPROM_OFFSET 0x20
|
||||
#define SMB380_EEPROM_OFFSET 0x20
|
||||
//Chip-ID Bit0-2, default: 010b
|
||||
#define SMB380_CHIP_ID 0x00
|
||||
#define SMB380_CHIP_ID 0x00
|
||||
//Chip-ID mask
|
||||
#define SMB380_CHIP_ID_MASK 0x07
|
||||
#define SMB380_CHIP_ID_MASK 0x07
|
||||
//ml_version Bit0-3 ; al_version Bit4-7
|
||||
#define SMB380_AL_ML_VERSION 0x01
|
||||
#define SMB380_AL_MASK 0xF0
|
||||
#define SMB380_ML_MASK 0x0F
|
||||
#define SMB380_AL_ML_VERSION 0x01
|
||||
#define SMB380_AL_MASK 0xF0
|
||||
#define SMB380_ML_MASK 0x0F
|
||||
//LSB_acc_x Bit6-7; new_data_x Bit0
|
||||
#define SMB380_ACC_X_LSB_NEWDATA 0x02
|
||||
#define SMB380_ACC_X_LSB_NEWDATA 0x02
|
||||
//MSB_acc_x Bit0-7
|
||||
#define SMB380_ACC_X_MSB 0x03
|
||||
#define SMB380_ACC_X_MSB 0x03
|
||||
//LSB_acc_y Bit6-7; new_data_y Bit0
|
||||
#define SMB380_ACC_Y_LSB_NEWDATA 0x04
|
||||
#define SMB380_ACC_Y_LSB_NEWDATA 0x04
|
||||
//MSB_acc_y Bit0-7
|
||||
#define SMB380_ACC_Y_MSB 0x05
|
||||
#define SMB380_ACC_Y_MSB 0x05
|
||||
//LSB_acc_z Bit6-7; new_data_z Bit0
|
||||
#define SMB380_ACC_Z_LSB_NEWDATA 0x06
|
||||
#define SMB380_ACC_Z_LSB_NEWDATA 0x06
|
||||
//MSB_acc_z Bit0-7
|
||||
#define SMB380_ACC_Z_MSB 0x07
|
||||
#define SMB380_ACC_LSB_MASK 0xC0
|
||||
#define SMB380_ACC_MSB_MASK 0xFF
|
||||
#define SMB380_ACC_NEWDATA_MASK 0x01
|
||||
#define SMB380_ACC_Z_MSB 0x07
|
||||
#define SMB380_ACC_LSB_MASK 0xC0
|
||||
#define SMB380_ACC_MSB_MASK 0xFF
|
||||
#define SMB380_ACC_NEWDATA_MASK 0x01
|
||||
//Temperature Bit0-7
|
||||
#define SMB380_TEMP 0x08
|
||||
#define SMB380_TEMP 0x08
|
||||
//Status register, contains six flags
|
||||
#define SMB380_STATUS 0x09
|
||||
#define SMB380_STATUS_ST_RESULT_MASK 0x80
|
||||
#define SMB380_STATUS_ALERT_PHASE_MASK 0x10
|
||||
#define SMB380_STATUS_LG_LATCHED_MASK 0x08
|
||||
#define SMB380_STATUS_HG_LATCHED_MASK 0x04
|
||||
#define SMB380_STATUS_STATUS_LG_MASK 0x02
|
||||
#define SMB380_STATUS_STATUS_HG_MASK 0x01
|
||||
#define SMB380_STATUS 0x09
|
||||
#define SMB380_STATUS_ST_RESULT_MASK 0x80
|
||||
#define SMB380_STATUS_ALERT_PHASE_MASK 0x10
|
||||
#define SMB380_STATUS_LG_LATCHED_MASK 0x08
|
||||
#define SMB380_STATUS_HG_LATCHED_MASK 0x04
|
||||
#define SMB380_STATUS_STATUS_LG_MASK 0x02
|
||||
#define SMB380_STATUS_STATUS_HG_MASK 0x01
|
||||
//Control register - contains seven values, default: x000 0000b
|
||||
#define SMB380_CONTROL1 0x0A
|
||||
#define SMB380_CONTROL1_RESET_INT_MASK 0x40
|
||||
#define SMB380_CONTROL1_UPDATE_MASK 0x20
|
||||
#define SMB380_CONTROL1_EE_W_MASK 0x10
|
||||
#define SMB380_CONTROL1_SELF_TEST_1_MASK 0x08
|
||||
#define SMB380_CONTROL1_SELF_TEST_0_MASK 0x04
|
||||
#define SMB380_CONTROL1_SOFT_RESET_MASK 0x02
|
||||
#define SMB380_CONTROL1_SLEEP_MASK 0x01
|
||||
#define SMB380_CONTROL1 0x0A
|
||||
#define SMB380_CONTROL1_RESET_INT_MASK 0x40
|
||||
#define SMB380_CONTROL1_UPDATE_MASK 0x20
|
||||
#define SMB380_CONTROL1_EE_W_MASK 0x10
|
||||
#define SMB380_CONTROL1_SELF_TEST_1_MASK 0x08
|
||||
#define SMB380_CONTROL1_SELF_TEST_0_MASK 0x04
|
||||
#define SMB380_CONTROL1_SOFT_RESET_MASK 0x02
|
||||
#define SMB380_CONTROL1_SLEEP_MASK 0x01
|
||||
//Control register - contains six values, default: x000 0011b
|
||||
#define SMB380_CONTROL2 0x0B
|
||||
#define SMB380_CONTROL2_ALERT_MASK 0x80
|
||||
#define SMB380_CONTROL2_ANY_MOTION_MASK 0x40
|
||||
#define SMB380_CONTROL2_COUNTER_HG_MASK 0x30
|
||||
#define SMB380_CONTROL2_COUNTER_LG_MASK 0x0C
|
||||
#define SMB380_CONTROL2_ENABLE_HG_MASK 0x02
|
||||
#define SMB380_CONTROL2_ENABLE_LG_MASK 0x01
|
||||
#define SMB380_CONTROL2 0x0B
|
||||
#define SMB380_CONTROL2_ALERT_MASK 0x80
|
||||
#define SMB380_CONTROL2_ANY_MOTION_MASK 0x40
|
||||
#define SMB380_CONTROL2_COUNTER_HG_MASK 0x30
|
||||
#define SMB380_CONTROL2_COUNTER_LG_MASK 0x0C
|
||||
#define SMB380_CONTROL2_ENABLE_HG_MASK 0x02
|
||||
#define SMB380_CONTROL2_ENABLE_LG_MASK 0x01
|
||||
//default: 20
|
||||
#define SMB380_LG_THRES 0x0C
|
||||
#define SMB380_LG_THRES 0x0C
|
||||
//default: 150
|
||||
#define SMB380_LG_DUR 0x0D
|
||||
#define SMB380_LG_DUR 0x0D
|
||||
//default: 160
|
||||
#define SMB380_HG_THRES 0x0E
|
||||
#define SMB380_HG_THRES 0x0E
|
||||
//default: 150
|
||||
#define SMB380_HG_DUR 0x0F
|
||||
#define SMB380_HG_DUR 0x0F
|
||||
//default: 0
|
||||
#define SMB380_ANY_MOTION_THRES 0x10
|
||||
#define SMB380_ANY_MOTION_THRES 0x10
|
||||
//default: 0000 0000b
|
||||
#define SMB380_ANY_MOTION_DUR_HYST 0x1
|
||||
#define SMB380_ANY_MOTION_DUR_MASK 0xC0
|
||||
#define SMB380_ANY_MOTION_DUR_HG_HYST_MASK 0x38
|
||||
#define SMB380_ANY_MOTION_DUR_LG_HYST_MASK 0x07
|
||||
#define SMB380_ANY_MOTION_DUR_HYST 0x1
|
||||
#define SMB380_ANY_MOTION_DUR_MASK 0xC0
|
||||
#define SMB380_ANY_MOTION_DUR_HG_HYST_MASK 0x38
|
||||
#define SMB380_ANY_MOTION_DUR_LG_HYST_MASK 0x07
|
||||
//default: 162
|
||||
#define SMB380_CUST1 0x12
|
||||
#define SMB380_CUST1 0x12
|
||||
//default: 13
|
||||
#define SMB380_CUST2 0x13
|
||||
#define SMB380_CUST2 0x13
|
||||
//default: xxx0 1110b
|
||||
#define SMB380_CONTROL3 0x14
|
||||
#define SMB380_CONTROL3_RANGE_MASK 0x18
|
||||
#define SMB380_CONTROL3_BANDWITH_MASK 0x07
|
||||
#define SMB380_CONTROL3 0x14
|
||||
#define SMB380_CONTROL3_RANGE_MASK 0x18
|
||||
#define SMB380_CONTROL3_BANDWITH_MASK 0x07
|
||||
//default: 1000 0000b
|
||||
#define SMB380_CONTROL4 0x15
|
||||
#define SMB380_CONTROL4_SPI4_MASK 0x80
|
||||
#define SMB380_CONTROL4_ENABLE_ADV_INT_MASK 0x40
|
||||
#define SMB380_CONTROL4_NEW_DATA_INT_MASK 0x20
|
||||
#define SMB380_CONTROL4_LATCH_INT_MASK 0x10
|
||||
#define SMB380_CONTROL4_SHADOW_DIS_MASK 0x08
|
||||
#define SMB380_CONTROL4_WAKEUP_PAUSE_MASK 0x06
|
||||
#define SMB380_CONTROL4_WAKEUP_MASK 0x01
|
||||
#define SMB380_CONTROL4 0x15
|
||||
#define SMB380_CONTROL4_SPI4_MASK 0x80
|
||||
#define SMB380_CONTROL4_ENABLE_ADV_INT_MASK 0x40
|
||||
#define SMB380_CONTROL4_NEW_DATA_INT_MASK 0x20
|
||||
#define SMB380_CONTROL4_LATCH_INT_MASK 0x10
|
||||
#define SMB380_CONTROL4_SHADOW_DIS_MASK 0x08
|
||||
#define SMB380_CONTROL4_WAKEUP_PAUSE_MASK 0x06
|
||||
#define SMB380_CONTROL4_WAKEUP_MASK 0x01
|
||||
|
||||
#define SMB380_OFFSET_LSB_GAIN_X 0x16
|
||||
#define SMB380_OFFSET_LSB_GAIN_Y 0x17
|
||||
#define SMB380_OFFSET_LSB_GAIN_Z 0x18
|
||||
#define SMB380_OFFSET_LSB_GAIN_T 0x19
|
||||
#define SMB380_OFFSET_LSB_MASK 0xC0
|
||||
#define SMB380_OFFSET_GAIN_MASK 0x3F
|
||||
#define SMB380_OFFSET_LSB_GAIN_X 0x16
|
||||
#define SMB380_OFFSET_LSB_GAIN_Y 0x17
|
||||
#define SMB380_OFFSET_LSB_GAIN_Z 0x18
|
||||
#define SMB380_OFFSET_LSB_GAIN_T 0x19
|
||||
#define SMB380_OFFSET_LSB_MASK 0xC0
|
||||
#define SMB380_OFFSET_GAIN_MASK 0x3F
|
||||
|
||||
#define SMB380_OFFSET_MSB_X 0x1A
|
||||
#define SMB380_OFFSET_MSB_Y 0x1B
|
||||
#define SMB380_OFFSET_MSB_Z 0x1C
|
||||
#define SMB380_OFFSET_MSB_T 0x1D
|
||||
#define SMB380_OFFSET_MSB_X 0x1A
|
||||
#define SMB380_OFFSET_MSB_Y 0x1B
|
||||
#define SMB380_OFFSET_MSB_Z 0x1C
|
||||
#define SMB380_OFFSET_MSB_T 0x1D
|
||||
|
||||
#define SMB380_TEMP_OFFSET -30
|
||||
#define SMB380_DEFAULT_MAXG 4.0f
|
||||
#define SMB380_READ_REGISTER 0x00
|
||||
#define SMB380_WRITE_REGISTER 0x01
|
||||
#define SMB380_WAKE_UP_PAUSE_20MS 0x00
|
||||
#define SMB380_WAKE_UP_PAUSE_80MS 0x01
|
||||
#define SMB380_WAKE_UP_PAUSE_320MS 0x02
|
||||
#define SMB380_WAKE_UP_PAUSE_2560MS 0x03
|
||||
#define SMB380_RANGE_2G 0x00
|
||||
#define SMB380_RANGE_4G 0x01
|
||||
#define SMB380_RANGE_8G 0x02
|
||||
#define SMB380_BAND_WIDTH_25HZ 0x00
|
||||
#define SMB380_BAND_WIDTH_50HZ 0x01
|
||||
#define SMB380_BAND_WIDTH_100HZ 0x02
|
||||
#define SMB380_BAND_WIDTH_190HZ 0x03
|
||||
#define SMB380_BAND_WIDTH_375HZ 0x04
|
||||
#define SMB380_BAND_WIDTH_750HZ 0x05
|
||||
#define SMB380_BAND_WIDTH_1500HZ 0x06
|
||||
#define SMB380_TEMP_OFFSET -30
|
||||
#define SMB380_DEFAULT_MAXG 4.0f
|
||||
#define SMB380_READ_REGISTER 0x00
|
||||
#define SMB380_WRITE_REGISTER 0x01
|
||||
#define SMB380_WAKE_UP_PAUSE_20MS 0x00
|
||||
#define SMB380_WAKE_UP_PAUSE_80MS 0x01
|
||||
#define SMB380_WAKE_UP_PAUSE_320MS 0x02
|
||||
#define SMB380_WAKE_UP_PAUSE_2560MS 0x03
|
||||
#define SMB380_RANGE_2G 0x00
|
||||
#define SMB380_RANGE_4G 0x01
|
||||
#define SMB380_RANGE_8G 0x02
|
||||
#define SMB380_BAND_WIDTH_25HZ 0x00
|
||||
#define SMB380_BAND_WIDTH_50HZ 0x01
|
||||
#define SMB380_BAND_WIDTH_100HZ 0x02
|
||||
#define SMB380_BAND_WIDTH_190HZ 0x03
|
||||
#define SMB380_BAND_WIDTH_375HZ 0x04
|
||||
#define SMB380_BAND_WIDTH_750HZ 0x05
|
||||
#define SMB380_BAND_WIDTH_1500HZ 0x06
|
||||
//SMB380_RING_BUFF_SIZE * int16_t (2Byte) * 4 (x,y,z,Temp) = 512 Byte (for 64)
|
||||
#define SMB380_RING_BUFF_SIZE 256
|
||||
#define SMB380_RING_BUFF_SIZE 256
|
||||
//TODO chsnge size to 2048
|
||||
#define SMB380_RING_BUFF_MAX_THREADS 10
|
||||
#define SMB380_SAMPLE_RATE_MAX 3000
|
||||
#define SMB380_RING_BUFF_MAX_THREADS 10
|
||||
#define SMB380_SAMPLE_RATE_MAX 3000
|
||||
|
||||
/*
|
||||
* change from Header (public) to internal use (private)
|
||||
@ -183,7 +183,7 @@ void SMB380_update_image(void);
|
||||
/*
|
||||
* change from Header (public) to internal use (private)
|
||||
* set ee_w Bit in control1 to
|
||||
* enable read to 0x16 to 0x22 and
|
||||
* enable read to 0x16 to 0x22 and
|
||||
* enable write to 0x16 to 0x3D
|
||||
**/
|
||||
void SMB380_enable_eeprom_default(void);
|
||||
|
||||
@ -23,82 +23,82 @@
|
||||
|
||||
#include "stdint.h"
|
||||
|
||||
#define DMA_ENABLED 0
|
||||
#define DMA_ENABLED 0
|
||||
|
||||
/*
|
||||
* if USE_CS is zero, set SSEL as GPIO that you have total control of the
|
||||
* sequence
|
||||
**/
|
||||
#define USE_CS 0
|
||||
#define USE_CS 0
|
||||
|
||||
/*
|
||||
* if 1, use driver for onboard BMA180, otherwise for external BMA180 utilizing
|
||||
* Nanopan Connector
|
||||
**/
|
||||
#define BMA180_ONBOARD 1
|
||||
#define BMA180_ONBOARD 1
|
||||
|
||||
#define SMB380_ACC 0
|
||||
#define NANOPAN 1
|
||||
#define NORDIC 2
|
||||
#define BMA180_EXTERN 3
|
||||
#define BMA180_INTERN 4
|
||||
#define L3G_EXTERN 5
|
||||
#define L3G_INTERN 6
|
||||
#define ACAMDMS 7
|
||||
#define SMB380_ACC 0
|
||||
#define NANOPAN 1
|
||||
#define NORDIC 2
|
||||
#define BMA180_EXTERN 3
|
||||
#define BMA180_INTERN 4
|
||||
#define L3G_EXTERN 5
|
||||
#define L3G_INTERN 6
|
||||
#define ACAMDMS 7
|
||||
|
||||
/* SPI read and write buffer size */
|
||||
#define BUFSIZE 256
|
||||
#define FIFOSIZE 8
|
||||
#define BUFSIZE 256
|
||||
#define FIFOSIZE 8
|
||||
|
||||
/* SSP select pin */
|
||||
#define SSP0_SEL 1 << 21 //P1.21 SMB380
|
||||
#define SSP0_SEL 1 << 21 //P1.21 SMB380
|
||||
|
||||
#define SSP0_SELN 1 << 16 //P0.16 Nanotron
|
||||
#define SSP0_SELN 1 << 16 //P0.16 Nanotron
|
||||
|
||||
/* SSP1 external interrupt Pin (SMB380 specific) */
|
||||
#define SMB380_INT1 1 << 1 //P0.1
|
||||
#define BMA180_INT1 1 << 8 //P2.8
|
||||
#define SMB380_INT1 1 << 1 //P0.1
|
||||
#define BMA180_INT1 1 << 8 //P2.8
|
||||
|
||||
|
||||
|
||||
/* SSP1 CR0 register */
|
||||
#define SSPCR0_DSS 1 << 0
|
||||
#define SSPCR0_FRF 1 << 4
|
||||
#define SSPCR0_SPO 1 << 6
|
||||
#define SSPCR0_SPH 1 << 7
|
||||
#define SSPCR0_SCR 1 << 8
|
||||
#define SSPCR0_DSS 1 << 0
|
||||
#define SSPCR0_FRF 1 << 4
|
||||
#define SSPCR0_SPO 1 << 6
|
||||
#define SSPCR0_SPH 1 << 7
|
||||
#define SSPCR0_SCR 1 << 8
|
||||
|
||||
/* SSP1 CR1 register */
|
||||
#define SSPCR1_LBM 1 << 0
|
||||
#define SSPCR1_SSE 1 << 1
|
||||
#define SSPCR1_MS 1 << 2
|
||||
#define SSPCR1_SOD 1 << 3
|
||||
#define SSPCR1_LBM 1 << 0
|
||||
#define SSPCR1_SSE 1 << 1
|
||||
#define SSPCR1_MS 1 << 2
|
||||
#define SSPCR1_SOD 1 << 3
|
||||
|
||||
/* SSP1 Interrupt Mask Set/Clear register */
|
||||
#define SSPIMSC_RORIM 1 << 0
|
||||
#define SSPIMSC_RTIM 1 << 1
|
||||
#define SSPIMSC_RXIM 1 << 2
|
||||
#define SSPIMSC_TXIM 1 << 3
|
||||
#define SSPIMSC_RORIM 1 << 0
|
||||
#define SSPIMSC_RTIM 1 << 1
|
||||
#define SSPIMSC_RXIM 1 << 2
|
||||
#define SSPIMSC_TXIM 1 << 3
|
||||
|
||||
/* SSP1 Interrupt Status register */
|
||||
#define SSPRIS_RORRIS 1 << 0
|
||||
#define SSPRIS_RTRIS 1 << 1
|
||||
#define SSPRIS_RXRIS 1 << 2
|
||||
#define SSPRIS_TXRIS 1 << 3
|
||||
#define SSPRIS_RORRIS 1 << 0
|
||||
#define SSPRIS_RTRIS 1 << 1
|
||||
#define SSPRIS_RXRIS 1 << 2
|
||||
#define SSPRIS_TXRIS 1 << 3
|
||||
|
||||
/* SSP1 Masked Interrupt register */
|
||||
#define SSPMIS_RORMIS 1 << 0
|
||||
#define SSPMIS_RTMIS 1 << 1
|
||||
#define SSPMIS_RXMIS 1 << 2
|
||||
#define SSPMIS_TXMIS 1 << 3
|
||||
#define SSPMIS_RORMIS 1 << 0
|
||||
#define SSPMIS_RTMIS 1 << 1
|
||||
#define SSPMIS_RXMIS 1 << 2
|
||||
#define SSPMIS_TXMIS 1 << 3
|
||||
|
||||
/* SSP1 Interrupt clear register */
|
||||
#define SSPICR_RORIC 1 << 0
|
||||
#define SSPICR_RTIC 1 << 1
|
||||
#define SSPICR_RORIC 1 << 0
|
||||
#define SSPICR_RTIC 1 << 1
|
||||
|
||||
#define SSP1_INTERRUPT_MODE 0
|
||||
#define SMB380_EXTINT_MODE 1
|
||||
#define BMA180_EXTINT_MODE 1
|
||||
#define SSP1_INTERRUPT_MODE 0
|
||||
#define SMB380_EXTINT_MODE 1
|
||||
#define BMA180_EXTINT_MODE 1
|
||||
|
||||
uint32_t SSP0Init(void);
|
||||
uint8_t SSP0Prepare(uint8_t chip, uint8_t datasize, uint8_t cpol, uint8_t cpha,
|
||||
|
||||
@ -2,10 +2,10 @@
|
||||
#define BUTTONS_H
|
||||
|
||||
// Button ports
|
||||
#define BUTTON_STAR_PIN (BIT2)
|
||||
#define BUTTON_NUM_PIN (BIT1)
|
||||
#define BUTTON_UP_PIN (BIT4)
|
||||
#define BUTTON_DOWN_PIN (BIT0)
|
||||
#define BUTTON_BACKLIGHT_PIN (BIT3)
|
||||
#define BUTTON_STAR_PIN (BIT2)
|
||||
#define BUTTON_NUM_PIN (BIT1)
|
||||
#define BUTTON_UP_PIN (BIT4)
|
||||
#define BUTTON_DOWN_PIN (BIT0)
|
||||
#define BUTTON_BACKLIGHT_PIN (BIT3)
|
||||
|
||||
#endif
|
||||
|
||||
@ -6,7 +6,7 @@
|
||||
* @author Oliver Hahm <oliver.hahm@inria.fr>
|
||||
*
|
||||
* @defgroup mbed_lpc1768 mbed NXP LPC1768 development kit
|
||||
* @ingroup boards
|
||||
* @ingroup boards
|
||||
* @brief Support for the mbed NXP LPC1768 board.
|
||||
* @{
|
||||
*/
|
||||
@ -22,8 +22,8 @@
|
||||
#define PIN_LED3 (BIT21)
|
||||
#define PIN_LED4 (BIT23)
|
||||
|
||||
#define LED_ON(led_nr) (LPC_GPIO1->FIOSET = PIN_LED##led_nr)
|
||||
#define LED_OFF(led_nr) (LPC_GPIO1->FIOCLR = PIN_LED##led_nr)
|
||||
#define LED_ON(led_nr) (LPC_GPIO1->FIOSET = PIN_LED##led_nr)
|
||||
#define LED_OFF(led_nr) (LPC_GPIO1->FIOCLR = PIN_LED##led_nr)
|
||||
#define LED_TOGGLE(led_nr) (LPC_GPIO1->FIOPIN ^= PIN_LED##led_nr)
|
||||
|
||||
typedef uint8_t radio_packet_length_t;
|
||||
|
||||
@ -19,22 +19,22 @@ You should have received a copy of the GNU General Public License along with
|
||||
this program. If not, see http://www.gnu.org/licenses/ .
|
||||
--------------------------------------------------------------------------------
|
||||
For further information and questions please use the web site
|
||||
http://scatterweb.mi.fu-berlin.de
|
||||
http://scatterweb.mi.fu-berlin.de
|
||||
and the mailinglist (subscription via web site)
|
||||
scatterweb@lists.spline.inf.fu-berlin.de
|
||||
scatterweb@lists.spline.inf.fu-berlin.de
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef SHT11BOARD_H_
|
||||
#define SHT11BOARD_H_
|
||||
|
||||
/**
|
||||
* @ingroup msb_430h
|
||||
* @ingroup msb_430h
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief SHT11 Device Driver Configuration For MSB-430 Platform
|
||||
* @brief SHT11 Device Driver Configuration For MSB-430 Platform
|
||||
*
|
||||
* @author Freie Universität Berlin, Computer Systems & Telematics, RIOT
|
||||
*
|
||||
@ -46,14 +46,14 @@ and the mailinglist (subscription via web site)
|
||||
* DATA = P3B4
|
||||
*/
|
||||
|
||||
#define SHT11_SCK_LOW P3OUT &= ~(BIT5); /**< serial clock line low */
|
||||
#define SHT11_SCK_HIGH P3OUT |= BIT5; /**< serial clock line high */
|
||||
#define SHT11_DATA (P3IN & BIT5) /**< read serial I/O */
|
||||
#define SHT11_DATA_LOW P3OUT &= ~(BIT5); /**< serial I/O line low */
|
||||
#define SHT11_DATA_HIGH P3OUT |= BIT5; /**< serial I/O line high */
|
||||
#define SHT11_DATA_IN P3DIR &= ~(BIT5); /**< serial I/O as input */
|
||||
#define SHT11_DATA_OUT P3DIR |= BIT5; /**< serial I/O as output */
|
||||
#define SHT11_INIT P3DIR |= BIT5; /* FIO1DIR |= BIT25; PINSEL3 &= ~(BIT14|BIT15 | BIT16|BIT17); */
|
||||
#define SHT11_SCK_LOW P3OUT &= ~(BIT5); /**< serial clock line low */
|
||||
#define SHT11_SCK_HIGH P3OUT |= BIT5; /**< serial clock line high */
|
||||
#define SHT11_DATA (P3IN & BIT5) /**< read serial I/O */
|
||||
#define SHT11_DATA_LOW P3OUT &= ~(BIT5); /**< serial I/O line low */
|
||||
#define SHT11_DATA_HIGH P3OUT |= BIT5; /**< serial I/O line high */
|
||||
#define SHT11_DATA_IN P3DIR &= ~(BIT5); /**< serial I/O as input */
|
||||
#define SHT11_DATA_OUT P3DIR |= BIT5; /**< serial I/O as output */
|
||||
#define SHT11_INIT P3DIR |= BIT5; /* FIO1DIR |= BIT25; PINSEL3 &= ~(BIT14|BIT15 | BIT16|BIT17); */
|
||||
|
||||
/** @} */
|
||||
#endif /* SHT11BOARD_H_ */
|
||||
|
||||
@ -19,9 +19,9 @@ You should have received a copy of the GNU General Public License along with
|
||||
this program. If not, see http://www.gnu.org/licenses/ .
|
||||
--------------------------------------------------------------------------------
|
||||
For further information and questions please use the web site
|
||||
http://scatterweb.mi.fu-berlin.de
|
||||
http://scatterweb.mi.fu-berlin.de
|
||||
and the mailinglist (subscription via web site)
|
||||
scatterweb@lists.spline.inf.fu-berlin.de
|
||||
scatterweb@lists.spline.inf.fu-berlin.de
|
||||
*******************************************************************************/
|
||||
|
||||
/**
|
||||
@ -61,13 +61,13 @@ and the mailinglist (subscription via web site)
|
||||
/* LEDs ports MSB430 */
|
||||
#define LEDS_PxDIR P5DIR
|
||||
#define LEDS_PxOUT P5OUT
|
||||
#define LEDS_CONF_RED 0x80
|
||||
#define LEDS_CONF_GREEN 0x00
|
||||
#define LEDS_CONF_YELLOW 0x00
|
||||
#define LEDS_CONF_RED 0x80
|
||||
#define LEDS_CONF_GREEN 0x00
|
||||
#define LEDS_CONF_YELLOW 0x00
|
||||
|
||||
#define LED_RED_ON LEDS_PxOUT &=~LEDS_CONF_RED
|
||||
#define LED_RED_OFF LEDS_PxOUT |= LEDS_CONF_RED
|
||||
#define LED_RED_TOGGLE LEDS_PxOUT ^= LEDS_CONF_RED
|
||||
#define LED_RED_ON LEDS_PxOUT &=~LEDS_CONF_RED
|
||||
#define LED_RED_OFF LEDS_PxOUT |= LEDS_CONF_RED
|
||||
#define LED_RED_TOGGLE LEDS_PxOUT ^= LEDS_CONF_RED
|
||||
|
||||
#include "board-conf.h"
|
||||
|
||||
|
||||
@ -124,7 +124,7 @@ cs_low:
|
||||
// has stabilized and the crystal is running)
|
||||
loop:
|
||||
|
||||
// asm volatile ("nop");
|
||||
// asm volatile ("nop");
|
||||
if (CC1100_GDO1) {
|
||||
abort_count++;
|
||||
|
||||
@ -137,7 +137,7 @@ loop:
|
||||
}
|
||||
|
||||
CC1100_CS_HIGH;
|
||||
goto cs_low; // try again
|
||||
goto cs_low; // try again
|
||||
}
|
||||
|
||||
goto loop;
|
||||
@ -216,100 +216,100 @@ void cc110x_spi_init(void)
|
||||
// // void spiInitTrx(void)
|
||||
// //
|
||||
// // DESCRIPTION:
|
||||
// // This function puts the cc110x into spi mode. You have to call this bevore every spi transaction.
|
||||
// // This function puts the cc110x into spi mode. You have to call this bevore every spi transaction.
|
||||
// //
|
||||
// //-------------------------------------------------------------------------------------------------------
|
||||
//
|
||||
//
|
||||
// void drivercc110x_spiwriteburstreg(uint8_t addr, unsigned char *buffer, uint8_t count)
|
||||
// {
|
||||
// uint8_t i;
|
||||
// long c;
|
||||
// drivercc110x_spiinittrx();
|
||||
// drivercc110x_trxspi(addr | CC1100_WRITE_BURST);
|
||||
// for (i = 0; i < count; i++)
|
||||
// {
|
||||
// c = 0;
|
||||
// IFG1 &= ~UTXIFG0;
|
||||
// IFG1 &= ~URXIFG0;
|
||||
// TXBUF0 = buffer[i];
|
||||
// /* Wait for TX to finish */
|
||||
// while(!(IFG1 & UTXIFG0))
|
||||
// {
|
||||
// if (c++ == 1000000)
|
||||
// alarm();
|
||||
// }
|
||||
// }
|
||||
// /* Wait for Byte received */
|
||||
// c = 0;
|
||||
// while(!(IFG1 & URXIFG0))
|
||||
// {
|
||||
// if (c++ == 1000000)
|
||||
// alarm();
|
||||
// }
|
||||
// CC1100_CS_HIGH;
|
||||
// uint8_t i;
|
||||
// long c;
|
||||
// drivercc110x_spiinittrx();
|
||||
// drivercc110x_trxspi(addr | CC1100_WRITE_BURST);
|
||||
// for (i = 0; i < count; i++)
|
||||
// {
|
||||
// c = 0;
|
||||
// IFG1 &= ~UTXIFG0;
|
||||
// IFG1 &= ~URXIFG0;
|
||||
// TXBUF0 = buffer[i];
|
||||
// /* Wait for TX to finish */
|
||||
// while(!(IFG1 & UTXIFG0))
|
||||
// {
|
||||
// if (c++ == 1000000)
|
||||
// alarm();
|
||||
// }
|
||||
// }
|
||||
// /* Wait for Byte received */
|
||||
// c = 0;
|
||||
// while(!(IFG1 & URXIFG0))
|
||||
// {
|
||||
// if (c++ == 1000000)
|
||||
// alarm();
|
||||
// }
|
||||
// CC1100_CS_HIGH;
|
||||
// }
|
||||
//
|
||||
// void drivercc110x_spireadburstreg(uint8_t addr, char *buffer, uint8_t count)
|
||||
// {
|
||||
// uint8_t i;
|
||||
// drivercc110x_spiinittrx();
|
||||
// drivercc110x_trxspi(addr | CC1100_READ_BURST);
|
||||
// for (i = 0; i < count; i++)
|
||||
// {
|
||||
// long c = 0;
|
||||
// IFG1 &= ~UTXIFG0;
|
||||
// IFG1 &= ~URXIFG0;
|
||||
// TXBUF0 = NOBYTE;
|
||||
// while(!(IFG1 & UTXIFG0))
|
||||
// {
|
||||
// if (c++ == 1000000)
|
||||
// alarm();
|
||||
// }
|
||||
// /* Wait for Byte received */
|
||||
// c = 0;
|
||||
// while(!(IFG1 & URXIFG0))
|
||||
// {
|
||||
// if (c++ == 1000000)
|
||||
// alarm();
|
||||
// }
|
||||
// buffer[i] = RXBUF0;
|
||||
// }
|
||||
// CC1100_CS_HIGH;
|
||||
// uint8_t i;
|
||||
// drivercc110x_spiinittrx();
|
||||
// drivercc110x_trxspi(addr | CC1100_READ_BURST);
|
||||
// for (i = 0; i < count; i++)
|
||||
// {
|
||||
// long c = 0;
|
||||
// IFG1 &= ~UTXIFG0;
|
||||
// IFG1 &= ~URXIFG0;
|
||||
// TXBUF0 = NOBYTE;
|
||||
// while(!(IFG1 & UTXIFG0))
|
||||
// {
|
||||
// if (c++ == 1000000)
|
||||
// alarm();
|
||||
// }
|
||||
// /* Wait for Byte received */
|
||||
// c = 0;
|
||||
// while(!(IFG1 & URXIFG0))
|
||||
// {
|
||||
// if (c++ == 1000000)
|
||||
// alarm();
|
||||
// }
|
||||
// buffer[i] = RXBUF0;
|
||||
// }
|
||||
// CC1100_CS_HIGH;
|
||||
// }
|
||||
//
|
||||
// void drivercc110x_load(callback_t cs_cb,callback_t paket_cb)
|
||||
// {
|
||||
// _paket_cb = paket_cb;
|
||||
// _cs_cb = cs_cb;
|
||||
// spi0_init(0);
|
||||
// _paket_cb = paket_cb;
|
||||
// _cs_cb = cs_cb;
|
||||
// spi0_init(0);
|
||||
// }
|
||||
//
|
||||
// void drivercc110x_aftersend(void)
|
||||
// {
|
||||
// CLEAR(P2IFG, 0x01);
|
||||
// SET(P2IE, 0x01); /* Enable interrupts on port 2 pin 0 */
|
||||
// CLEAR(P4OUT, 0x08); /* Turn off Sending Led*/
|
||||
// SET(P2IE, 0x01); /* Enable interrupts on port 2 pin 0 */
|
||||
// CLEAR(P4OUT, 0x08); /* Turn off Sending Led*/
|
||||
// }
|
||||
//
|
||||
// void drivercc110x_initinterrupts(void)
|
||||
// {
|
||||
// _DINT(); /* Disable all interrupts */
|
||||
// P2SEL = 0x00; /* must be <> 1 to use interrupts */
|
||||
// SET(P2IES, 0x01); /* Enables external interrupt on low edge (for GDO2) */
|
||||
// SET(P2IE, 0x01); /* Enable interrupt */
|
||||
// _DINT(); /* Disable all interrupts */
|
||||
// P2SEL = 0x00; /* must be <> 1 to use interrupts */
|
||||
// SET(P2IES, 0x01); /* Enables external interrupt on low edge (for GDO2) */
|
||||
// SET(P2IE, 0x01); /* Enable interrupt */
|
||||
// CLEAR(P2IFG, 0x01); /* Clears the interrupt flag */
|
||||
// CLEAR(P2IE, 0x02); /* Disable interrupt for GDO0 */
|
||||
// CLEAR(P2IFG, 0x02); /* Clear IFG for GDO0 */
|
||||
// _EINT(); /* Enable all interrupts */
|
||||
// CLEAR(P2IE, 0x02); /* Disable interrupt for GDO0 */
|
||||
// CLEAR(P2IFG, 0x02); /* Clear IFG for GDO0 */
|
||||
// _EINT(); /* Enable all interrupts */
|
||||
// }
|
||||
//
|
||||
// void drivercc110x_beforesend(void)
|
||||
// {
|
||||
// /* Turn on Led while sending paket for debug reasons */
|
||||
// SET(P4OUT, 0x08);
|
||||
// /* Disable interrupts on port 2 pin 0 */
|
||||
// CLEAR(P2IE, 0x01);
|
||||
// /* Turn on Led while sending paket for debug reasons */
|
||||
// SET(P4OUT, 0x08);
|
||||
// /* Disable interrupts on port 2 pin 0 */
|
||||
// CLEAR(P2IE, 0x01);
|
||||
// }
|
||||
//
|
||||
//
|
||||
@ -325,7 +325,7 @@ void cc110x_spi_init(void)
|
||||
interrupt(PORT2_VECTOR) __attribute__((naked)) cc110x_isr(void)
|
||||
{
|
||||
__enter_isr();
|
||||
// if (system_state.POWERDOWN) SPI_INIT; /* Initialize SPI after wakeup */
|
||||
// if (system_state.POWERDOWN) SPI_INIT; /* Initialize SPI after wakeup */
|
||||
/* Check IFG */
|
||||
if ((P2IFG & 0x01) != 0) {
|
||||
P2IFG &= ~0x01;
|
||||
@ -333,15 +333,15 @@ interrupt(PORT2_VECTOR) __attribute__((naked)) cc110x_isr(void)
|
||||
}
|
||||
else if ((P2IFG & 0x02) != 0) {
|
||||
cc110x_gdo0_irq();
|
||||
P2IE &= ~0x02; // Disable interrupt for GDO0
|
||||
P2IFG &= ~0x02; // Clear IFG for GDO0
|
||||
P2IE &= ~0x02; // Disable interrupt for GDO0
|
||||
P2IFG &= ~0x02; // Clear IFG for GDO0
|
||||
}
|
||||
else {
|
||||
puts("cc110x_isr(): unexpected IFG!");
|
||||
/* Should not occur - only Port 2 Pin 0 interrupts are enabled */
|
||||
// CLEAR(P2IFG, 0xFF); /* Clear all flags */
|
||||
// CLEAR(P2IFG, 0xFF); /* Clear all flags */
|
||||
}
|
||||
|
||||
// if (system_state.POWERDOWN != 0) END_LPM3;
|
||||
// if (system_state.POWERDOWN != 0) END_LPM3;
|
||||
__exit_isr();
|
||||
}
|
||||
|
||||
@ -19,9 +19,9 @@ You should have received a copy of the GNU General Public License along with
|
||||
this program. If not, see http://www.gnu.org/licenses/ .
|
||||
--------------------------------------------------------------------------------
|
||||
For further information and questions please use the web site
|
||||
http://scatterweb.mi.fu-berlin.de
|
||||
http://scatterweb.mi.fu-berlin.de
|
||||
and the mailinglist (subscription via web site)
|
||||
scatterweb@lists.spline.inf.fu-berlin.de
|
||||
scatterweb@lists.spline.inf.fu-berlin.de
|
||||
*******************************************************************************/
|
||||
|
||||
/**
|
||||
@ -54,13 +54,13 @@ and the mailinglist (subscription via web site)
|
||||
/* LEDs ports MSB430 */
|
||||
#define LEDS_PxDIR P5DIR
|
||||
#define LEDS_PxOUT P5OUT
|
||||
#define LEDS_CONF_RED 0x80
|
||||
#define LEDS_CONF_GREEN 0x00
|
||||
#define LEDS_CONF_YELLOW 0x00
|
||||
#define LEDS_CONF_RED 0x80
|
||||
#define LEDS_CONF_GREEN 0x00
|
||||
#define LEDS_CONF_YELLOW 0x00
|
||||
|
||||
#define LED_RED_ON LEDS_PxOUT &=~LEDS_CONF_RED
|
||||
#define LED_RED_OFF LEDS_PxOUT |= LEDS_CONF_RED
|
||||
#define LED_RED_TOGGLE LEDS_PxOUT ^= LEDS_CONF_RED
|
||||
#define LED_RED_ON LEDS_PxOUT &=~LEDS_CONF_RED
|
||||
#define LED_RED_OFF LEDS_PxOUT |= LEDS_CONF_RED
|
||||
#define LED_RED_TOGGLE LEDS_PxOUT ^= LEDS_CONF_RED
|
||||
|
||||
#include "board-conf.h"
|
||||
|
||||
|
||||
@ -18,7 +18,7 @@
|
||||
* @author Heiko Will
|
||||
* @author Kaspar Schleiser
|
||||
* @author Michael Baar <baar@inf.fu-berlin.de>
|
||||
* @author Zakaria Kasmi <zkasmi@inf.fu-berlin.de>
|
||||
* @author Zakaria Kasmi <zkasmi@inf.fu-berlin.de>
|
||||
* @note $Id$
|
||||
*/
|
||||
#include <string.h>
|
||||
@ -28,10 +28,10 @@
|
||||
#include "cpu.h"
|
||||
#include "config.h"
|
||||
|
||||
#define PCRTC BIT9
|
||||
#define CL_CPU_DIV 4
|
||||
#define PCRTC BIT9
|
||||
#define CL_CPU_DIV 4
|
||||
|
||||
#define WD_INTERVAL 10 ///< number of seconds before WD triggers
|
||||
#define WD_INTERVAL 10 ///< number of seconds before WD triggers
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/**
|
||||
|
||||
@ -19,40 +19,40 @@ You should have received a copy of the GNU General Public License along with
|
||||
this program. If not, see http://www.gnu.org/licenses/ .
|
||||
--------------------------------------------------------------------------------
|
||||
For further information and questions please use the web site
|
||||
http://scatterweb.mi.fu-berlin.de
|
||||
http://scatterweb.mi.fu-berlin.de
|
||||
and the mailinglist (subscription via web site)
|
||||
scatterweb@lists.spline.inf.fu-berlin.de
|
||||
scatterweb@lists.spline.inf.fu-berlin.de
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef SHT11BOARD_H_
|
||||
#define SHT11BOARD_H_
|
||||
|
||||
/**
|
||||
* @ingroup lpc2387
|
||||
* @ingroup lpc2387
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief LPC2387 SHT11 Device Driver
|
||||
* @brief LPC2387 SHT11 Device Driver
|
||||
*
|
||||
* @author Freie Universität Berlin, Computer Systems & Telematics, FeuerWhere project
|
||||
* @version $Revision$
|
||||
*
|
||||
* @note $Id$
|
||||
* @note $Id$
|
||||
*/
|
||||
|
||||
#include "lpc23xx.h"
|
||||
#include "board.h"
|
||||
|
||||
#define SHT11_SCK_LOW FIO1CLR = BIT25; // serial clock line low
|
||||
#define SHT11_SCK_HIGH FIO1SET = BIT25; // serial clock line high
|
||||
#define SHT11_DATA ((FIO1PIN & BIT26) != 0) // read serial I/O
|
||||
#define SHT11_DATA_LOW (FIO1CLR = BIT26); // serial I/O line low
|
||||
#define SHT11_DATA_HIGH (FIO1SET = BIT26); // serial I/O line high
|
||||
#define SHT11_DATA_IN (FIO1DIR &= ~BIT26) // serial I/O as input
|
||||
#define SHT11_DATA_OUT (FIO1DIR |= BIT26) // serial I/O as output
|
||||
#define SHT11_INIT FIO1DIR |= BIT25; PINSEL3 &= ~(BIT14|BIT15 | BIT16|BIT17);
|
||||
#define SHT11_SCK_LOW FIO1CLR = BIT25; // serial clock line low
|
||||
#define SHT11_SCK_HIGH FIO1SET = BIT25; // serial clock line high
|
||||
#define SHT11_DATA ((FIO1PIN & BIT26) != 0) // read serial I/O
|
||||
#define SHT11_DATA_LOW (FIO1CLR = BIT26); // serial I/O line low
|
||||
#define SHT11_DATA_HIGH (FIO1SET = BIT26); // serial I/O line high
|
||||
#define SHT11_DATA_IN (FIO1DIR &= ~BIT26) // serial I/O as input
|
||||
#define SHT11_DATA_OUT (FIO1DIR |= BIT26) // serial I/O as output
|
||||
#define SHT11_INIT FIO1DIR |= BIT25; PINSEL3 &= ~(BIT14|BIT15 | BIT16|BIT17);
|
||||
|
||||
/** @} */
|
||||
#endif /* SHT11BOARD_H_ */
|
||||
|
||||
@ -7,17 +7,17 @@
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup msba2
|
||||
* @ingroup ltc4150
|
||||
* @ingroup msba2
|
||||
* @ingroup ltc4150
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief LTC4150 MSB-A2 specific implemetation
|
||||
* @brief LTC4150 MSB-A2 specific implemetation
|
||||
*
|
||||
* @author Heiko Will
|
||||
* @author Michael Baar
|
||||
* @author Heiko Will
|
||||
* @author Michael Baar
|
||||
* @author Kaspar Schleiser <kaspar@schleiser.de>
|
||||
*/
|
||||
|
||||
|
||||
@ -26,25 +26,25 @@
|
||||
|
||||
void benchmark_init(void)
|
||||
{
|
||||
PCLKSEL1 = (PCLKSEL1 & ~(BIT14|BIT15)) | (1 << 14); // CCLK to PCLK divider
|
||||
PCONP |= PCTIM3;
|
||||
T3TCR = 0; // disable timer
|
||||
T3MCR = 0; // disable interrupt
|
||||
T3CCR = 0; // capture is disabled.
|
||||
T3EMR = 0; // no external match output.
|
||||
T3PR = 0; // set prescaler
|
||||
T3TC = 0; // reset counter
|
||||
PCLKSEL1 = (PCLKSEL1 & ~(BIT14|BIT15)) | (1 << 14); // CCLK to PCLK divider
|
||||
PCONP |= PCTIM3;
|
||||
T3TCR = 0; // disable timer
|
||||
T3MCR = 0; // disable interrupt
|
||||
T3CCR = 0; // capture is disabled.
|
||||
T3EMR = 0; // no external match output.
|
||||
T3PR = 0; // set prescaler
|
||||
T3TC = 0; // reset counter
|
||||
}
|
||||
|
||||
void benchmark_reset_start(void)
|
||||
{
|
||||
T3TCR = 0; // disable timer
|
||||
T3TC = 0; // reset counter
|
||||
T3TCR = BIT0;
|
||||
T3TCR = 0; // disable timer
|
||||
T3TC = 0; // reset counter
|
||||
T3TCR = BIT0;
|
||||
}
|
||||
|
||||
unsigned int benchmark_read_stop(void)
|
||||
{
|
||||
T3TCR = 0; // disable timer
|
||||
return T3TC;
|
||||
T3TCR = 0; // disable timer
|
||||
return T3TC;
|
||||
}
|
||||
|
||||
@ -112,33 +112,33 @@ struct chip_info_struct chip_info[] = {
|
||||
{"LPC2104 (120k)", "4293984018", 0x40000200, 0x2000, 15, lpc2106_layout, boot_2xxx},
|
||||
{"LPC2105 (120k)", "4293984034", 0x40000200, 0x2000, 15, lpc2106_layout, boot_2xxx},
|
||||
{"LPC2106 (120k)", "4293984050", 0x40000200, 0x2000, 15, lpc2106_layout, boot_2xxx},
|
||||
{"LPC2114 (120k)", "16908050", 0x40000200, 0x2000, 15, lpc2106_layout, boot_2xxx},
|
||||
{"LPC2119 (120k)", "33685266", 0x40000200, 0x2000, 15, lpc2106_layout, boot_2xxx},
|
||||
{"LPC2124 (120k)", "16908051", 0x40000200, 0x2000, 15, lpc2106_layout, boot_2xxx},
|
||||
{"LPC2129 (248k)", "33685267", 0x40000200, 0x2000, 17, lpc2214_layout, boot_2xxx},
|
||||
{"LPC2131 (32k)", "196353", 0x40000200, 0x1000, 8, lpc2138_layout, boot_2xxx},
|
||||
{"LPC2132 (64k)", "196369", 0x40000200, 0x1000, 9, lpc2138_layout, boot_2xxx},
|
||||
{"LPC2134 (128k)", "196370", 0x40000200, 0x1000, 11, lpc2138_layout, boot_2xxx},
|
||||
{"LPC2136 (256k)", "196387", 0x40000200, 0x1000, 15, lpc2138_layout, boot_2xxx},
|
||||
{"LPC2138 (500k)", "196389", 0x40000200, 0x1000, 27, lpc2138_layout, boot_2xxx},
|
||||
{"LPC2141 (32k)", "67305217", 0x40000200, 0x1000, 8, lpc2138_layout, boot_2xxx},
|
||||
{"LPC2142 (64k)", "67305233", 0x40000200, 0x1000, 9, lpc2138_layout, boot_2xxx},
|
||||
{"LPC2144 (128k)", "67305234", 0x40000200, 0x1000, 11, lpc2138_layout, boot_2xxx},
|
||||
{"LPC2146 (256k)", "67305251", 0x40000200, 0x1000, 15, lpc2138_layout, boot_2xxx},
|
||||
{"LPC2148 (500k)", "67305253", 0x40000200, 0x1000, 27, lpc2138_layout, boot_2xxx},
|
||||
{"LPC2194 (248k)", "50462483", 0x40000200, 0x2000, 17, lpc2214_layout, boot_2xxx},
|
||||
{"LPC2212 (248k)", "67239698", 0x40000200, 0x2000, 17, lpc2214_layout, boot_2xxx},
|
||||
{"LPC2214 (248k)", "100794131", 0x40000200, 0x2000, 17, lpc2214_layout, boot_2xxx},
|
||||
{"LPC2292 (248k)", "67239699", 0x40000200, 0x2000, 17, lpc2214_layout, boot_2xxx},
|
||||
{"LPC2294 (248k)", "84016915", 0x40000200, 0x2000, 17, lpc2214_layout, boot_2xxx},
|
||||
{"LPC2103 (32k)", "327441", 0x40000200, 0x1000, 8, lpc2138_layout, boot_2xxx},
|
||||
{"LPC2364 (128k)", "100924162", 0x40000200, 0x1000, 11, lpc2138_layout, boot_23xx},
|
||||
{"LPC2366 (256k)", "100924195", 0x40000200, 0x1000, 15, lpc2138_layout, boot_23xx},
|
||||
{"LPC2368 (500k)", "100924197", 0x40000200, 0x1000, 27, lpc2138_layout, boot_23xx},
|
||||
{"LPC2378 (500k)", "117702437", 0x40000200, 0x1000, 27, lpc2138_layout, boot_23xx},
|
||||
{"LPC2387 (500k)", "402716981", 0x40000200, 0x1000, 27, lpc2138_layout, boot_23xx},
|
||||
{"LPC2387 (500k)", "385941301", 0x40000200, 0x1000, 27, lpc2138_layout, boot_23xx},
|
||||
{"LPC2468 (500k)", "100925237", 0x40000200, 0x1000, 27, lpc2138_layout, boot_23xx},
|
||||
{"LPC2114 (120k)", "16908050", 0x40000200, 0x2000, 15, lpc2106_layout, boot_2xxx},
|
||||
{"LPC2119 (120k)", "33685266", 0x40000200, 0x2000, 15, lpc2106_layout, boot_2xxx},
|
||||
{"LPC2124 (120k)", "16908051", 0x40000200, 0x2000, 15, lpc2106_layout, boot_2xxx},
|
||||
{"LPC2129 (248k)", "33685267", 0x40000200, 0x2000, 17, lpc2214_layout, boot_2xxx},
|
||||
{"LPC2131 (32k)", "196353", 0x40000200, 0x1000, 8, lpc2138_layout, boot_2xxx},
|
||||
{"LPC2132 (64k)", "196369", 0x40000200, 0x1000, 9, lpc2138_layout, boot_2xxx},
|
||||
{"LPC2134 (128k)", "196370", 0x40000200, 0x1000, 11, lpc2138_layout, boot_2xxx},
|
||||
{"LPC2136 (256k)", "196387", 0x40000200, 0x1000, 15, lpc2138_layout, boot_2xxx},
|
||||
{"LPC2138 (500k)", "196389", 0x40000200, 0x1000, 27, lpc2138_layout, boot_2xxx},
|
||||
{"LPC2141 (32k)", "67305217", 0x40000200, 0x1000, 8, lpc2138_layout, boot_2xxx},
|
||||
{"LPC2142 (64k)", "67305233", 0x40000200, 0x1000, 9, lpc2138_layout, boot_2xxx},
|
||||
{"LPC2144 (128k)", "67305234", 0x40000200, 0x1000, 11, lpc2138_layout, boot_2xxx},
|
||||
{"LPC2146 (256k)", "67305251", 0x40000200, 0x1000, 15, lpc2138_layout, boot_2xxx},
|
||||
{"LPC2148 (500k)", "67305253", 0x40000200, 0x1000, 27, lpc2138_layout, boot_2xxx},
|
||||
{"LPC2194 (248k)", "50462483", 0x40000200, 0x2000, 17, lpc2214_layout, boot_2xxx},
|
||||
{"LPC2212 (248k)", "67239698", 0x40000200, 0x2000, 17, lpc2214_layout, boot_2xxx},
|
||||
{"LPC2214 (248k)", "100794131", 0x40000200, 0x2000, 17, lpc2214_layout, boot_2xxx},
|
||||
{"LPC2292 (248k)", "67239699", 0x40000200, 0x2000, 17, lpc2214_layout, boot_2xxx},
|
||||
{"LPC2294 (248k)", "84016915", 0x40000200, 0x2000, 17, lpc2214_layout, boot_2xxx},
|
||||
{"LPC2103 (32k)", "327441", 0x40000200, 0x1000, 8, lpc2138_layout, boot_2xxx},
|
||||
{"LPC2364 (128k)", "100924162", 0x40000200, 0x1000, 11, lpc2138_layout, boot_23xx},
|
||||
{"LPC2366 (256k)", "100924195", 0x40000200, 0x1000, 15, lpc2138_layout, boot_23xx},
|
||||
{"LPC2368 (500k)", "100924197", 0x40000200, 0x1000, 27, lpc2138_layout, boot_23xx},
|
||||
{"LPC2378 (500k)", "117702437", 0x40000200, 0x1000, 27, lpc2138_layout, boot_23xx},
|
||||
{"LPC2387 (500k)", "402716981", 0x40000200, 0x1000, 27, lpc2138_layout, boot_23xx},
|
||||
{"LPC2387 (500k)", "385941301", 0x40000200, 0x1000, 27, lpc2138_layout, boot_23xx},
|
||||
{"LPC2468 (500k)", "100925237", 0x40000200, 0x1000, 27, lpc2138_layout, boot_23xx},
|
||||
{NULL, NULL, 0, 0, 0, NULL}
|
||||
};
|
||||
|
||||
|
||||
@ -1,18 +1,18 @@
|
||||
extern char *lpc_return_strings[];
|
||||
|
||||
struct sector_info_struct { // an array of
|
||||
int address; // where each sector is located
|
||||
int size; // and how big it is
|
||||
struct sector_info_struct { // an array of
|
||||
int address; // where each sector is located
|
||||
int size; // and how big it is
|
||||
};
|
||||
|
||||
struct chip_info_struct {
|
||||
char *part_number; // human readable part number
|
||||
char *id_string; // id string sent by "J" command
|
||||
unsigned int ram_addr; // where to download into RAM
|
||||
int chunk_size; // download to ram chunk size
|
||||
int num_sector; // number of flash sectors
|
||||
char *part_number; // human readable part number
|
||||
char *id_string; // id string sent by "J" command
|
||||
unsigned int ram_addr; // where to download into RAM
|
||||
int chunk_size; // download to ram chunk size
|
||||
int num_sector; // number of flash sectors
|
||||
struct sector_info_struct *layout; // layout of sectors
|
||||
const unsigned int *bootprog; // code that boots into user program (NULL = DTR/RTS only)
|
||||
const unsigned int *bootprog; // code that boots into user program (NULL = DTR/RTS only)
|
||||
};
|
||||
|
||||
extern struct chip_info_struct chip_info[];
|
||||
|
||||
@ -26,33 +26,33 @@
|
||||
|
||||
void hard_reset_to_bootloader(void)
|
||||
{
|
||||
/* Use this lines for flashing a node with interrupted DTR line */
|
||||
/* printf("Press Reset - confirm with anykey\n");
|
||||
/* Use this lines for flashing a node with interrupted DTR line */
|
||||
/* printf("Press Reset - confirm with anykey\n");
|
||||
getchar();
|
||||
*/
|
||||
printf("Reset CPU (into bootloader)\r\n");
|
||||
set_rts(1); // RTS (ttl level) connects to P0.14
|
||||
set_rts(1); // RTS (ttl level) connects to P0.14
|
||||
/* the next two lines should be commented for the prepared node */
|
||||
set_dtr(1); // DTR (ttl level) connects to RST
|
||||
send_break_signal(); // or break detect circuit to RST
|
||||
set_dtr(1); // DTR (ttl level) connects to RST
|
||||
send_break_signal(); // or break detect circuit to RST
|
||||
usleep(75000);
|
||||
/* Use this lines for flashing a node with interrupted DTR line */
|
||||
/* Use this lines for flashing a node with interrupted DTR line */
|
||||
/* printf("Release Reset - confirm with anykey\n");
|
||||
getchar();
|
||||
*/
|
||||
set_dtr(0); // allow the CPU to run:
|
||||
set_dtr(0); // allow the CPU to run:
|
||||
set_baud(baud_rate);
|
||||
set_rts(1); // set RTS again (as it has been reset by set_baudrate)
|
||||
set_rts(1); // set RTS again (as it has been reset by set_baudrate)
|
||||
usleep(40000);
|
||||
}
|
||||
|
||||
void hard_reset_to_user_code(void)
|
||||
{
|
||||
printf("Reset CPU (into user code)\r\n");
|
||||
set_rts(0); // RTS (ttl level) connects to P0.14
|
||||
set_dtr(1); // DTR (ttl level) connects to RST
|
||||
send_break_signal(); // or break detect circuit to RST
|
||||
set_rts(0); // RTS (ttl level) connects to P0.14
|
||||
set_dtr(1); // DTR (ttl level) connects to RST
|
||||
send_break_signal(); // or break detect circuit to RST
|
||||
usleep(75000);
|
||||
set_dtr(0); // allow the CPU to run
|
||||
set_dtr(0); // allow the CPU to run
|
||||
usleep(40000);
|
||||
}
|
||||
|
||||
@ -75,37 +75,37 @@ char *file_name = "";
|
||||
char *crystal = "16";
|
||||
|
||||
/****************************************************************/
|
||||
/* */
|
||||
/* Main Download Section */
|
||||
/* */
|
||||
/* */
|
||||
/* Main Download Section */
|
||||
/* */
|
||||
/****************************************************************/
|
||||
|
||||
// possible states
|
||||
#define SYNC_1 1
|
||||
#define SYNC_2 2
|
||||
#define SYNC_3 3
|
||||
#define CHIP_ID 4
|
||||
#define UNLOCK 5
|
||||
#define BLANK_CHECK_SECTOR 6
|
||||
#define ERASE_PREPARE 7
|
||||
#define ERASE_SECTOR 8
|
||||
#define DOWNLOAD_CODE 9
|
||||
#define XMIT_DATA 10
|
||||
#define XMIT_CKSUM 11
|
||||
#define WRITE_PREPARE 12
|
||||
#define WRITE_SECTOR 13
|
||||
#define BOOT_HARD 14
|
||||
#define BOOT_SOFT 15
|
||||
#define BOOT_XMIT_DATA 16
|
||||
#define BOOT_XMIT_CKSUM 17
|
||||
#define BOOT_RUN_CODE 18
|
||||
#define SYNC_1 1
|
||||
#define SYNC_2 2
|
||||
#define SYNC_3 3
|
||||
#define CHIP_ID 4
|
||||
#define UNLOCK 5
|
||||
#define BLANK_CHECK_SECTOR 6
|
||||
#define ERASE_PREPARE 7
|
||||
#define ERASE_SECTOR 8
|
||||
#define DOWNLOAD_CODE 9
|
||||
#define XMIT_DATA 10
|
||||
#define XMIT_CKSUM 11
|
||||
#define WRITE_PREPARE 12
|
||||
#define WRITE_SECTOR 13
|
||||
#define BOOT_HARD 14
|
||||
#define BOOT_SOFT 15
|
||||
#define BOOT_XMIT_DATA 16
|
||||
#define BOOT_XMIT_CKSUM 17
|
||||
#define BOOT_RUN_CODE 18
|
||||
|
||||
|
||||
// possible input values for "event"
|
||||
#define BEGIN 1
|
||||
#define RESPONSE 2
|
||||
#define TIMEOUT 3
|
||||
#define RETRY 4
|
||||
#define BEGIN 1
|
||||
#define RESPONSE 2
|
||||
#define TIMEOUT 3
|
||||
#define RETRY 4
|
||||
|
||||
|
||||
|
||||
@ -251,9 +251,9 @@ static void download_main(int event)
|
||||
int n;
|
||||
static unsigned int cksum;
|
||||
static int retry = 0;
|
||||
static int sector; // current sector we're doing
|
||||
static int sector; // current sector we're doing
|
||||
static int sector_offset;
|
||||
static struct chip_info_struct *chip; // which chip
|
||||
static struct chip_info_struct *chip; // which chip
|
||||
static int current_addr, num_to_xmit, linecount;
|
||||
|
||||
|
||||
@ -832,16 +832,16 @@ static void download_main(int event)
|
||||
|
||||
|
||||
case BOOT_HARD:
|
||||
// if (chip->bootprog) {
|
||||
// state = BOOT_SOFT;
|
||||
// break;
|
||||
// }
|
||||
// else {
|
||||
// if (chip->bootprog) {
|
||||
// state = BOOT_SOFT;
|
||||
// break;
|
||||
// }
|
||||
// else {
|
||||
printf("Booting (hardware reset)...\r\n\r\n");
|
||||
hard_reset_to_user_code();
|
||||
done_program(0);
|
||||
return;
|
||||
// }
|
||||
// }
|
||||
|
||||
case BOOT_SOFT:
|
||||
switch (event) {
|
||||
@ -1036,9 +1036,9 @@ void download_cancel(const char *mesg)
|
||||
|
||||
|
||||
/****************************************************************/
|
||||
/* */
|
||||
/* Transmit Commands to Bootloader */
|
||||
/* */
|
||||
/* */
|
||||
/* Transmit Commands to Bootloader */
|
||||
/* */
|
||||
/****************************************************************/
|
||||
|
||||
|
||||
@ -1077,9 +1077,9 @@ static void xmit_cmd(const char *cmd, int max_time)
|
||||
|
||||
|
||||
/****************************************************************/
|
||||
/* */
|
||||
/* Handlers that respond to input */
|
||||
/* */
|
||||
/* */
|
||||
/* Handlers that respond to input */
|
||||
/* */
|
||||
/****************************************************************/
|
||||
|
||||
|
||||
|
||||
@ -52,9 +52,9 @@ static int parse_hex_line(char *line);
|
||||
|
||||
|
||||
/****************************************************************/
|
||||
/* */
|
||||
/* Read Intel Hex File */
|
||||
/* */
|
||||
/* */
|
||||
/* Read Intel Hex File */
|
||||
/* */
|
||||
/****************************************************************/
|
||||
|
||||
|
||||
@ -210,7 +210,7 @@ parse_hex_line(char *line)
|
||||
//printf("ext addr = %08X\n", extended_addr);
|
||||
}
|
||||
|
||||
return 1; // non-data line
|
||||
return 1; // non-data line
|
||||
}
|
||||
|
||||
byte_count += len;
|
||||
|
||||
@ -199,7 +199,7 @@ static void report_open_error(const char *filename, int err)
|
||||
}
|
||||
|
||||
/* printf("%s is owned by: user %s, group %s\r\n",
|
||||
filename, file_uname, file_gname); */
|
||||
filename, file_uname, file_gname); */
|
||||
|
||||
perm = info.st_mode;
|
||||
|
||||
|
||||
@ -18,7 +18,7 @@
|
||||
* @author Heiko Will
|
||||
* @author Kaspar Schleiser
|
||||
* @author Michael Baar <baar@inf.fu-berlin.de>
|
||||
* @author Zakaria Kasmi <zkasmi@inf.fu-berlin.de>
|
||||
* @author Zakaria Kasmi <zkasmi@inf.fu-berlin.de>
|
||||
*
|
||||
* @note $Id$
|
||||
*/
|
||||
|
||||
@ -8,14 +8,14 @@
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @ingroup LPC2387
|
||||
* @brief CC1100 LPC2387 dependend functions
|
||||
* @ingroup LPC2387
|
||||
* @brief CC1100 LPC2387 dependend functions
|
||||
*
|
||||
* @author Heiko Will <hwill@inf.fu-berlin.de>
|
||||
* @author Thomas Hillebrandt <hillebra@inf.fu-berlin.de>
|
||||
* @author Heiko Will <hwill@inf.fu-berlin.de>
|
||||
* @author Thomas Hillebrandt <hillebra@inf.fu-berlin.de>
|
||||
* @version $Revision: 1781 $
|
||||
*
|
||||
* @note $Id: msba2-cc110x.c 1781 2010-01-26 13:39:36Z hillebra $
|
||||
* @note $Id: msba2-cc110x.c 1781 2010-01-26 13:39:36Z hillebra $
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
@ -29,16 +29,16 @@
|
||||
|
||||
#include "gpioint.h"
|
||||
|
||||
#define CC1100_GDO0 (FIO0PIN & BIT27) // read serial I/O (GDO0)
|
||||
#define CC1100_GDO1 (FIO1PIN & BIT23) // read serial I/O (GDO1)
|
||||
#define CC1100_GDO2 (FIO0PIN & BIT28) // read serial I/O (GDO2)
|
||||
#define CC1100_GDO0 (FIO0PIN & BIT27) // read serial I/O (GDO0)
|
||||
#define CC1100_GDO1 (FIO1PIN & BIT23) // read serial I/O (GDO1)
|
||||
#define CC1100_GDO2 (FIO0PIN & BIT28) // read serial I/O (GDO2)
|
||||
|
||||
#define SPI_TX_EMPTY (SSP0SR & SSPSR_TFE)
|
||||
#define SPI_BUSY (SSP0SR & SSPSR_BSY)
|
||||
#define SPI_RX_AVAIL (SSP0SR & SSPSR_RNE)
|
||||
#define SPI_TX_EMPTY (SSP0SR & SSPSR_TFE)
|
||||
#define SPI_BUSY (SSP0SR & SSPSR_BSY)
|
||||
#define SPI_RX_AVAIL (SSP0SR & SSPSR_RNE)
|
||||
|
||||
#define CC1100_GDO1_LOW_RETRY (100) // max. retries for GDO1 to go low
|
||||
#define CC1100_GDO1_LOW_COUNT (2700) // loop count (timeout ~ 500 us) to wait
|
||||
#define CC1100_GDO1_LOW_RETRY (100) // max. retries for GDO1 to go low
|
||||
#define CC1100_GDO1_LOW_COUNT (2700) // loop count (timeout ~ 500 us) to wait
|
||||
// for GDO1 to go low when CS low
|
||||
|
||||
//#define DEBUG
|
||||
@ -67,17 +67,17 @@ static int test_time(int code)
|
||||
|
||||
int cc110x_get_gdo0(void)
|
||||
{
|
||||
return CC1100_GDO0;
|
||||
return CC1100_GDO0;
|
||||
}
|
||||
|
||||
int cc110x_get_gdo1(void)
|
||||
{
|
||||
return CC1100_GDO1;
|
||||
return CC1100_GDO1;
|
||||
}
|
||||
|
||||
int cc110x_get_gdo2(void)
|
||||
{
|
||||
return CC1100_GDO2;
|
||||
return CC1100_GDO2;
|
||||
}
|
||||
|
||||
void cc110x_spi_init(void)
|
||||
@ -87,12 +87,12 @@ void cc110x_spi_init(void)
|
||||
FIO1SET = BIT21;
|
||||
|
||||
// Power
|
||||
PCONP |= PCSSP0; // Enable power for SSP0 (default is on)
|
||||
PCONP |= PCSSP0; // Enable power for SSP0 (default is on)
|
||||
|
||||
// PIN Setup
|
||||
PINSEL3 |= BIT8 + BIT9; // Set CLK function to SPI
|
||||
PINSEL3 |= BIT14 + BIT15; // Set MISO function to SPI
|
||||
PINSEL3 |= BIT16 + BIT17; // Set MOSI function to SPI
|
||||
PINSEL3 |= BIT8 + BIT9; // Set CLK function to SPI
|
||||
PINSEL3 |= BIT14 + BIT15; // Set MISO function to SPI
|
||||
PINSEL3 |= BIT16 + BIT17; // Set MOSI function to SPI
|
||||
|
||||
// Interface Setup
|
||||
SSP0CR0 = 7;
|
||||
@ -101,17 +101,17 @@ void cc110x_spi_init(void)
|
||||
uint32_t pclksel;
|
||||
uint32_t cpsr;
|
||||
lpc2387_pclk_scale(F_CPU / 1000, 6000, &pclksel, &cpsr);
|
||||
PCLKSEL1 &= ~(BIT10 | BIT11); // CCLK to PCLK divider
|
||||
PCLKSEL1 &= ~(BIT10 | BIT11); // CCLK to PCLK divider
|
||||
PCLKSEL1 |= pclksel << 10;
|
||||
SSP0CPSR = cpsr;
|
||||
|
||||
// Enable
|
||||
SSP0CR1 |= BIT1; // SSP-Enable
|
||||
SSP0CR1 |= BIT1; // SSP-Enable
|
||||
int dummy;
|
||||
|
||||
// Clear RxFIFO:
|
||||
while (SPI_RX_AVAIL) { // while RNE (Receive FIFO Not Empty)...
|
||||
dummy = SSP0DR; // read data
|
||||
while (SPI_RX_AVAIL) { // while RNE (Receive FIFO Not Empty)...
|
||||
dummy = SSP0DR; // read data
|
||||
}
|
||||
|
||||
/* to suppress unused-but-set-variable */
|
||||
@ -189,8 +189,8 @@ loop:
|
||||
goto final;
|
||||
}
|
||||
|
||||
FIO1SET = BIT21; // CS to high
|
||||
goto cs_low; // try again
|
||||
FIO1SET = BIT21; // CS to high
|
||||
goto cs_low; // try again
|
||||
}
|
||||
|
||||
goto loop;
|
||||
@ -198,7 +198,7 @@ loop:
|
||||
|
||||
final:
|
||||
// Switch to SPI mode
|
||||
PINSEL3 |= (BIT14 + BIT15); // Set MISO function to SPI
|
||||
PINSEL3 |= (BIT14 + BIT15); // Set MISO function to SPI
|
||||
}
|
||||
|
||||
void
|
||||
|
||||
@ -30,35 +30,35 @@
|
||||
/*---------------------------------------------------------------------------*/
|
||||
void init_clks1(void)
|
||||
{
|
||||
// Disconnect PLL
|
||||
PLLCON &= ~0x0002;
|
||||
pllfeed();
|
||||
while (PLLSTAT & BIT25); // wait until PLL is disconnected before disabling - deadlock otherwise
|
||||
// Disconnect PLL
|
||||
PLLCON &= ~0x0002;
|
||||
pllfeed();
|
||||
while (PLLSTAT & BIT25); // wait until PLL is disconnected before disabling - deadlock otherwise
|
||||
|
||||
// Disable PLL
|
||||
PLLCON &= ~0x0001;
|
||||
pllfeed();
|
||||
while (PLLSTAT & BIT24); // wait until PLL is disabled
|
||||
// Disable PLL
|
||||
PLLCON &= ~0x0001;
|
||||
pllfeed();
|
||||
while (PLLSTAT & BIT24); // wait until PLL is disabled
|
||||
|
||||
SCS |= 0x20; // Enable main OSC
|
||||
while( !(SCS & 0x40) ); // Wait until main OSC is usable
|
||||
SCS |= 0x20; // Enable main OSC
|
||||
while( !(SCS & 0x40) ); // Wait until main OSC is usable
|
||||
|
||||
/* select main OSC, 16MHz, as the PLL clock source */
|
||||
CLKSRCSEL = 0x0001;
|
||||
/* select main OSC, 16MHz, as the PLL clock source */
|
||||
CLKSRCSEL = 0x0001;
|
||||
|
||||
// Setting Multiplier and Divider values
|
||||
PLLCFG = 0x0008; // M=9 N=1 Fcco = 288 MHz
|
||||
pllfeed();
|
||||
// Setting Multiplier and Divider values
|
||||
PLLCFG = 0x0008; // M=9 N=1 Fcco = 288 MHz
|
||||
pllfeed();
|
||||
|
||||
// Enabling the PLL */
|
||||
PLLCON = 0x0001;
|
||||
pllfeed();
|
||||
// Enabling the PLL */
|
||||
PLLCON = 0x0001;
|
||||
pllfeed();
|
||||
|
||||
/* Set clock divider to 4 (value+1) */
|
||||
CCLKCFG = CL_CPU_DIV - 1; // Fcpu = 72 MHz
|
||||
/* Set clock divider to 4 (value+1) */
|
||||
CCLKCFG = CL_CPU_DIV - 1; // Fcpu = 72 MHz
|
||||
|
||||
#if USE_USB
|
||||
USBCLKCFG = USBCLKDivValue; /* usbclk = 288 MHz/6 = 48 MHz */
|
||||
USBCLKCFG = USBCLKDivValue; /* usbclk = 288 MHz/6 = 48 MHz */
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
@ -25,9 +25,9 @@
|
||||
|
||||
#define F_CPU (24000000) ///< CPU target speed in Hz
|
||||
|
||||
#define CTUNE 0xb
|
||||
#define IBIAS 0x1f
|
||||
#define FTUNE 0x7
|
||||
#define CTUNE 0xb
|
||||
#define IBIAS 0x1f
|
||||
#define FTUNE 0x7
|
||||
|
||||
typedef uint8_t radio_packet_length_t;
|
||||
|
||||
|
||||
@ -96,12 +96,12 @@ void erase(struct ftdi_context *ftdic, const struct layout *l);
|
||||
void usage(void);
|
||||
|
||||
#define std_layout(x) \
|
||||
.interface = interface(x), \
|
||||
.dir = dir(x), \
|
||||
.reset_release = reset_release(x), \
|
||||
.reset_set = reset_set(x), \
|
||||
.vref2_normal = vref2_normal(x), \
|
||||
.vref2_erase = vref2_erase(x),
|
||||
.interface = interface(x), \
|
||||
.dir = dir(x), \
|
||||
.reset_release = reset_release(x), \
|
||||
.reset_set = reset_set(x), \
|
||||
.vref2_normal = vref2_normal(x), \
|
||||
.vref2_erase = vref2_erase(x),
|
||||
|
||||
static struct layout layouts[] = {
|
||||
{
|
||||
|
||||
@ -40,20 +40,20 @@
|
||||
/* LEDs ports MSB430 */
|
||||
#define LEDS_PxDIR P5DIR
|
||||
#define LEDS_PxOUT P5OUT
|
||||
#define LEDS_CONF_RED 0x10
|
||||
#define LEDS_CONF_GREEN 0x20
|
||||
#define LEDS_CONF_BLUE 0x40
|
||||
#define LEDS_CONF_RED 0x10
|
||||
#define LEDS_CONF_GREEN 0x20
|
||||
#define LEDS_CONF_BLUE 0x40
|
||||
|
||||
#define LED_RED_ON LEDS_PxOUT &=~LEDS_CONF_RED
|
||||
#define LED_RED_OFF LEDS_PxOUT |= LEDS_CONF_RED
|
||||
#define LED_RED_TOGGLE LEDS_PxOUT ^= LEDS_CONF_RED
|
||||
#define LED_RED_ON LEDS_PxOUT &=~LEDS_CONF_RED
|
||||
#define LED_RED_OFF LEDS_PxOUT |= LEDS_CONF_RED
|
||||
#define LED_RED_TOGGLE LEDS_PxOUT ^= LEDS_CONF_RED
|
||||
|
||||
#define LED_GREEN_ON LEDS_PxOUT &=~LEDS_CONF_GREEN
|
||||
#define LED_GREEN_OFF LEDS_PxOUT |= LEDS_CONF_GREEN
|
||||
#define LED_GREEN_TOGGLE LEDS_PxOUT ^= LEDS_CONF_GREEN
|
||||
#define LED_GREEN_ON LEDS_PxOUT &=~LEDS_CONF_GREEN
|
||||
#define LED_GREEN_OFF LEDS_PxOUT |= LEDS_CONF_GREEN
|
||||
#define LED_GREEN_TOGGLE LEDS_PxOUT ^= LEDS_CONF_GREEN
|
||||
|
||||
#define LED_BLUE_ON LEDS_PxOUT &=~LEDS_CONF_BLUE
|
||||
#define LED_BLUE_OFF LEDS_PxOUT |= LEDS_CONF_BLUE
|
||||
#define LED_BLUE_ON LEDS_PxOUT &=~LEDS_CONF_BLUE
|
||||
#define LED_BLUE_OFF LEDS_PxOUT |= LEDS_CONF_BLUE
|
||||
#define LED_BLUE_TOGGLE LEDS_PxOUT ^= LEDS_CONF_BLUE
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
@ -42,20 +42,20 @@
|
||||
/* LEDs ports MSB430 */
|
||||
#define LEDS_PxDIR P5DIR
|
||||
#define LEDS_PxOUT P5OUT
|
||||
#define LEDS_CONF_RED 0x04
|
||||
#define LEDS_CONF_GREEN 0x05
|
||||
#define LEDS_CONF_BLUE 0x06
|
||||
#define LEDS_CONF_RED 0x04
|
||||
#define LEDS_CONF_GREEN 0x05
|
||||
#define LEDS_CONF_BLUE 0x06
|
||||
|
||||
#define LED_RED_ON LEDS_PxOUT &=~LEDS_CONF_RED
|
||||
#define LED_RED_OFF LEDS_PxOUT |= LEDS_CONF_RED
|
||||
#define LED_RED_TOGGLE LEDS_PxOUT ^= LEDS_CONF_RED
|
||||
#define LED_RED_ON LEDS_PxOUT &=~LEDS_CONF_RED
|
||||
#define LED_RED_OFF LEDS_PxOUT |= LEDS_CONF_RED
|
||||
#define LED_RED_TOGGLE LEDS_PxOUT ^= LEDS_CONF_RED
|
||||
|
||||
#define LED_GREEN_ON LEDS_PxOUT &=~LEDS_CONF_GREEN
|
||||
#define LED_GREEN_OFF LEDS_PxOUT |= LEDS_CONF_GREEN
|
||||
#define LED_GREEN_TOGGLE LEDS_PxOUT ^= LEDS_CONF_GREEN
|
||||
#define LED_GREEN_ON LEDS_PxOUT &=~LEDS_CONF_GREEN
|
||||
#define LED_GREEN_OFF LEDS_PxOUT |= LEDS_CONF_GREEN
|
||||
#define LED_GREEN_TOGGLE LEDS_PxOUT ^= LEDS_CONF_GREEN
|
||||
|
||||
#define LED_BLUE_ON LEDS_PxOUT &=~LEDS_CONF_BLUE
|
||||
#define LED_BLUE_OFF LEDS_PxOUT |= LEDS_CONF_BLUE
|
||||
#define LED_BLUE_ON LEDS_PxOUT &=~LEDS_CONF_BLUE
|
||||
#define LED_BLUE_OFF LEDS_PxOUT |= LEDS_CONF_BLUE
|
||||
#define LED_BLUE_TOGGLE LEDS_PxOUT ^= LEDS_CONF_BLUE
|
||||
|
||||
#include <msp430x16x.h>
|
||||
|
||||
@ -42,20 +42,20 @@
|
||||
/* LEDs ports MSB430 */
|
||||
#define LEDS_PxDIR P5DIR
|
||||
#define LEDS_PxOUT P5OUT
|
||||
#define LEDS_CONF_RED 0x04
|
||||
#define LEDS_CONF_GREEN 0x05
|
||||
#define LEDS_CONF_BLUE 0x06
|
||||
#define LEDS_CONF_RED 0x04
|
||||
#define LEDS_CONF_GREEN 0x05
|
||||
#define LEDS_CONF_BLUE 0x06
|
||||
|
||||
#define LED_RED_ON LEDS_PxOUT &=~LEDS_CONF_RED
|
||||
#define LED_RED_OFF LEDS_PxOUT |= LEDS_CONF_RED
|
||||
#define LED_RED_TOGGLE LEDS_PxOUT ^= LEDS_CONF_RED
|
||||
#define LED_RED_ON LEDS_PxOUT &=~LEDS_CONF_RED
|
||||
#define LED_RED_OFF LEDS_PxOUT |= LEDS_CONF_RED
|
||||
#define LED_RED_TOGGLE LEDS_PxOUT ^= LEDS_CONF_RED
|
||||
|
||||
#define LED_GREEN_ON LEDS_PxOUT &=~LEDS_CONF_GREEN
|
||||
#define LED_GREEN_OFF LEDS_PxOUT |= LEDS_CONF_GREEN
|
||||
#define LED_GREEN_TOGGLE LEDS_PxOUT ^= LEDS_CONF_GREEN
|
||||
#define LED_GREEN_ON LEDS_PxOUT &=~LEDS_CONF_GREEN
|
||||
#define LED_GREEN_OFF LEDS_PxOUT |= LEDS_CONF_GREEN
|
||||
#define LED_GREEN_TOGGLE LEDS_PxOUT ^= LEDS_CONF_GREEN
|
||||
|
||||
#define LED_BLUE_ON LEDS_PxOUT &=~LEDS_CONF_BLUE
|
||||
#define LED_BLUE_OFF LEDS_PxOUT |= LEDS_CONF_BLUE
|
||||
#define LED_BLUE_ON LEDS_PxOUT &=~LEDS_CONF_BLUE
|
||||
#define LED_BLUE_OFF LEDS_PxOUT |= LEDS_CONF_BLUE
|
||||
#define LED_BLUE_TOGGLE LEDS_PxOUT ^= LEDS_CONF_BLUE
|
||||
|
||||
#include <msp430x16x.h>
|
||||
|
||||
@ -164,7 +164,7 @@ uint8_t cc2420_txrx(uint8_t data)
|
||||
UCB0TXBUF = data;
|
||||
count = 0;
|
||||
do {
|
||||
count++;
|
||||
count++;
|
||||
if (count >= MAX_SPI_WAIT) {
|
||||
core_panic(0x2420, "cc2420_txrx(): couldn't send byte!");
|
||||
}
|
||||
@ -172,7 +172,7 @@ uint8_t cc2420_txrx(uint8_t data)
|
||||
/* Read the byte that CC2420 has (normally, during TX) returned */
|
||||
count = 0;
|
||||
do {
|
||||
count++;
|
||||
count++;
|
||||
if (count >= MAX_SPI_WAIT) {
|
||||
core_panic(0x2420, "cc2420_txrx(): couldn't receive byte!");
|
||||
}
|
||||
|
||||
@ -123,10 +123,10 @@ interrupt(USCIAB0RX_VECTOR) __attribute__ ((naked)) usart1irq(void)
|
||||
c = UCA0RXBUF;
|
||||
#ifdef MODULE_UART0
|
||||
} else if (uart0_handler_pid) {
|
||||
/* All went well -> let's signal the reception to adequate callbacks */
|
||||
c = UCA0RXBUF;
|
||||
uart0_handle_incoming(c);
|
||||
uart0_notify_thread();
|
||||
/* All went well -> let's signal the reception to adequate callbacks */
|
||||
c = UCA0RXBUF;
|
||||
uart0_handle_incoming(c);
|
||||
uart0_notify_thread();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user