RIOT-OS/RIOT
RIOT-OS/RIOT
1
0
Fork 0
mirror of https://github.com/RIOT-OS/RIOT.git synced 2025-01-17 05:32:45 +01:00
Code Releases Activity

Merge pull request #20713 from dylad/pr/cpu/samd21/avoid_bitfields_reg

Browse Source 
cpu/samd21: avoid the use of bitfield
This commit is contained in:
Teufelchen 2024-06-01 16:10:12 +00:00 committed by GitHub
commit 893fab953b
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
1 changed files with 8 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
cpu/samd21/cpu.c
View File

@ -130,10 +130,8 @@ static void clk_init(void)
#if CLOCK_8MHZ
/* configure internal 8MHz oscillator to run without prescaler */
SYSCTRL->OSC8M.bit.PRESC = 0;
SYSCTRL->OSC8M.bit.ONDEMAND = 1;
SYSCTRL->OSC8M.bit.RUNSTDBY = 0;
SYSCTRL->OSC8M.bit.ENABLE = 1;
SYSCTRL->OSC8M.reg &= ~(SYSCTRL_OSC8M_PRESC_Msk);
SYSCTRL->OSC8M.reg |= (SYSCTRL_OSC8M_ONDEMAND | SYSCTRL_OSC8M_ENABLE);
while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_OSC8MRDY)) {}
#endif
@ -144,7 +142,7 @@ static void clk_init(void)
SYSCTRL_XOSC32K_STARTUP(XOSC32_STARTUP_TIME) |
SYSCTRL_XOSC32K_RUNSTDBY;
/* Enable XOSC32 with Separate Call */
SYSCTRL->XOSC32K.bit.ENABLE = 1;
SYSCTRL->XOSC32K.reg |= SYSCTRL_XOSC32K_ENABLE;
#endif
/* reset the GCLK module so it is in a known state */
@ -202,7 +200,7 @@ static void clk_init(void)
while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
/* Disable ONDEMAND mode while writing configurations */
SYSCTRL->DFLLCTRL.bit.ONDEMAND = 0;
SYSCTRL->DFLLCTRL.reg &= ~(SYSCTRL_DFLLCTRL_ONDEMAND);
while ((SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0) {
/* Wait for DFLL sync */
}
@ -221,7 +219,7 @@ static void clk_init(void)
/* Wait for DFLL sync */
}
SYSCTRL->DFLLCTRL.bit.ENABLE = 1;
SYSCTRL->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_ENABLE;
uint32_t mask = SYSCTRL_PCLKSR_DFLLRDY |
SYSCTRL_PCLKSR_DFLLLCKF |
SYSCTRL_PCLKSR_DFLLLCKC;
@ -237,7 +235,7 @@ static void clk_init(void)
| GCLK_CLKCTRL_GEN(SAM0_GCLK_MAIN);
while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
SYSCTRL->DFLLCTRL.bit.ONDEMAND = 1;
SYSCTRL->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_ONDEMAND;
while ((SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0) {
/* Wait for DFLL sync */
}
@ -265,14 +263,14 @@ static void clk_init(void)
/* redirect all peripherals to a disabled clock generator (7) by default */
for (unsigned i = 0x3; i <= GCLK_CLKCTRL_ID_Msk; i++) {
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(i) | GCLK_CLKCTRL_GEN(SAM0_GCLK_DISABLED);
while (GCLK->STATUS.bit.SYNCBUSY) {}
while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
}
}
void cpu_init(void)
{
/* disable the watchdog timer */
WDT->CTRL.bit.ENABLE = 0;
WDT->CTRL.reg = 0;
/* initialize the Cortex-M core */
cortexm_init();
/* Initialise clock sources and generic clocks */