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Code Releases Activity

cpu/native: defer yield when IRQs are disabled.

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This makes native behave like Cortex-M, which flags PENDSV, which then
gets triggered once IRQs are re-enabled.
This commit is contained in:
Kaspar Schleiser 2021-08-18 12:08:22 +02:00
parent b062ce8660
commit 87b49d04ab
2 changed files with 6 additions and 4 deletions
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5
cpu/native/irq_cpu.c
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@ -201,6 +201,11 @@ unsigned irq_enable(void)
_native_syscall_leave(); _native_syscall_leave();
if (_native_in_isr == 0 && sched_context_switch_request) {
DEBUG("irq_enable() deferred thread_yield_higher()\n");
thread_yield_higher();
}
DEBUG("irq_enable(): return\n"); DEBUG("irq_enable(): return\n");
return prev_state; return prev_state;

5
cpu/native/native_cpu.c
View File

@ -210,12 +210,9 @@ void thread_yield_higher(void)
{ {
sched_context_switch_request = 1; sched_context_switch_request = 1;
if (_native_in_isr == 0) { if (_native_in_isr == 0 && native_interrupts_enabled) {
ucontext_t *ctx = (ucontext_t *)(thread_get_active()->sp); ucontext_t *ctx = (ucontext_t *)(thread_get_active()->sp);
_native_in_isr = 1; _native_in_isr = 1;
if (!native_interrupts_enabled) {
warnx("thread_yield_higher: interrupts are disabled - this should not be");
}
irq_disable(); irq_disable();
native_isr_context.uc_stack.ss_sp = __isr_stack; native_isr_context.uc_stack.ss_sp = __isr_stack;
native_isr_context.uc_stack.ss_size = SIGSTKSZ; native_isr_context.uc_stack.ss_size = SIGSTKSZ;