cpu: adapt to COREIF_NG removal

cpu/atmega1281/Makefile.include

@@ -1,6 +1,3 @@
-# this CPU implementation is using the new core/CPU interface
-export CFLAGS += -DCOREIF_NG=1
-
 # tell the build system that the CPU depends on the atmega common files
 USEMODULE += atmega_common
 

cpu/atmega2560/Makefile.include

@@ -1,6 +1,3 @@
-# this CPU implementation is using the new core/CPU interface
-export CFLAGS += -DCOREIF_NG=1
-
 # tell the build system that the CPU depends on the atmega common files
 USEMODULE += atmega_common
 

cpu/atmega328p/Makefile.include

@@ -1,6 +1,3 @@
-# this CPU implementation is using the new core/CPU interface
-export CFLAGS += -DCOREIF_NG=1
-
 # tell the build system that the CPU depends on the atmega common files
 USEMODULE += atmega_common
 

cpu/atmega_common/irq_arch.c

@@ -21,7 +21,7 @@
 
 #include <stdint.h>
 #include <stdio.h>
-#include "arch/irq_arch.h"
+#include "irq.h"
 #include "cpu.h"
 
 /**
@@ -58,7 +58,7 @@ __attribute__((always_inline)) inline void __set_interrupt_state(uint8_t state)
 /**
  * @brief Disable all maskable interrupts
  */
-unsigned int irq_arch_disable(void)
+unsigned int irq_disable(void)
 {
     uint8_t mask = __get_interrupt_state();
     cli();
@@ -68,7 +68,7 @@ unsigned int irq_arch_disable(void)
 /**
  * @brief Enable all maskable interrupts
  */
-unsigned int irq_arch_enable(void)
+unsigned int irq_enable(void)
 {
     sei();
     return __get_interrupt_state();
@@ -77,7 +77,7 @@ unsigned int irq_arch_enable(void)
 /**
  * @brief Restore the state of the IRQ flags
  */
-void irq_arch_restore(unsigned int state)
+void irq_restore(unsigned int state)
 {
     __set_interrupt_state(state);
 }
@@ -85,7 +85,7 @@ void irq_arch_restore(unsigned int state)
 /**
  * @brief See if the current context is inside an ISR
  */
-int irq_arch_in(void)
+int irq_is_in(void)
 {
     return __in_isr;
 }

cpu/atmega_common/thread_arch.c

@@ -20,7 +20,6 @@
 
 #include <stdio.h>
 
-#include "arch/thread_arch.h"
 #include "thread.h"
 #include "sched.h"
 #include "irq.h"
@@ -64,7 +63,7 @@ static void __enter_thread_mode(void);
  * @brief Since AVR doesn't support direct manipulation of the program counter we
  * model a stack like it would be left by __context_save().
  * The resulting layout in memory is the following:
- * ---------------thread_t (not created by thread_arch_stack_init) ----------
+ * ---------------thread_t (not created by thread_stack_init) ----------
  * local variables (a temporary value and the stackpointer)
  * -----------------------------------------------------------------------
  * a marker (AFFE) - for debugging purposes (helps finding the stack
@@ -92,7 +91,7 @@ static void __enter_thread_mode(void);
  * it inside of the programm counter of the MCU.
  * if task_func returns sched_task_exit gets popped into the PC
  */
-char *thread_arch_stack_init(thread_task_func_t task_func, void *arg,
+char *thread_stack_init(thread_task_func_t task_func, void *arg,
                              void *stack_start, int stack_size)
 {
     uint16_t tmp_adress;
@@ -193,14 +192,14 @@ char *thread_arch_stack_init(thread_task_func_t task_func, void *arg,
 }
 
 /**
- * @brief thread_arch_stack_print prints the stack to stdout.
+ * @brief thread_stack_print prints the stack to stdout.
  * It depends on getting the correct values for stack_start, stack_size and sp
  * from sched_active_thread.
  * Maybe it would be good to change that to way that is less dependant on
  * getting correct values elsewhere (since it is a debugging tool and in the
  * presence of bugs the data may be corrupted).
  */
-void thread_arch_stack_print(void)
+void thread_stack_print(void)
 {
     uint8_t  found_marker = 1;
     uint8_t *sp = (uint8_t *)sched_active_thread->sp;
@@ -223,8 +222,8 @@ void thread_arch_stack_print(void)
     printf("stack size: %u bytes\n", size);
 }
 
-void thread_arch_start_threading(void) __attribute__((naked));
+void thread_start_threading(void) __attribute__((naked));
-void thread_arch_start_threading(void)
+void thread_start_threading(void)
 {
     sched_run();
     AVR_CONTEXT_SWAP_INIT;
@@ -245,7 +244,7 @@ void NORETURN __enter_thread_mode(void)
     UNREACHABLE();
 }
 
-void thread_arch_yield(void) {
+void thread_yield_higher(void) {
     AVR_CONTEXT_SWAP_TRIGGER;
 }
 

cpu/cortexm_common/irq_arch.c

@@ -19,13 +19,13 @@
  */
 
 #include <stdint.h>
-#include "arch/irq_arch.h"
+#include "irq.h"
 #include "cpu.h"
 
 /**
  * @brief Disable all maskable interrupts
  */
-unsigned int irq_arch_disable(void)
+unsigned int irq_disable(void)
 {
     uint32_t mask = __get_PRIMASK();
     __disable_irq();
@@ -35,7 +35,7 @@ unsigned int irq_arch_disable(void)
 /**
  * @brief Enable all maskable interrupts
  */
-__attribute__((used)) unsigned int irq_arch_enable(void)
+__attribute__((used)) unsigned int irq_enable(void)
 {
     __enable_irq();
     return __get_PRIMASK();
@@ -44,7 +44,7 @@ __attribute__((used)) unsigned int irq_arch_enable(void)
 /**
  * @brief Restore the state of the IRQ flags
  */
-void irq_arch_restore(unsigned int state)
+void irq_restore(unsigned int state)
 {
     __set_PRIMASK(state);
 }
@@ -52,7 +52,7 @@ void irq_arch_restore(unsigned int state)
 /**
  * @brief See if the current context is inside an ISR
  */
-int irq_arch_in(void)
+int irq_is_in(void)
 {
     return (__get_IPSR() & 0xFF);
 }

cpu/cortexm_common/thread_arch.c

@@ -94,7 +94,6 @@
 
 #include <stdio.h>
 
-#include "arch/thread_arch.h"
 #include "sched.h"
 #include "thread.h"
 #include "irq.h"
@@ -106,7 +105,7 @@ extern uint32_t _sstack;
 /**
  * @brief   Noticeable marker marking the beginning of a stack segment
  *
- * This marker is used e.g. by *thread_arch_start_threading* to identify the
+ * This marker is used e.g. by *thread_start_threading* to identify the
  * stacks beginning.
  */
 #define STACK_MARKER                (0x77777777)
@@ -124,7 +123,7 @@ extern uint32_t _sstack;
  */
 #define EXCEPT_RET_TASK_MODE        (0xfffffffd)
 
-char *thread_arch_stack_init(thread_task_func_t task_func,
+char *thread_stack_init(thread_task_func_t task_func,
                              void *arg,
                              void *stack_start,
                              int stack_size)
@@ -236,7 +235,7 @@ char *thread_arch_stack_init(thread_task_func_t task_func,
     return (char*) stk;
 }
 
-void thread_arch_stack_print(void)
+void thread_stack_print(void)
 {
     int count = 0;
     uint32_t *sp = (uint32_t *)sched_active_thread->sp;
@@ -255,7 +254,7 @@ void thread_arch_stack_print(void)
 }
 
 /* This function returns the number of bytes used on the ISR stack */
-int thread_arch_isr_stack_usage(void)
+int thread_isr_stack_usage(void)
 {
     uint32_t *ptr = &_sstack;
 
@@ -267,21 +266,21 @@ int thread_arch_isr_stack_usage(void)
     return num_used_words * sizeof(*ptr);
 }
 
-void *thread_arch_isr_stack_pointer(void)
+void *thread_isr_stack_pointer(void)
 {
     void *msp = (void *)__get_MSP();
     return msp;
 }
 
-void *thread_arch_isr_stack_start(void)
+void *thread_isr_stack_start(void)
 {
     return (void *)&_sstack;
 }
 
-__attribute__((naked)) void NORETURN thread_arch_start_threading(void)
+__attribute__((naked)) void NORETURN thread_start_threading(void)
 {
     __asm__ volatile (
-    "bl     irq_arch_enable               \n" /* enable IRQs to make the SVC
+    "bl     irq_enable               \n" /* enable IRQs to make the SVC
                                            * interrupt is reachable */
     "svc    #1                            \n" /* trigger the SVC interrupt */
     "unreachable%=:                       \n" /* this loop is unreachable */
@@ -289,7 +288,7 @@ __attribute__((naked)) void NORETURN thread_arch_start_threading(void)
     :::);
 }
 
-void thread_arch_yield(void)
+void thread_yield_higher(void)
 {
     /* trigger the PENDSV interrupt to run scheduler and schedule new thread if
      * applicable */

cpu/lm4f120/cpu.c

@@ -21,8 +21,7 @@
 #include "irq.h"
 #include "sched.h"
 #include "thread.h"
-#include "arch/thread_arch.h"
+#include "irq.h"
-#include "arch/irq_arch.h"
 #include "periph/init.h"
 #include "periph_conf.h"
 

cpu/mips32r2_common/cpu.c

@@ -15,7 +15,7 @@
 
 #include "periph/uart.h"
 #include "periph/timer.h"
-#include "arch/panic_arch.h"
+#include "panic.h"
 #include "kernel_init.h"
 #include "cpu.h"
 #include "board.h"

cpu/mips32r2_common/irq_arch.c

@@ -7,10 +7,10 @@
  */
 
 #include <mips/m32c0.h>
-#include "arch/irq_arch.h"
+#include "irq.h"
 
 
-unsigned int irq_arch_enable(void)
+unsigned int irq_enable(void)
 {
     unsigned int status;
 
@@ -18,7 +18,7 @@ unsigned int irq_arch_enable(void)
     return status;
 }
 
-unsigned int irq_arch_disable(void)
+unsigned int irq_disable(void)
 {
     unsigned int status;
 
@@ -26,7 +26,7 @@ unsigned int irq_arch_disable(void)
     return status;
 }
 
-void irq_arch_restore(unsigned int state)
+void irq_restore(unsigned int state)
 {
     if (state & SR_IE) {
         mips32_bs_c0(C0_STATUS, SR_IE);
@@ -36,7 +36,7 @@ void irq_arch_restore(unsigned int state)
     }
 }
 
-int irq_arch_in(void)
+int irq_is_in(void)
 {
     return (mips32_get_c0(C0_STATUS) & SR_EXL) != 0;
 }

cpu/mips32r2_common/periph/timer.c

@@ -126,9 +126,9 @@ int timer_set(tim_t dev, int channel, unsigned int timeout)
     timeout >>= TIMER_ACCURACY_SHIFT;
     timeout <<= TIMER_ACCURACY_SHIFT;
 
-    uint32_t status = irq_arch_disable();
+    uint32_t status = irq_disable();
     compares[channel] = counter + timeout;
-    irq_arch_restore(status);
+    irq_restore(status);
 
     return channel;
 }
@@ -141,9 +141,9 @@ int timer_set_absolute(tim_t dev, int channel, unsigned int value)
     value >>= TIMER_ACCURACY_SHIFT;
     value <<= TIMER_ACCURACY_SHIFT;
 
-    uint32_t status = irq_arch_disable();
+    uint32_t status = irq_disable();
     compares[channel] = value;
-    irq_arch_restore(status);
+    irq_restore(status);
 
     return channel;
 }
@@ -153,9 +153,9 @@ int timer_clear(tim_t dev, int channel)
     assert(dev == 0);
     assert(channel < CHANNELS);
 
-    uint32_t status = irq_arch_disable();
+    uint32_t status = irq_disable();
     compares[channel] = 0;
-    irq_arch_restore(status);
+    irq_restore(status);
 
     return channel;
 }
@@ -225,9 +225,9 @@ void __attribute__ ((interrupt("vector=hw5"))) _mips_isr_hw5(void)
 #ifdef EIC_IRQ
         eic_irq_ack(EIC_IRQ_TIMER);
 #endif
-        uint32_t status = irq_arch_disable();
+        uint32_t status = irq_disable();
         counter += TIMER_ACCURACY;
-        irq_arch_restore(status);
+        irq_restore(status);
 
         if (counter == compares[0]) {
             /*

cpu/mips32r2_common/thread_arch.c

@@ -60,7 +60,7 @@ static struct fp64ctx *oldfpctx;       /* fpu context of last task that executed
  *     ---------------   <--- sched_active_thread->sp
  */
 
-char *thread_arch_stack_init(thread_task_func_t task_func, void *arg,
+char *thread_stack_init(thread_task_func_t task_func, void *arg,
                              void *stack_start, int stack_size)
 {
     /* make sure it is aligned to 8 bytes this is a requirement of the O32 ABI */
@@ -106,7 +106,7 @@ char *thread_arch_stack_init(thread_task_func_t task_func, void *arg,
     return (void *)p;
 }
 
-void thread_arch_stack_print(void)
+void thread_stack_print(void)
 {
     uintptr_t *sp = (void *)sched_active_thread->sp;
 
@@ -118,7 +118,7 @@ void thread_arch_stack_print(void)
 }
 
 extern void __exception_restore(void);
-void thread_arch_start_threading(void)
+void thread_start_threading(void)
 {
     unsigned int status = mips32_get_c0(C0_STATUS);
 
@@ -140,7 +140,7 @@ void thread_arch_start_threading(void)
     UNREACHABLE();
 }
 
-void thread_arch_yield(void)
+void thread_yield_higher(void)
 {
     /*
      * throw a syscall exception to get into exception level
@@ -217,11 +217,11 @@ _mips_handle_exception(struct gpctx *ctx, int exception)
             if (syscall_num == __MIPS_UHI_SYSCALL_NUM) {
                 if (ctx->t2[1] == __MIPS_UHI_WRITE &&
                     (ctx->a[0] == STDOUT_FILENO || ctx->a[0] == STDERR_FILENO)) {
-                    uint32_t status = irq_arch_disable();
+                    uint32_t status = irq_disable();
                     uart_write(DEBUG_VIA_UART, (uint8_t *)ctx->a[1], ctx->a[2]);
                     ctx->v[0] = ctx->a[2];
                     ctx->epc += 4; /* move PC past the syscall */
-                    irq_arch_restore(status);
+                    irq_restore(status);
                     return;
                 }
                 else if (ctx->t2[1] == __MIPS_UHI_FSTAT &&

cpu/msp430_common/cpu.c

@@ -34,19 +34,19 @@ __attribute__((naked)) void thread_yield_higher(void)
 }
 
 /* This function calculates the ISR_usage */
-int thread_arch_isr_stack_usage(void)
+int thread_isr_stack_usage(void)
 {
     /* TODO */
     return -1;
 }
 
-void *thread_arch_isr_stack_pointer(void)
+void *thread_isr_stack_pointer(void)
 {
     /* TODO */
     return (void *)-1;
 }
 
-void *thread_arch_isr_stack_start(void)
+void *thread_isr_stack_start(void)
 {
     /* TODO */
     return (void *)-1;

cpu/native/irq_cpu.c

@@ -61,12 +61,12 @@ int _sig_pipefd[2];
 static _native_callback_t native_irq_handlers[255];
 char sigalt_stk[SIGSTKSZ];
 
-void *thread_arch_isr_stack_pointer(void)
+void *thread_isr_stack_pointer(void)
 {
     return native_isr_context.uc_stack.ss_sp;
 }
 
-void *thread_arch_isr_stack_start(void)
+void *thread_isr_stack_start(void)
 {
     return __isr_stack;
 }

cpu/native/native_cpu.c

@@ -97,7 +97,7 @@ void thread_print_stack(void)
 }
 
 /* This function calculates the ISR_usage */
-int thread_arch_isr_stack_usage(void)
+int thread_isr_stack_usage(void)
 {
     /* TODO */
     return -1;

cpu/nrf52/vectors.c

@@ -59,10 +59,10 @@ WEAK_DEFAULT void isr_swi0(void);
  * the softdevice ISRs leads to a crash. This workaround
  * uses swi0 as trampoline.
  */
-extern void thread_arch_yield(void);
+extern void thread_yield_higher(void);
 void isr_swi0(void)
 {
-    thread_arch_yield();
+    thread_yield_higher();
 }
 #endif
 

makefiles/arch/cortexm.inc.mk

@@ -22,9 +22,6 @@ export LINKFLAGS += -T$(LINKER_SCRIPT) -Wl,--fatal-warnings
 export LINKFLAGS += $(CFLAGS_CPU) $(CFLAGS_DBG) $(CFLAGS_OPT) -static -lgcc -nostartfiles
 export LINKFLAGS += -Wl,--gc-sections
 
-# This CPU implementation is using the new core/CPU interface:
-export CFLAGS += -DCOREIF_NG=1
-
 # Tell the build system that the CPU depends on the Cortex-M common files:
 export USEMODULE += cortexm_common
 # Export the peripheral drivers to be linked into the final binary:

makefiles/arch/mips.inc.mk

@@ -64,6 +64,3 @@ export LINKFLAGS += $(MIPS_HAL_LDFLAGS)
 export LINKFLAGS += -L$(RIOTCPU)/$(CPU)/ldscripts
 export LINKFLAGS += $(CFLAGS_CPU) $(CFLAGS_DBG) $(CFLAGS_OPT)
 export LINKFLAGS += -Wl,--gc-sections
-
-# This CPU implementation is using the new core/CPU interface:
-export CFLAGS += -DCOREIF_NG=1