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cpu/sam0_common/periph/sdhc: always use 25 MHz
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@ -95,6 +95,7 @@ typedef struct {
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/** This SD stack uses the maximum block size authorized (512 bytes) */
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#define SD_MMC_BLOCK_SIZE 512 /**< SD card block size */
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#define SDHC_SLOW_CLOCK_HZ 400000 /**< Clock frequency on init */
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#define SDHC_FAST_CLOCK_HZ 25000000 /**< Clock frequency after init */
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/**
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* @brief Initialize the SD host controller
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@ -103,12 +103,6 @@ static bool _init_transfer(sdhc_state_t *state, uint32_t cmd, uint32_t arg, uint
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uint16_t num_blocks);
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static bool sdio_test_type(sdhc_state_t *state);
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/** SD/MMC transfer rate unit codes (10K) list */
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static const uint32_t transfer_units[] = { 10, 100, 1000, 10000, 0, 0, 0, 0 };
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/** SD transfer multiplier factor codes (1/10) list */
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static const uint8_t transfer_multiplier[16] =
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{ 0, 10, 12, 13, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80 };
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static bool _card_detect(sdhc_state_t *state)
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{
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return state->dev->PSR.bit.CARDINS;
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@ -369,6 +363,9 @@ int sdhc_init(sdhc_state_t *state)
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goto out;
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}
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/* all SD Cards should support this clock at that point */
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state->clock = SDHC_FAST_CLOCK_HZ;
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/* update the host controller to the detected changes in bus_width and clock */
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_set_hc(state);
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@ -567,7 +564,6 @@ static bool _test_capacity(sdhc_state_t *state)
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{
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alignas(uint32_t)
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uint8_t csd[CSD_REG_BSIZE];
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uint32_t transfer_speed;
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if (!sdhc_send_cmd(state, SDMMC_MCI_CMD9_SEND_CSD, (uint32_t)state->rca << 16)) {
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return false;
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@ -576,9 +572,7 @@ static bool _test_capacity(sdhc_state_t *state)
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uint32_t *csd32 = (void *)csd;
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csd32[i] = __builtin_bswap32(SDHC_DEV->RR[3 - i].reg);
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}
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transfer_speed = CSD_TRAN_SPEED(&csd[1]);
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state->clock = transfer_units[transfer_speed & 0x7] *
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transfer_multiplier[(transfer_speed >> 3) & 0xF] * 1000;
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/*
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* Card Capacity.
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* ----------------------------------------------------
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