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cpu/stm32: fixed lfclk functions for L0 and L1

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This commit is contained in:
Hauke Petersen 2017-08-23 14:57:58 +02:00
parent 7ea8c7f768
commit 82485cf7c6
2 changed files with 17 additions and 16 deletions
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17
cpu/stm32_common/stmclk_common.c
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@ -37,6 +37,16 @@
#define BIT_APB_PWREN RCC_APB1ENR_PWREN
#endif
#if defined (CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
#define REG_LSE CSR
#define BIT_LSEON RCC_CSR_LSEON
#define BIT_LSERDY RCC_CSR_LSERDY
#else
#define REG_LSE BDCR
#define BIT_LSEON RCC_BDCR_LSEON
#define BIT_LSERDY RCC_BDCR_LSERDY
#endif
void stmclk_enable_hsi(void)
{
RCC->CR |= RCC_CR_HSION;
@ -58,8 +68,8 @@ void stmclk_enable_lfclk(void)
{
#if CLOCK_LSE
stmclk_dbp_unlock();
RCC->BDCR |= RCC_BDCR_LSEON;
while (!(RCC->BDCR & RCC_BDCR_LSERDY)) {}
RCC->REG_LSE |= BIT_LSEON;
while (!(RCC->REG_LSE & BIT_LSERDY)) {}
stmclk_dbp_lock();
#else
RCC->CSR |= RCC_CSR_LSION;
@ -71,7 +81,8 @@ void stmclk_disable_lfclk(void)
{
#if CLOCK_LSE
stmclk_dbp_unlock();
RCC->BDCR &= ~(RCC_BDCR_LSEON);
RCC->REG_LSE &= ~(BIT_LSEON);
while (!(RCC->REG_LSE & BIT_LSERDY)) {}
stmclk_dbp_lock();
#else
RCC->CSR &= ~(RCC_CSR_LSION);

16
cpu/stm32l4/cpu.c
View File

@ -21,6 +21,7 @@
#include <stdint.h>
#include "cpu.h"
#include "irq.h"
#include "stmclk.h"
#include "periph_conf.h"
#include "periph/init.h"
@ -125,22 +126,11 @@ static void cpu_clock_init(void)
/* configure the low speed clock domain (LSE vs LSI) */
#if CLOCK_LSE
/* allow write access to backup domain */
periph_clk_en(APB1, RCC_APB1ENR1_PWREN);
PWR->CR1 |= PWR_CR1_DBP;
/* enable LSE */
RCC->BDCR = RCC_BDCR_LSEON;
while (!(RCC->BDCR & RCC_BDCR_LSERDY)) {}
/* disable write access to back domain when done */
PWR->CR1 &= ~(PWR_CR1_DBP);
periph_clk_dis(APB1, RCC_APB1ENR1_PWREN);
/* we enable the LSE clock if available for calibrating the MSI clock */
stmclk_enable_lfclk();
/* now we can enable the MSI PLL mode */
RCC->CR |= RCC_CR_MSIPLLEN;
while (!(RCC->CR & RCC_CR_MSIRDY)) {}
#else
RCC->CSR = RCC_CSR_LSION;
while (!(RCC->CSR & RCC_CSR_LSIRDY)) {}
#endif
/* select the MSI clock for the 48MHz clock tree (USB, RNG) */