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https://github.com/RIOT-OS/RIOT.git
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Merge pull request #14896 from aabadie/pr/boards/hifive_clock_cleanup
boards/hifive*: improve clock configuration and initialization
This commit is contained in:
Leandro Lanzieri
GitHub
commit
7d680046c6
@ -33,22 +33,22 @@ extern "C" {
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#ifndef CONFIG_USE_CLOCK_HFXOSC_PLL
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#if IS_ACTIVE(CONFIG_USE_CLOCK_HFXOSC) || IS_ACTIVE(CONFIG_USE_CLOCK_HFROSC_PLL) || \
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IS_ACTIVE(CONFIG_USE_CLOCK_HFROSC)
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#define CONFIG_USE_CLOCK_HFXOSC_PLL (0)
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#define CONFIG_USE_CLOCK_HFXOSC_PLL 0
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#else
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#define CONFIG_USE_CLOCK_HFXOSC_PLL (1) /* Use PLL clocked by HFXOSC by default */
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#define CONFIG_USE_CLOCK_HFXOSC_PLL 1 /* Use PLL clocked by HFXOSC by default */
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#endif
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#endif /* CONFIG_USE_CLOCK_HFXOSC_PLL */
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#ifndef CONFIG_USE_CLOCK_HFXOSC
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#define CONFIG_USE_CLOCK_HFXOSC (0)
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#define CONFIG_USE_CLOCK_HFXOSC 0
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#endif /* CONFIG_USE_CLOCK_HFXOSC */
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#ifndef CONFIG_USE_CLOCK_HFROSC_PLL
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#define CONFIG_USE_CLOCK_HFROSC_PLL (0)
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#define CONFIG_USE_CLOCK_HFROSC_PLL 0
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#endif /* CONFIG_USE_CLOCK_HFROSC_PLL */
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#ifndef CONFIG_USE_CLOCK_HFROSC
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#define CONFIG_USE_CLOCK_HFROSC (0)
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#define CONFIG_USE_CLOCK_HFROSC 0
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#endif /* CONFIG_USE_CLOCK_HFROSC */
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#if CONFIG_USE_CLOCK_HFXOSC_PLL && \
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@ -71,7 +71,6 @@ extern "C" {
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#error "Cannot use HFROSC with other clock configurations"
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#endif
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#if CONFIG_USE_CLOCK_HFXOSC_PLL
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#define CONFIG_CLOCK_PLL_R (1) /* Divide input clock by 2, mandatory with HFXOSC */
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#ifndef CONFIG_CLOCK_PLL_F
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#define CONFIG_CLOCK_PLL_F (39) /* Multiply REFR by 80, e.g 2 * (39 + 1) */
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@ -79,46 +78,43 @@ extern "C" {
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#ifndef CONFIG_CLOCK_PLL_Q
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#define CONFIG_CLOCK_PLL_Q (1) /* Divide VCO by 2, e.g 2^1 */
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#endif
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#define CLOCK_PLL_INPUT_CLOCK (16000000UL)
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#if CONFIG_USE_CLOCK_HFXOSC_PLL
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#define CLOCK_PLL_INPUT_CLOCK MHZ(16)
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#define CLOCK_PLL_REFR (CLOCK_PLL_INPUT_CLOCK / (CONFIG_CLOCK_PLL_R + 1))
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#define CLOCK_PLL_VCO (CLOCK_PLL_REFR * (2 * (CONFIG_CLOCK_PLL_F + 1)))
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#define CLOCK_PLL_OUT (CLOCK_PLL_VCO / (1 << CONFIG_CLOCK_PLL_Q))
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#define CLOCK_CORECLOCK (CLOCK_PLL_OUT) /* 320000000Hz with the values used above */
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/* Check PLL settings */
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#if CLOCK_PLL_REFR != 8000000
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#if CLOCK_PLL_REFR != MHZ(8)
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#error "Only R=2 can be used when using HFXOSC"
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#endif
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#if (CLOCK_PLL_VCO < 384000000) || (CLOCK_PLL_VCO > 768000000)
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#if (CLOCK_PLL_VCO < MHZ(384)) || (CLOCK_PLL_VCO > MHZ(768))
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#error "VCO frequency must be in the range [384MHz - 768MHz], check the CLOCK_PLL_F value"
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#endif
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#if (CLOCK_PLL_OUT < 48000000) || (CLOCK_PLL_OUT > 384000000)
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#if (CLOCK_PLL_OUT < MHZ(48)) || (CLOCK_PLL_OUT > MHZ(384))
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#error "PLL output frequency must be in the range [48MHz - 384MHz], check the CLOCK_PLL_Q value"
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#endif
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#elif CONFIG_USE_CLOCK_HFXOSC
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#define CLOCK_CORECLOCK (16000000UL)
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#define CLOCK_CORECLOCK MHZ(16)
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#endif
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/*
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When using HFROSC input clock, the core clock cannot be computed from settings,
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call cpu_freq() to get the configured CPU frequency.
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*/
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#elif CONFIG_USE_CLOCK_HFROSC_PLL
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#ifndef CONFIG_CLOCK_DESIRED_FREQUENCY
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#define CONFIG_CLOCK_DESIRED_FREQUENCY (320000000UL)
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#define CONFIG_CLOCK_DESIRED_FREQUENCY MHZ(320)
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#endif
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#elif CONFIG_USE_CLOCK_HFROSC
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#ifndef CONFIG_CLOCK_HFROSC_TRIM
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#define CONFIG_CLOCK_HFROSC_TRIM (6) /* ~72000000Hz input freq */
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#endif
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#ifndef CONFIG_CLOCK_HFROSC_DIV
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#define CONFIG_CLOCK_HFROSC_DIV (1) /* Divide by 2 */
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#endif
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#else
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#error "Invalid clock configuration"
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#endif
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/** @} */
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/**
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@ -34,22 +34,22 @@ extern "C" {
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#ifndef CONFIG_USE_CLOCK_HFXOSC_PLL
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#if IS_ACTIVE(CONFIG_USE_CLOCK_HFXOSC) || IS_ACTIVE(CONFIG_USE_CLOCK_HFROSC_PLL) || \
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IS_ACTIVE(CONFIG_USE_CLOCK_HFROSC)
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#define CONFIG_USE_CLOCK_HFXOSC_PLL (0)
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#define CONFIG_USE_CLOCK_HFXOSC_PLL 0
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#else
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#define CONFIG_USE_CLOCK_HFXOSC_PLL (1) /* Use PLL clocked by HFXOSC by default */
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#define CONFIG_USE_CLOCK_HFXOSC_PLL 1 /* Use PLL clocked by HFXOSC by default */
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#endif
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#endif /* CONFIG_USE_CLOCK_HFXOSC_PLL */
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#ifndef CONFIG_USE_CLOCK_HFXOSC
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#define CONFIG_USE_CLOCK_HFXOSC (0)
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#define CONFIG_USE_CLOCK_HFXOSC 0
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#endif /* CONFIG_USE_CLOCK_HFXOSC */
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#ifndef CONFIG_USE_CLOCK_HFROSC_PLL
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#define CONFIG_USE_CLOCK_HFROSC_PLL (0)
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#define CONFIG_USE_CLOCK_HFROSC_PLL 0
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#endif /* CONFIG_USE_CLOCK_HFROSC_PLL */
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#ifndef CONFIG_USE_CLOCK_HFROSC
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#define CONFIG_USE_CLOCK_HFROSC (0)
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#define CONFIG_USE_CLOCK_HFROSC 0
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#endif /* CONFIG_USE_CLOCK_HFROSC */
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#if CONFIG_USE_CLOCK_HFXOSC_PLL && \
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@ -72,7 +72,6 @@ extern "C" {
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#error "Cannot use HFROSC with other clock configurations"
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#endif
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#if CONFIG_USE_CLOCK_HFXOSC_PLL
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#define CONFIG_CLOCK_PLL_R (1) /* Divide input clock by 2, mandatory with HFXOSC */
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#ifndef CONFIG_CLOCK_PLL_F
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#define CONFIG_CLOCK_PLL_F (39) /* Multiply REFR by 80, e.g 2 * (39 + 1) */
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@ -80,46 +79,43 @@ extern "C" {
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#ifndef CONFIG_CLOCK_PLL_Q
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#define CONFIG_CLOCK_PLL_Q (1) /* Divide VCO by 2, e.g 2^1 */
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#endif
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#define CLOCK_PLL_INPUT_CLOCK (16000000UL)
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#if CONFIG_USE_CLOCK_HFXOSC_PLL
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#define CLOCK_PLL_INPUT_CLOCK MHZ(16)
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#define CLOCK_PLL_REFR (CLOCK_PLL_INPUT_CLOCK / (CONFIG_CLOCK_PLL_R + 1))
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#define CLOCK_PLL_VCO (CLOCK_PLL_REFR * (2 * (CONFIG_CLOCK_PLL_F + 1)))
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#define CLOCK_PLL_OUT (CLOCK_PLL_VCO / (1 << CONFIG_CLOCK_PLL_Q))
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#define CLOCK_CORECLOCK (CLOCK_PLL_OUT) /* 320000000Hz with the values used above */
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/* Check PLL settings */
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#if CLOCK_PLL_REFR != 8000000
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#if CLOCK_PLL_REFR != MHZ(8)
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#error "Only R=2 can be used when using HFXOSC"
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#endif
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#if (CLOCK_PLL_VCO < 384000000) || (CLOCK_PLL_VCO > 768000000)
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#if (CLOCK_PLL_VCO < MHZ(384)) || (CLOCK_PLL_VCO > MHZ(768))
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#error "VCO frequency must be in the range [384MHz - 768MHz], check the CLOCK_PLL_F value"
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#endif
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#if (CLOCK_PLL_OUT < 48000000) || (CLOCK_PLL_OUT > 384000000)
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#if (CLOCK_PLL_OUT < MHZ(48)) || (CLOCK_PLL_OUT > MHZ(384))
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#error "PLL output frequency must be in the range [48MHz - 384MHz], check the CLOCK_PLL_Q value"
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#endif
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#elif CONFIG_USE_CLOCK_HFXOSC
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#define CLOCK_CORECLOCK (16000000UL)
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#define CLOCK_CORECLOCK MHZ(16)
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#endif
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/*
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When using HFROSC input clock, the core clock cannot be computed from settings,
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call cpu_freq() to get the configured CPU frequency.
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*/
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#elif CONFIG_USE_CLOCK_HFROSC_PLL
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#ifndef CONFIG_CLOCK_DESIRED_FREQUENCY
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#define CONFIG_CLOCK_DESIRED_FREQUENCY (320000000UL)
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#define CONFIG_CLOCK_DESIRED_FREQUENCY MHZ(320)
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#endif
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#elif CONFIG_USE_CLOCK_HFROSC
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#ifndef CONFIG_CLOCK_HFROSC_TRIM
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#define CONFIG_CLOCK_HFROSC_TRIM (6) /* ~72000000Hz input freq */
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#endif
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#ifndef CONFIG_CLOCK_HFROSC_DIV
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#define CONFIG_CLOCK_HFROSC_DIV (1) /* Divide by 2 */
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#endif
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#else
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#error "Invalid clock configuration"
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#endif
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/** @} */
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/**
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@ -22,7 +22,7 @@
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#include "vendor/prci_driver.h"
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#if !(CONFIG_USE_CLOCK_HFXOSC || CONFIG_USE_CLOCK_HFXOSC_PLL)
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#if IS_ACTIVE(CONFIG_USE_CLOCK_HFROSC) || IS_ACTIVE(CONFIG_USE_CLOCK_HFROSC_PLL)
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static uint32_t _cpu_frequency = 0;
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#endif
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@ -41,58 +41,59 @@ void clock_init(void)
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PRCI_REG(PRCI_PLLCFG) &= ~PLL_SEL(PLL_SEL_PLL);
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}
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#if CONFIG_USE_CLOCK_HFXOSC || CONFIG_USE_CLOCK_HFXOSC_PLL
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/* Ensure HFXOSC is enabled */
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PRCI_REG(PRCI_HFXOSCCFG) = XOSC_EN(1);
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if (IS_ACTIVE(CONFIG_USE_CLOCK_HFXOSC) || IS_ACTIVE(CONFIG_USE_CLOCK_HFXOSC_PLL)) {
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/* Ensure HFXOSC is enabled */
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PRCI_REG(PRCI_HFXOSCCFG) = XOSC_EN(1);
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/* Wait for HFXOSC to become ready */
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while ((PRCI_REG(PRCI_HFXOSCCFG) & XOSC_RDY(1)) == 0);
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/* Wait for HFXOSC to become ready */
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while ((PRCI_REG(PRCI_HFXOSCCFG) & XOSC_RDY(1)) == 0);
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/* Select HFXOSC as reference frequency and bypass PLL */
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PRCI_REG(PRCI_PLLCFG) = PLL_REFSEL(PLL_REFSEL_HFXOSC) | PLL_BYPASS(1);
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/* Select HFXOSC as reference frequency and bypass PLL */
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PRCI_REG(PRCI_PLLCFG) = PLL_REFSEL(PLL_REFSEL_HFXOSC) | PLL_BYPASS(1);
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#if CONFIG_USE_CLOCK_HFXOSC_PLL
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/* Divide final output frequency by 1 */
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PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
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if (IS_ACTIVE(CONFIG_USE_CLOCK_HFXOSC_PLL)) {
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/* Divide final output frequency by 1 */
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PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
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/* Configure PLL */
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PRCI_REG(PRCI_PLLCFG) |= PLL_R(CONFIG_CLOCK_PLL_R) | PLL_F(CONFIG_CLOCK_PLL_F) | PLL_Q(CONFIG_CLOCK_PLL_Q);
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/* Configure PLL */
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PRCI_REG(PRCI_PLLCFG) |= PLL_R(CONFIG_CLOCK_PLL_R) | PLL_F(CONFIG_CLOCK_PLL_F) | PLL_Q(CONFIG_CLOCK_PLL_Q);
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/* Disable PLL Bypass */
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PRCI_REG(PRCI_PLLCFG) &= ~PLL_BYPASS(1);
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/* Disable PLL Bypass */
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PRCI_REG(PRCI_PLLCFG) &= ~PLL_BYPASS(1);
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/* Now it is safe to check for PLL Lock */
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while ((PRCI_REG(PRCI_PLLCFG) & PLL_LOCK(1)) == 0);
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#endif
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/* Now it is safe to check for PLL Lock */
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while ((PRCI_REG(PRCI_PLLCFG) & PLL_LOCK(1)) == 0);
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}
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/* Switch over to PLL Clock source */
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PRCI_REG(PRCI_PLLCFG) |= PLL_SEL(PLL_SEL_PLL);
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/* Switch over to PLL Clock source */
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PRCI_REG(PRCI_PLLCFG) |= PLL_SEL(PLL_SEL_PLL);
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/* Turn off the HFROSC */
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PRCI_REG(PRCI_HFROSCCFG) &= ~ROSC_EN(1);
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#elif CONFIG_USE_CLOCK_HFROSC_PLL
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PRCI_set_hfrosctrim_for_f_cpu(CONFIG_CLOCK_DESIRED_FREQUENCY, PRCI_FREQ_UNDERSHOOT);
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#else /* Clock HFROSC */
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/* Disable Bypass */
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PRCI_REG(PRCI_PLLCFG) &= ~PLL_BYPASS(1);
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/* Turn off the HFROSC */
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PRCI_REG(PRCI_HFROSCCFG) &= ~ROSC_EN(1);
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}
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else if (IS_ACTIVE(CONFIG_USE_CLOCK_HFROSC_PLL)) {
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PRCI_set_hfrosctrim_for_f_cpu(CONFIG_CLOCK_DESIRED_FREQUENCY, PRCI_FREQ_UNDERSHOOT);
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}
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else { /* Clock HFROSC */
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/* Disable Bypass */
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PRCI_REG(PRCI_PLLCFG) &= ~PLL_BYPASS(1);
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/* Configure trim and divider values of HFROSC */
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PRCI_REG(PRCI_HFROSCCFG) = (ROSC_DIV(CONFIG_CLOCK_HFROSC_DIV) | ROSC_TRIM(CONFIG_CLOCK_HFROSC_TRIM) | ROSC_EN(1));
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/* Configure trim and divider values of HFROSC */
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PRCI_REG(PRCI_HFROSCCFG) = (ROSC_DIV(CONFIG_CLOCK_HFROSC_DIV) | ROSC_TRIM(CONFIG_CLOCK_HFROSC_TRIM) | ROSC_EN(1));
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/* Wait for HFROSC to be ready */
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while ((PRCI_REG(PRCI_HFROSCCFG) & ROSC_RDY(1)) == 0);
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/* Wait for HFROSC to be ready */
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while ((PRCI_REG(PRCI_HFROSCCFG) & ROSC_RDY(1)) == 0);
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/* Don't use PLL clock source */
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PRCI_REG(PRCI_PLLCFG) &= ~PLL_SEL(PLL_SEL_PLL);
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#endif
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/* Don't use PLL clock source */
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PRCI_REG(PRCI_PLLCFG) &= ~PLL_SEL(PLL_SEL_PLL);
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}
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}
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uint32_t cpu_freq(void)
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{
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#if CONFIG_USE_CLOCK_HFXOSC || CONFIG_USE_CLOCK_HFXOSC_PLL
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return CLOCK_CORECLOCK;
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#else /* Clock frequency with HFROSC cannot be determined precisely from
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settings */
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#if IS_ACTIVE(CONFIG_USE_CLOCK_HFROSC) || IS_ACTIVE(CONFIG_USE_CLOCK_HFROSC_PLL)
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/* Clock frequency with HFROSC cannot be determined precisely from
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settings */
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/* If not done already, estimate the CPU frequency */
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if (_cpu_frequency == 0) {
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/* Ignore the first run (for icache reasons) */
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@ -100,5 +101,7 @@ uint32_t cpu_freq(void)
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_cpu_frequency = PRCI_measure_mcycle_freq(3000, RTC_FREQ);
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}
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return _cpu_frequency;
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#else
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return CLOCK_CORECLOCK;
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#endif
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}
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@ -26,6 +26,7 @@
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#define CPU_H
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#include "thread.h"
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#include "macros/units.h"
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#include "vendor/platform.h"
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#include "vendor/plic_driver.h"
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