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Merge #19910
19910: boards/stm32f469i-disco: enable FMC with SDRAM support r=aabadie a=gschorcht ### Contribution description This PR enables the FMC support on the `stm32f469i-disco` board and the on-board SDRAM ISSI IS42S32400F-6BL with 16 MByte. ### Testing procedure 1. `tests/periph/fmc` should succeed, just compile and flash the app with ``` BOARD=stm32f469i-disco make -C tests/periph/fmc flash term ``` 2. `tests/sys/malloc` should also use the SDRAM. Use ``` USEMODULE=periph_fmc_sdram CFLAGS='-DCHUNK_SIZE=131072' \ BOARD=stm32f469i-disco make -C tests/sys/malloc flash term ``` and check that the heap also uses the memory in the range from `0xc0000000` to `0xc0fffffff`. ### Issues/PRs references Co-authored-by: Gunar Schorcht <gunar@schorcht.net>
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@ -10,6 +10,9 @@ config BOARD_STM32F469I_DISCO
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select HAS_PERIPH_ADC
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select HAS_PERIPH_DAC
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select HAS_PERIPH_DMA
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select HAS_PERIPH_FMC
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select HAS_PERIPH_FMC_SDRAM
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select HAS_PERIPH_FMC_32BIT
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select HAS_PERIPH_I2C
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select HAS_PERIPH_PWM
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select HAS_PERIPH_RTC
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@ -1,3 +1,7 @@
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ifneq (,$(filter saul_default,$(USEMODULE)))
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USEMODULE += saul_gpio
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endif
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ifneq (,$(filter periph_fmc,$(USEMODULE)))
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FEATURES_REQUIRED += periph_fmc_32bit
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endif
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@ -5,6 +5,9 @@ CPU_MODEL = stm32f469ni
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FEATURES_PROVIDED += periph_adc
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FEATURES_PROVIDED += periph_dac
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FEATURES_PROVIDED += periph_dma
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FEATURES_PROVIDED += periph_fmc
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FEATURES_PROVIDED += periph_fmc_32bit
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FEATURES_PROVIDED += periph_fmc_sdram
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FEATURES_PROVIDED += periph_i2c
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FEATURES_PROVIDED += periph_rtc
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FEATURES_PROVIDED += periph_pwm
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@ -13,3 +13,7 @@ DIR_NAME_AT_REMED = "DIS_F469NI"
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# openocd and cpy2remed programmers are supported
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PROGRAMMERS_SUPPORTED += openocd cpy2remed
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# heap configuration
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FMC_RAM_ADDR=0xc0000000
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FMC_RAM_LEN=16384K
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@ -38,6 +38,7 @@ The MCU presents a large list of peripherals available, but specifically this de
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| USBs | 1 Full Speed |
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| Ethernet MAC | Yes |
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| RNG | Yes |
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| SDRAM | Yes (16 MByte) |
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| Vcc | 1.7V - 3.6V |
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| Datasheet | [MCU Datasheet](https://www.st.com/resource/en/datasheet/stm32f469ae.pdf) (pdf) |
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| Reference Manual | [Dev-Kit Reference Manual](https://www.st.com/resource/en/user_manual/um1932-discovery-kit-with-stm32f469ni-mcu-stmicroelectronics.pdf) (pdf)|
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@ -263,6 +263,129 @@ static const dac_conf_t dac_config[] = {
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#define DAC_NUMOF ARRAY_SIZE(dac_config)
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/** @} */
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/**
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* @name FMC configuration
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* @{
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*/
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/**
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* @brief FMC controller configuration
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*/
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static const fmc_conf_t fmc_config = {
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.bus = AHB3,
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.rcc_mask = RCC_AHB3ENR_FMCEN,
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#if MODULE_PERIPH_FMC_SDRAM
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.ba0_pin = { .pin = GPIO_PIN(PORT_G, 4), .af = GPIO_AF12, }, /* A14 signal */
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.ba1_pin = { .pin = GPIO_PIN(PORT_G, 5), .af = GPIO_AF12, }, /* A15 signal */
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.sdclk_pin = { .pin = GPIO_PIN(PORT_G, 8), .af = GPIO_AF12, }, /* SDCLK signal */
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.sdnwe_pin = { .pin = GPIO_PIN(PORT_C, 0), .af = GPIO_AF12, }, /* SDNWE signal */
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.sdnras_pin = { .pin = GPIO_PIN(PORT_F, 11), .af = GPIO_AF12, }, /* SDNRAS signal */
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.sdncas_pin = { .pin = GPIO_PIN(PORT_G, 15), .af = GPIO_AF12, }, /* SDNCAS signal */
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.sdcke0_pin = { .pin = GPIO_PIN(PORT_H, 2), .af = GPIO_AF12, }, /* SDCKE0 signal */
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.sdne0_pin = { .pin = GPIO_PIN(PORT_H, 3), .af = GPIO_AF12, }, /* SDNE0 signal */
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.addr = {
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{ .pin = GPIO_PIN(PORT_F, 0), .af = GPIO_AF12, }, /* A0 signal */
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{ .pin = GPIO_PIN(PORT_F, 1), .af = GPIO_AF12, }, /* A1 signal */
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{ .pin = GPIO_PIN(PORT_F, 2), .af = GPIO_AF12, }, /* A2 signal */
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{ .pin = GPIO_PIN(PORT_F, 3), .af = GPIO_AF12, }, /* A3 signal */
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{ .pin = GPIO_PIN(PORT_F, 4), .af = GPIO_AF12, }, /* A4 signal */
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{ .pin = GPIO_PIN(PORT_F, 5), .af = GPIO_AF12, }, /* A5 signal */
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{ .pin = GPIO_PIN(PORT_F, 12), .af = GPIO_AF12, }, /* A6 signal */
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{ .pin = GPIO_PIN(PORT_F, 13), .af = GPIO_AF12, }, /* A7 signal */
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{ .pin = GPIO_PIN(PORT_F, 14), .af = GPIO_AF12, }, /* A8 signal */
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{ .pin = GPIO_PIN(PORT_F, 15), .af = GPIO_AF12, }, /* A9 signal */
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{ .pin = GPIO_PIN(PORT_G, 0), .af = GPIO_AF12, }, /* A10 signal */
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{ .pin = GPIO_PIN(PORT_G, 1), .af = GPIO_AF12, }, /* A11 signal */
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},
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#endif
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.data = {
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{ .pin = GPIO_PIN(PORT_D, 14), .af = GPIO_AF12, }, /* D0 signal */
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{ .pin = GPIO_PIN(PORT_D, 15), .af = GPIO_AF12, }, /* D1 signal */
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{ .pin = GPIO_PIN(PORT_D, 0), .af = GPIO_AF12, }, /* D2 signal */
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{ .pin = GPIO_PIN(PORT_D, 1), .af = GPIO_AF12, }, /* D3 signal */
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{ .pin = GPIO_PIN(PORT_E, 7), .af = GPIO_AF12, }, /* D4 signal */
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{ .pin = GPIO_PIN(PORT_E, 8), .af = GPIO_AF12, }, /* D5 signal */
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{ .pin = GPIO_PIN(PORT_E, 9), .af = GPIO_AF12, }, /* D6 signal */
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{ .pin = GPIO_PIN(PORT_E, 10), .af = GPIO_AF12, }, /* D7 signal */
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#if MODULE_PERIPH_FMC_32BIT
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{ .pin = GPIO_PIN(PORT_E, 11), .af = GPIO_AF12, }, /* D8 signal */
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{ .pin = GPIO_PIN(PORT_E, 12), .af = GPIO_AF12, }, /* D9 signal */
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{ .pin = GPIO_PIN(PORT_E, 13), .af = GPIO_AF12, }, /* D10 signal */
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{ .pin = GPIO_PIN(PORT_E, 14), .af = GPIO_AF12, }, /* D11 signal */
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{ .pin = GPIO_PIN(PORT_E, 15), .af = GPIO_AF12, }, /* D12 signal */
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{ .pin = GPIO_PIN(PORT_D, 8), .af = GPIO_AF12, }, /* D13 signal */
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{ .pin = GPIO_PIN(PORT_D, 9), .af = GPIO_AF12, }, /* D14 signal */
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{ .pin = GPIO_PIN(PORT_D, 10), .af = GPIO_AF12, }, /* D15 signal */
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{ .pin = GPIO_PIN(PORT_H, 8), .af = GPIO_AF12, }, /* D16 signal */
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{ .pin = GPIO_PIN(PORT_H, 9), .af = GPIO_AF12, }, /* D17 signal */
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{ .pin = GPIO_PIN(PORT_H, 10), .af = GPIO_AF12, }, /* D18 signal */
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{ .pin = GPIO_PIN(PORT_H, 11), .af = GPIO_AF12, }, /* D19 signal */
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{ .pin = GPIO_PIN(PORT_H, 12), .af = GPIO_AF12, }, /* D20 signal */
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{ .pin = GPIO_PIN(PORT_H, 13), .af = GPIO_AF12, }, /* D21 signal */
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{ .pin = GPIO_PIN(PORT_H, 14), .af = GPIO_AF12, }, /* D22 signal */
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{ .pin = GPIO_PIN(PORT_H, 15), .af = GPIO_AF12, }, /* D23 signal */
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{ .pin = GPIO_PIN(PORT_I, 0), .af = GPIO_AF12, }, /* D24 signal */
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{ .pin = GPIO_PIN(PORT_I, 1), .af = GPIO_AF12, }, /* D25 signal */
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{ .pin = GPIO_PIN(PORT_I, 2), .af = GPIO_AF12, }, /* D26 signal */
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{ .pin = GPIO_PIN(PORT_I, 3), .af = GPIO_AF12, }, /* D27 signal */
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{ .pin = GPIO_PIN(PORT_I, 6), .af = GPIO_AF12, }, /* D28 signal */
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{ .pin = GPIO_PIN(PORT_I, 7), .af = GPIO_AF12, }, /* D29 signal */
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{ .pin = GPIO_PIN(PORT_I, 9), .af = GPIO_AF12, }, /* D30 signal */
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{ .pin = GPIO_PIN(PORT_I, 10), .af = GPIO_AF12, }, /* D31 signal */
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#endif
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},
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.nbl0_pin = { .pin = GPIO_PIN(PORT_E, 0), .af = GPIO_AF12, }, /* FMC_NBL0 signal (DQM0) */
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.nbl1_pin = { .pin = GPIO_PIN(PORT_E, 1), .af = GPIO_AF12, }, /* FMC_NBL1 signal (DQM1) */
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.nbl2_pin = { .pin = GPIO_PIN(PORT_I, 4), .af = GPIO_AF12, }, /* FMC_NBL2 signal (DQM2) */
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.nbl3_pin = { .pin = GPIO_PIN(PORT_I, 5), .af = GPIO_AF12, }, /* FMC_NBL3 signal (DQM3) */
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};
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/**
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* @brief FMC Bank configuration
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*
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* The board has a SDRAM IS42S32400F-6BL with 128 MBit on-board.
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* It is organized in 4 banks of 1M x 32 bits each and connected to bank 5
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* at address 0xc0000000.
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*/
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static const fmc_bank_conf_t fmc_bank_config[] = {
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/* bank 5 is used for SDRAM */
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{
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.bank = FMC_BANK_5,
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.mem_type = FMC_SDRAM,
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.data_width = FMC_BUS_WIDTH_32BIT,
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.address = 0xc0000000, /* Bank 6 is mapped to 0xc0000000 */
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.size = MiB(16), /* Size in MByte, 4M x 32 Bit */
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.sdram = {
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.clk_period = 2, /* SDCLK = 2 x HCLK */
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.row_bits = 12, /* A11..A0 used for row address */
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.col_bits = 8, /* A7..A0 used for column address */
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.cas_latency = 2, /* CAS latency is 2 clock cycles */
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.read_delay = 0, /* No read delay after CAS */
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.burst_read = true, /* Burst read mode enabled */
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.burst_write = false, /* Burst write mode disabled */
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.burst_len = FMC_BURST_LENGTH_1, /* Burst length is 1 */
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.burst_interleaved = false, /* Burst mode interleaved */
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.write_protect = false, /* No write protection */
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.four_banks = true, /* SDRAM has four internal banks */
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.timing = { /* SDRAM Timing parameters */
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.row_to_col_delay = 2, /* Row to column delay (2 clock cycles) */
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.row_precharge = 2, /* Row precharge delay (2 clock cycles) */
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.recovery_delay = 2, /* Recovery delay is (2 clock cycles) */
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.row_cylce = 7, /* Row cycle delay is (7 clock cycles) */
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.self_refresh = 4, /* Self refresh time is (4 clock cycles) */
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.exit_self_refresh = 7, /* Exit self-refresh delay (7 clock cycles) */
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.load_mode_register = 2, /* Load Mode Register to Activate delay */
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.refresh_period = 16, /* Refresh period in ms */
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},
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},
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},
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};
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/**
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* @brief Number of configured FMC banks
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*/
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#define FMC_BANK_NUMOF ARRAY_SIZE(fmc_bank_config)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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