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Merge pull request #6991 from aabadie/nucleo144_f722
boards/nucleo144-f722: add initial support
This commit is contained in:
GitHub
commit
7b79f4d3d2
3
boards/nucleo144-f722/Makefile
Normal file
3
boards/nucleo144-f722/Makefile
Normal file
@ -0,0 +1,3 @@
|
||||
MODULE = board
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|
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include $(RIOTBASE)/Makefile.base
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1
boards/nucleo144-f722/Makefile.dep
Normal file
1
boards/nucleo144-f722/Makefile.dep
Normal file
@ -0,0 +1 @@
|
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include $(RIOTBOARD)/nucleo-common/Makefile.dep
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12
boards/nucleo144-f722/Makefile.features
Normal file
12
boards/nucleo144-f722/Makefile.features
Normal file
@ -0,0 +1,12 @@
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# Put defined MCU peripherals here (in alphabetical order)
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FEATURES_PROVIDED += periph_cpuid
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FEATURES_PROVIDED += periph_gpio
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FEATURES_PROVIDED += periph_hwrng
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FEATURES_PROVIDED += periph_timer
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FEATURES_PROVIDED += periph_uart
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# load the common Makefile.features for Nucleo144 boards
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include $(RIOTBOARD)/nucleo144-common/Makefile.features
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# The board MPU family (used for grouping by the CI system)
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FEATURES_MCU_GROUP = cortex_m7
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6
boards/nucleo144-f722/Makefile.include
Normal file
6
boards/nucleo144-f722/Makefile.include
Normal file
@ -0,0 +1,6 @@
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## the cpu to build for
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export CPU = stm32f7
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export CPU_MODEL = stm32f722ze
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# load the common Makefile.include for Nucleo144 boards
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include $(RIOTBOARD)/nucleo144-common/Makefile.include
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32
boards/nucleo144-f722/board.c
Normal file
32
boards/nucleo144-f722/board.c
Normal file
@ -0,0 +1,32 @@
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/*
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* Copyright (C) 2017 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
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* directory for more details.
|
||||
*/
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|
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/**
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* @ingroup boards_nucleo144-f722
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* @{
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*
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* @file
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* @brief Board specific implementations for the nucleo144-f722 board
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*
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*
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* @}
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*/
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#include "board.h"
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#include "periph/gpio.h"
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void board_init(void)
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{
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/* initialize the CPU */
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cpu_init();
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gpio_init(LED0_PIN, GPIO_OUT);
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gpio_init(LED1_PIN, GPIO_OUT);
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gpio_init(LED2_PIN, GPIO_OUT);
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}
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5
boards/nucleo144-f722/dist/openocd.cfg
vendored
Normal file
5
boards/nucleo144-f722/dist/openocd.cfg
vendored
Normal file
@ -0,0 +1,5 @@
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source [find interface/stlink-v2-1.cfg]
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transport select hla_swd
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source [find target/stm32f7x.cfg]
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35
boards/nucleo144-f722/include/board.h
Normal file
35
boards/nucleo144-f722/include/board.h
Normal file
@ -0,0 +1,35 @@
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/*
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* Copyright (C) 2017 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
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* directory for more details.
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*/
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/**
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* @defgroup boards_nucleo144-f722 Nucleo144-F722
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* @ingroup boards
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* @brief Board specific files for the nucleo144-f722 board
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* @{
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*
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* @file
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* @brief Board specific definitions for the nucleo144-f722 board
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*
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*/
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#ifndef BOARD_H
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#define BOARD_H
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#include "board_common.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* BOARD_H */
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/** @} */
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140
boards/nucleo144-f722/include/periph_conf.h
Normal file
140
boards/nucleo144-f722/include/periph_conf.h
Normal file
@ -0,0 +1,140 @@
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/*
|
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* Copyright (C) 2017 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
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*/
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|
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/**
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* @ingroup boards_nucleo144-f722
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* @{
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*
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* @file
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* @brief Peripheral MCU configuration for the nucleo144-f722 board
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*
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock system configuration
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* @{
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*/
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/* 0: no external high speed crystal available
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* else: actual crystal frequency [in Hz] */
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#define CLOCK_HSE (8000000U)
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/* 0: no external low speed crystal available,
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* 1: external crystal available (always 32.768kHz) */
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#define CLOCK_LSE (1)
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/* give the target core clock (HCLK) frequency [in Hz],
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* maximum: 216MHz, min: 96MHz, must be multiple of 24MHz */
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#define CLOCK_CORECLOCK (216000000U)
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/* peripheral clock setup */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* min 25MHz */
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 54MHz */
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 108MHz */
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
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/** @} */
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/**
|
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* @name Timer configuration
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* @{
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*/
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static const timer_conf_t timer_config[] = {
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{
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.dev = TIM2,
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.max = 0xffffffff,
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.rcc_mask = RCC_APB1ENR_TIM2EN,
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.bus = APB1,
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.irqn = TIM2_IRQn
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}
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};
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#define TIMER_0_ISR isr_tim2
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#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
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/** @} */
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/**
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* @name UART configuration
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* @{
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*/
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static const uart_conf_t uart_config[] = {
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{
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.dev = USART3,
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.rcc_mask = RCC_APB1ENR_USART3EN,
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.rx_pin = GPIO_PIN(PORT_D, 9),
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.tx_pin = GPIO_PIN(PORT_D, 8),
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.rx_af = GPIO_AF7,
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.tx_af = GPIO_AF7,
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.bus = APB1,
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.irqn = USART3_IRQn,
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#ifdef UART_USE_DMA
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.dma_stream = 6,
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.dma_chan = 4
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#endif
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},
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{
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.dev = USART6,
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.rcc_mask = RCC_APB2ENR_USART6EN,
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.rx_pin = GPIO_PIN(PORT_G, 9),
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.tx_pin = GPIO_PIN(PORT_G, 14),
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.rx_af = GPIO_AF8,
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.tx_af = GPIO_AF8,
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.bus = APB2,
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.irqn = USART6_IRQn,
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#ifdef UART_USE_DMA
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.dma_stream = 5,
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.dma_chan = 4
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#endif
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},
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{
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.dev = USART2,
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.rcc_mask = RCC_APB1ENR_USART2EN,
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.rx_pin = GPIO_PIN(PORT_D, 6),
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.tx_pin = GPIO_PIN(PORT_D, 5),
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.rx_af = GPIO_AF7,
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.tx_af = GPIO_AF7,
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.bus = APB1,
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.irqn = USART2_IRQn,
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#ifdef UART_USE_DMA
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.dma_stream = 4,
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.dma_chan = 4
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#endif
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}
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};
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#define UART_0_ISR (isr_usart3)
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#define UART_0_DMA_ISR (isr_dma1_stream6)
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#define UART_1_ISR (isr_usart6)
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#define UART_1_DMA_ISR (isr_dma1_stream5)
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#define UART_2_ISR (isr_usart2)
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#define UART_2_DMA_ISR (isr_dma1_stream4)
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#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
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/** @} */
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/**
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* @name ADC configuration
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* @{
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*/
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#define ADC_NUMOF (0)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CONF_H */
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/** @} */
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@ -1,5 +1,6 @@
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/*
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* Copyright (C) 2017 Freie Universität Berlin
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* 2017 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
|
||||
* Public License v2.1. See the file LICENSE in the top level directory for more
|
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@ -16,6 +17,7 @@
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* @brief Implementation specific CPU configuration options
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*
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* @author Hauke Petersen <hauke.pertersen@fu-berlin.de>
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*/
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#ifndef CPU_CONF_H
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@ -29,6 +31,8 @@
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#include "vendor/stm32f767xx.h"
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#elif defined(CPU_MODEL_STM32F769NI)
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#include "vendor/stm32f769xx.h"
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#elif defined(CPU_MODEL_STM32F722ZE)
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#include "vendor/stm32f722xx.h"
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#endif
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#ifdef __cplusplus
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@ -44,6 +48,8 @@ extern "C" {
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#define CPU_IRQ_NUMOF (98U)
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#elif defined(CPU_MODEL_STM32F769NI) || defined(CPU_MODEL_STM32F767ZI)
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#define CPU_IRQ_NUMOF (110U)
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#elif defined(CPU_MODEL_STM32F722ZE)
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#define CPU_IRQ_NUMOF (104U)
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#endif
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/** @} */
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|
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15160
cpu/stm32f7/include/vendor/stm32f722xx.h
vendored
Normal file
15160
cpu/stm32f7/include/vendor/stm32f722xx.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
30
cpu/stm32f7/ldscripts/stm32f722ze.ld
Normal file
30
cpu/stm32f7/ldscripts/stm32f722ze.ld
Normal file
@ -0,0 +1,30 @@
|
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/*
|
||||
* Copyright (C) 2017 Inria
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32f7
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32F722ZE
|
||||
*
|
||||
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
|
||||
*
|
||||
* @}
|
||||
*/
|
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|
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MEMORY
|
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{
|
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rom (rx) : ORIGIN = 0x08000000, LENGTH = 512K
|
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ram (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
|
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cpuid (r) : ORIGIN = 0x1ff07A10, LENGTH = 12
|
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}
|
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|
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_cpuid_address = ORIGIN(cpuid);
|
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|
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INCLUDE cortexm_base.ld
|
||||
@ -132,7 +132,6 @@ WEAK_DEFAULT void isr_dfsdm1_flt0(void);
|
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WEAK_DEFAULT void isr_dfsdm1_flt1(void);
|
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WEAK_DEFAULT void isr_dfsdm1_flt2(void);
|
||||
WEAK_DEFAULT void isr_dfsdm1_flt3(void);
|
||||
WEAK_DEFAULT void isr_sdmmc2(void);
|
||||
WEAK_DEFAULT void isr_can3_tx(void);
|
||||
WEAK_DEFAULT void isr_can3_rx0(void);
|
||||
WEAK_DEFAULT void isr_can3_rx1(void);
|
||||
@ -140,144 +139,177 @@ WEAK_DEFAULT void isr_can3_sce(void);
|
||||
WEAK_DEFAULT void isr_jpeg(void);
|
||||
WEAK_DEFAULT void isr_mdios(void);
|
||||
#endif
|
||||
#if defined(CPU_MODEL_STM32F769NI) || defined(CPU_MODEL_STM32F767ZI) \
|
||||
|| defined(CPU_MODEL_STM32F722ZE)
|
||||
WEAK_DEFAULT void isr_sdmmc2(void);
|
||||
#endif
|
||||
|
||||
/* interrupt vector table */
|
||||
ISR_VECTORS const void *interrupt_vector[] = {
|
||||
/* Exception stack pointer */
|
||||
(void*) (&_estack), /* pointer to the top of the stack */
|
||||
(void*) (&_estack), /* pointer to the top of the stack */
|
||||
/* Cortex-M7 handlers */
|
||||
(void*) reset_handler_default, /* entry point of the program */
|
||||
(void*) nmi_default, /* non maskable interrupt handler */
|
||||
(void*) hard_fault_default, /* hard fault exception */
|
||||
(void*) mem_manage_default, /* memory manage exception */
|
||||
(void*) bus_fault_default, /* bus fault exception */
|
||||
(void*) usage_fault_default, /* usage fault exception */
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) isr_svc, /* system call interrupt, in RIOT used for
|
||||
* switching into thread context on boot */
|
||||
(void*) debug_mon_default, /* debug monitor exception */
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) isr_pendsv, /* pendSV interrupt, in RIOT the actual
|
||||
* context switching is happening here */
|
||||
(void*) isr_systick, /* SysTick interrupt, not used in RIOT */
|
||||
(void*) reset_handler_default, /* entry point of the program */
|
||||
(void*) nmi_default, /* [-14] non maskable interrupt handler */
|
||||
(void*) hard_fault_default, /* [-13] hard fault exception */
|
||||
(void*) mem_manage_default, /* [-12] memory manage exception */
|
||||
(void*) bus_fault_default, /* [-11] bus fault exception */
|
||||
(void*) usage_fault_default, /* [-10] usage fault exception */
|
||||
(void*) (0UL), /* [-9] Reserved */
|
||||
(void*) (0UL), /* [-8] Reserved */
|
||||
(void*) (0UL), /* [-7] Reserved */
|
||||
(void*) (0UL), /* [-6] Reserved */
|
||||
(void*) isr_svc, /* [-5] system call interrupt, in RIOT used for
|
||||
switching into thread context on boot */
|
||||
(void*) debug_mon_default, /* [-4] debug monitor exception */
|
||||
(void*) (0UL), /* [-3] Reserved */
|
||||
(void*) isr_pendsv, /* [-2] pendSV interrupt, in RIOT the actual
|
||||
context switching is happening here */
|
||||
(void*) isr_systick, /* [-1] SysTick interrupt, not used in RIOT */
|
||||
/* STM specific peripheral handlers */
|
||||
(void*) isr_wwdg,
|
||||
(void*) isr_pvd,
|
||||
(void*) isr_tamp_stamp,
|
||||
(void*) isr_rtc_wkup,
|
||||
(void*) isr_flash,
|
||||
(void*) isr_rcc,
|
||||
(void*) isr_exti,
|
||||
(void*) isr_exti,
|
||||
(void*) isr_exti,
|
||||
(void*) isr_exti,
|
||||
(void*) isr_exti,
|
||||
(void*) isr_dma1_stream0,
|
||||
(void*) isr_dma1_stream1,
|
||||
(void*) isr_dma1_stream2,
|
||||
(void*) isr_dma1_stream3,
|
||||
(void*) isr_dma1_stream4,
|
||||
(void*) isr_dma1_stream5,
|
||||
(void*) isr_dma1_stream6,
|
||||
(void*) isr_adc,
|
||||
(void*) isr_can1_tx,
|
||||
(void*) isr_can1_rx0,
|
||||
(void*) isr_can1_rx1,
|
||||
(void*) isr_can1_sce,
|
||||
(void*) isr_exti,
|
||||
(void*) isr_tim1_brk_tim9,
|
||||
(void*) isr_tim1_up_tim10,
|
||||
(void*) isr_tim1_trg_com_tim11,
|
||||
(void*) isr_tim1_cc,
|
||||
(void*) isr_tim2,
|
||||
(void*) isr_tim3,
|
||||
(void*) isr_tim4,
|
||||
(void*) isr_i2c1_ev,
|
||||
(void*) isr_i2c1_er,
|
||||
(void*) isr_i2c2_ev,
|
||||
(void*) isr_i2c2_er,
|
||||
(void*) isr_spi1,
|
||||
(void*) isr_spi2,
|
||||
(void*) isr_usart1,
|
||||
(void*) isr_usart2,
|
||||
(void*) isr_usart3,
|
||||
(void*) isr_exti,
|
||||
(void*) isr_rtc_alarm,
|
||||
(void*) isr_otg_fs_wkup,
|
||||
(void*) isr_tim8_brk_tim12,
|
||||
(void*) isr_tim8_up_tim13,
|
||||
(void*) isr_tim8_trg_com_tim14,
|
||||
(void*) isr_tim8_cc,
|
||||
(void*) isr_dma1_stream7,
|
||||
(void*) isr_fmc,
|
||||
(void*) isr_sdmmc1,
|
||||
(void*) isr_tim5,
|
||||
(void*) isr_spi3,
|
||||
(void*) isr_uart4,
|
||||
(void*) isr_uart5,
|
||||
(void*) isr_tim6_dac,
|
||||
(void*) isr_tim7,
|
||||
(void*) isr_dma2_stream0,
|
||||
(void*) isr_dma2_stream1,
|
||||
(void*) isr_dma2_stream2,
|
||||
(void*) isr_dma2_stream3,
|
||||
(void*) isr_dma2_stream4,
|
||||
(void*) isr_eth,
|
||||
(void*) isr_eth_wkup,
|
||||
(void*) isr_can2_tx,
|
||||
(void*) isr_can2_rx0,
|
||||
(void*) isr_can2_rx1,
|
||||
(void*) isr_can2_sce,
|
||||
(void*) isr_otg_fs,
|
||||
(void*) isr_dma2_stream5,
|
||||
(void*) isr_dma2_stream6,
|
||||
(void*) isr_dma2_stream7,
|
||||
(void*) isr_usart6,
|
||||
(void*) isr_i2c3_ev,
|
||||
(void*) isr_i2c3_er,
|
||||
(void*) isr_otg_hs_ep1_out,
|
||||
(void*) isr_otg_hs_ep1_in,
|
||||
(void*) isr_otg_hs_wkup,
|
||||
(void*) isr_otg_hs,
|
||||
(void*) isr_dcmi,
|
||||
(void*) (0UL),
|
||||
(void*) isr_rng,
|
||||
(void*) isr_fpu,
|
||||
(void*) isr_uart7,
|
||||
(void*) isr_uart8,
|
||||
(void*) isr_spi4,
|
||||
(void*) isr_spi5,
|
||||
(void*) isr_spi6,
|
||||
(void*) isr_sai1,
|
||||
(void*) isr_ltdc,
|
||||
(void*) isr_ltdc_er,
|
||||
(void*) isr_dma2d,
|
||||
(void*) isr_sai2,
|
||||
(void*) isr_quadspi,
|
||||
(void*) isr_lptim1,
|
||||
(void*) isr_cec,
|
||||
(void*) isr_i2c4_ev,
|
||||
(void*) isr_i2c4_er,
|
||||
(void*) isr_spdif_rx,
|
||||
(void*) isr_wwdg, /* [0] Window WatchDog Interrupt */
|
||||
(void*) isr_pvd, /* [1] PVD through EXTI Line detection Interrupt */
|
||||
(void*) isr_tamp_stamp, /* [2] Tamper and TimeStamp interrupts through the EXTI line */
|
||||
(void*) isr_rtc_wkup, /* [3] RTC Wakeup interrupt through the EXTI line */
|
||||
(void*) isr_flash, /* [4] FLASH global Interrupt */
|
||||
(void*) isr_rcc, /* [5] RCC global Interrupt */
|
||||
(void*) isr_exti, /* [6] EXTI Line0 Interrupt */
|
||||
(void*) isr_exti, /* [7] EXTI Line1 Interrupt */
|
||||
(void*) isr_exti, /* [8] EXTI Line2 Interrupt */
|
||||
(void*) isr_exti, /* [9] EXTI Line3 Interrupt */
|
||||
(void*) isr_exti, /* [10] EXTI Line4 Interrupt */
|
||||
(void*) isr_dma1_stream0, /* [11] DMA1 Stream 0 global Interrupt */
|
||||
(void*) isr_dma1_stream1, /* [12] DMA1 Stream 1 global Interrupt */
|
||||
(void*) isr_dma1_stream2, /* [13] DMA1 Stream 2 global Interrupt */
|
||||
(void*) isr_dma1_stream3, /* [14] DMA1 Stream 3 global Interrupt */
|
||||
(void*) isr_dma1_stream4, /* [15] DMA1 Stream 4 global Interrupt */
|
||||
(void*) isr_dma1_stream5, /* [16] DMA1 Stream 5 global Interrupt */
|
||||
(void*) isr_dma1_stream6, /* [17] DMA1 Stream 6 global Interrupt */
|
||||
(void*) isr_adc, /* [18] ADC1, ADC2 and ADC3 global Interrupts */
|
||||
(void*) isr_can1_tx, /* [19] CAN1 TX Interrupt */
|
||||
(void*) isr_can1_rx0, /* [20] CAN1 RX0 Interrupt */
|
||||
(void*) isr_can1_rx1, /* [21] CAN1 RX1 Interrupt */
|
||||
(void*) isr_can1_sce, /* [22] CAN1 SCE Interrupt */
|
||||
(void*) isr_exti, /* [23] External Line[9:5] Interrupts */
|
||||
(void*) isr_tim1_brk_tim9, /* [24] TIM1 Break interrupt and TIM9 global interrupt */
|
||||
(void*) isr_tim1_up_tim10, /* [25] TIM1 Update Interrupt and TIM10 global interrupt */
|
||||
(void*) isr_tim1_trg_com_tim11, /* [26] TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
|
||||
(void*) isr_tim1_cc, /* [27] TIM1 Capture Compare Interrupt */
|
||||
(void*) isr_tim2, /* [28] TIM2 global Interrupt */
|
||||
(void*) isr_tim3, /* [29] TIM3 global Interrupt */
|
||||
(void*) isr_tim4, /* [30] TIM4 global Interrupt */
|
||||
(void*) isr_i2c1_ev, /* [31] I2C1 Event Interrupt */
|
||||
(void*) isr_i2c1_er, /* [32] I2C1 Error Interrupt */
|
||||
(void*) isr_i2c2_ev, /* [33] I2C2 Event Interrupt */
|
||||
(void*) isr_i2c2_er, /* [34] I2C2 Error Interrupt */
|
||||
(void*) isr_spi1, /* [35] SPI1 global Interrupt */
|
||||
(void*) isr_spi2, /* [36] SPI2 global Interrupt */
|
||||
(void*) isr_usart1, /* [37] USART1 global Interrupt */
|
||||
(void*) isr_usart2, /* [38] USART2 global Interrupt */
|
||||
(void*) isr_usart3, /* [39] USART3 global Interrupt */
|
||||
(void*) isr_exti, /* [40] External Line[15:10] Interrupts */
|
||||
(void*) isr_rtc_alarm, /* [41] RTC Alarm (A and B) through EXTI Line Interrupt */
|
||||
(void*) isr_otg_fs_wkup, /* [42] USB OTG FS Wakeup through EXTI line interrupt */
|
||||
(void*) isr_tim8_brk_tim12, /* [43] TIM8 Break Interrupt and TIM12 global interrupt */
|
||||
(void*) isr_tim8_up_tim13, /* [44] TIM8 Update Interrupt and TIM13 global interrupt */
|
||||
(void*) isr_tim8_trg_com_tim14, /* [45] TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
|
||||
(void*) isr_tim8_cc, /* [46] TIM8 Capture Compare Interrupt */
|
||||
(void*) isr_dma1_stream7, /* [47] DMA1 Stream7 Interrupt */
|
||||
(void*) isr_fmc, /* [48] FMC global Interrupt */
|
||||
(void*) isr_sdmmc1, /* [49] SDMMC1 global Interrupt */
|
||||
(void*) isr_tim5, /* [50] TIM5 global Interrupt */
|
||||
(void*) isr_spi3, /* [51] SPI3 global Interrupt */
|
||||
(void*) isr_uart4, /* [52] UART4 global Interrupt */
|
||||
(void*) isr_uart5, /* [53] UART5 global Interrupt */
|
||||
(void*) isr_tim6_dac, /* [54] TIM6 global and DAC1&2 underrun error interrupts */
|
||||
(void*) isr_tim7, /* [55] TIM7 global interrupt */
|
||||
(void*) isr_dma2_stream0, /* [56] DMA2 Stream 0 global Interrupt */
|
||||
(void*) isr_dma2_stream1, /* [57] DMA2 Stream 1 global Interrupt */
|
||||
(void*) isr_dma2_stream2, /* [58] DMA2 Stream 2 global Interrupt */
|
||||
(void*) isr_dma2_stream3, /* [59] DMA2 Stream 3 global Interrupt */
|
||||
(void*) isr_dma2_stream4, /* [60] DMA2 Stream 4 global Interrupt */
|
||||
(void*) isr_eth, /* [61] Ethernet global Interrupt */
|
||||
(void*) isr_eth_wkup, /* [62] Ethernet Wakeup through EXTI line Interrupt */
|
||||
(void*) isr_can2_tx, /* [63] CAN2 TX Interrupt */
|
||||
(void*) isr_can2_rx0, /* [64] CAN2 RX0 Interrupt */
|
||||
(void*) isr_can2_rx1, /* [65] CAN2 RX1 Interrupt */
|
||||
(void*) isr_can2_sce, /* [66] CAN2 SCE Interrupt */
|
||||
(void*) isr_otg_fs, /* [67] USB OTG FS global Interrupt */
|
||||
(void*) isr_dma2_stream5, /* [68] DMA2 Stream 5 global interrupt */
|
||||
(void*) isr_dma2_stream6, /* [69] DMA2 Stream 6 global interrupt */
|
||||
(void*) isr_dma2_stream7, /* [70] DMA2 Stream 7 global interrupt */
|
||||
(void*) isr_usart6, /* [71] USART6 global interrupt */
|
||||
(void*) isr_i2c3_ev, /* [72] I2C3 event interrupt */
|
||||
(void*) isr_i2c3_er, /* [73] I2C3 error interrupt */
|
||||
(void*) isr_otg_hs_ep1_out, /* [74] USB OTG HS End Point 1 Out global interrupt */
|
||||
(void*) isr_otg_hs_ep1_in, /* [75] USB OTG HS End Point 1 In global interrupt */
|
||||
(void*) isr_otg_hs_wkup, /* [76] USB OTG HS Wakeup through EXTI interrupt */
|
||||
(void*) isr_otg_hs, /* [77] USB OTG HS global interrupt */
|
||||
#if defined(CPU_MODEL_STM32F722ZE)
|
||||
(void*) (0UL), /* [78] Reserved */
|
||||
(void*) (0UL), /* [79] Reserved */
|
||||
(void*) isr_rng, /* [80] RNG global interrupt */
|
||||
(void*) isr_fpu, /* [81] FPU global interrupt */
|
||||
(void*) isr_uart7, /* [82] UART7 global interrupt */
|
||||
(void*) isr_uart8, /* [83] UART8 global interrupt */
|
||||
(void*) isr_spi4, /* [84] SPI4 global Interrupt */
|
||||
(void*) isr_spi5, /* [85] SPI5 global Interrupt */
|
||||
(void*) (0UL), /* [86] Reserved */
|
||||
(void*) isr_sai1, /* [87] SAI1 global Interrupt */
|
||||
(void*) (0UL), /* [88] Reserved */
|
||||
(void*) (0UL), /* [89] Reserved */
|
||||
(void*) (0UL), /* [90] Reserved */
|
||||
(void*) isr_sai2, /* [91] SAI2 global Interrupt */
|
||||
(void*) isr_quadspi, /* [92] Quad SPI global interrupt */
|
||||
(void*) isr_lptim1, /* [93] LP TIM1 interrupt */
|
||||
(void*) (0UL), /* [94] Reserved */
|
||||
(void*) (0UL), /* [95] Reserved */
|
||||
(void*) (0UL), /* [96] Reserved */
|
||||
(void*) (0UL), /* [97] Reserved */
|
||||
(void*) (0UL), /* [98] Reserved */
|
||||
(void*) (0UL), /* [99] Reserved */
|
||||
(void*) (0UL), /* [100] Reserved */
|
||||
(void*) (0UL), /* [101] Reserved */
|
||||
(void*) (0UL), /* [102] Reserved */
|
||||
(void*) isr_sdmmc2, /* [103] SDMMC2 global Interrup */
|
||||
#else
|
||||
(void*) isr_dcmi, /* [78] DCMI global interrupt */
|
||||
(void*) (0UL), /* [79] Reserved */
|
||||
(void*) isr_rng, /* [80] RNG global interrupt */
|
||||
(void*) isr_fpu, /* [81] FPU global interrupt */
|
||||
(void*) isr_uart7, /* [82] UART7 global interrupt */
|
||||
(void*) isr_uart8, /* [83] UART8 global interrupt */
|
||||
(void*) isr_spi4, /* [84] SPI4 global Interrupt */
|
||||
(void*) isr_spi5, /* [85] SPI5 global Interrupt */
|
||||
(void*) isr_spi6, /* [86] SPI6 global Interrupt */
|
||||
(void*) isr_sai1, /* [87] SAI1 global Interrupt */
|
||||
(void*) isr_ltdc, /* [88] LTDC global Interrupt */
|
||||
(void*) isr_ltdc_er, /* [89] LTDC Error global Interrupt */
|
||||
(void*) isr_dma2d, /* [90] DMA2D global Interrupt */
|
||||
(void*) isr_sai2, /* [91] SAI2 global Interrupt */
|
||||
(void*) isr_quadspi, /* [92] Quad SPI global interrupt */
|
||||
(void*) isr_lptim1, /* [93] LP TIM1 interrupt */
|
||||
(void*) isr_cec, /* [94] HDMI-CEC global Interrupt */
|
||||
(void*) isr_i2c4_ev, /* [95] I2C4 Event Interrupt */
|
||||
(void*) isr_i2c4_er, /* [96] I2C4 Error Interrupt */
|
||||
(void*) isr_spdif_rx, /* [97] SPDIF-RX global Interrupt */
|
||||
#if defined(CPU_MODEL_STM32F769NI)
|
||||
(void*) isr_dsi,
|
||||
(void*) isr_dsi, /* [98] DSI global Interrupt */
|
||||
#elif defined(CPU_MODEL_STM32F767ZI)
|
||||
(void*) (0UL),
|
||||
(void*) (0UL), /* [98] Reserved */
|
||||
#endif
|
||||
#if defined(CPU_MODEL_STM32F769NI) || defined(CPU_MODEL_STM32F767ZI)
|
||||
(void*) isr_dfsdm1_flt0,
|
||||
(void*) isr_dfsdm1_flt1,
|
||||
(void*) isr_dfsdm1_flt2,
|
||||
(void*) isr_dfsdm1_flt3,
|
||||
(void*) isr_sdmmc2,
|
||||
(void*) isr_can3_tx,
|
||||
(void*) isr_can3_rx0,
|
||||
(void*) isr_can3_rx1,
|
||||
(void*) isr_can3_sce,
|
||||
(void*) isr_jpeg,
|
||||
(void*) isr_mdios,
|
||||
(void*) isr_dfsdm1_flt0, /* [99] DFSDM1 Filter 0 global Interrupt */
|
||||
(void*) isr_dfsdm1_flt1, /* [100] DFSDM1 Filter 1 global Interrupt */
|
||||
(void*) isr_dfsdm1_flt2, /* [101] DFSDM1 Filter 2 global Interrupt */
|
||||
(void*) isr_dfsdm1_flt3, /* [102] DFSDM1 Filter 3 global Interrupt */
|
||||
(void*) isr_sdmmc2, /* [103] SDMMC2 global Interrup */
|
||||
(void*) isr_can3_tx, /* [104] CAN3 TX Interrupt */
|
||||
(void*) isr_can3_rx0, /* [105] CAN3 RX0 Interrupt */
|
||||
(void*) isr_can3_rx1, /* [106] CAN3 RX1 Interrupt */
|
||||
(void*) isr_can3_sce, /* [107] CAN3 SCE Interrupt */
|
||||
(void*) isr_jpeg, /* [108] JPEG global Interrupt */
|
||||
(void*) isr_mdios, /* [109] MDIO Slave global Interrupt */
|
||||
#endif
|
||||
#endif
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user