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cpu/stm32f4: adapted to centralized cpu conf
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@ -21,10 +21,6 @@
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#include "cpu.h"
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#include "periph_conf.h"
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/**
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* @name Pattern to write into the Coprocessor Access Control Register to allow full FPU access
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*/
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#define FULL_FPU_ACCESS (0x00f00000)
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static void cpu_clock_init(void);
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@ -34,17 +30,10 @@ static void cpu_clock_init(void);
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*/
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void cpu_init(void)
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{
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/* give full access to the FPU */
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SCB->CPACR |= (uint32_t)FULL_FPU_ACCESS;
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/* configure the vector table location to internal flash */
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SCB->VTOR = FLASH_BASE;
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/* initialize the Cortex-M core */
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cortexm_init();
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/* initialize the clock system */
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cpu_clock_init();
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/* set pendSV interrupt to lowest possible priority */
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NVIC_SetPriority(PendSV_IRQn, 0xff);
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}
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/**
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@ -21,36 +21,23 @@
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#ifndef __CPU_CONF_H
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#define __CPU_CONF_H
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#ifdef CPU_MODEL_STM32F407VG
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#if defined(CPU_MODEL_STM32F407VG)
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#include "stm32f407xx.h"
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#elif defined CPU_MODEL_STM32F415RG
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#elif defined(CPU_MODEL_STM32F415RG)
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#include "stm32f415xx.h"
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#endif
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/**
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* @name Kernel configuration
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*
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* TODO: measure and adjust for the Cortex-M4f
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* @{
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*/
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#define THREAD_EXTRA_STACKSIZE_PRINTF (2500)
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#ifndef THREAD_STACKSIZE_DEFAULT
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#define THREAD_STACKSIZE_DEFAULT (2500)
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define THREAD_STACKSIZE_IDLE (512)
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/** @} */
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/**
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* @name UART0 buffer size definition for compatibility reasons
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*
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* TODO: remove once the remodeling of the uart0 driver is done
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* @brief ARM Cortex-M specific CPU configuration
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* @{
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*/
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#ifndef UART0_BUFSIZE
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#define UART0_BUFSIZE (128)
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#endif
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#define CPU_DEFAULT_IRQ_PRIO (1U)
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#define CPU_IRQ_NUMOF (82U)
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#define CPU_FLASH_BASE FLASH_BASE
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/** @} */
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/**
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@ -68,10 +55,6 @@
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#endif
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/** @} */
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef __cplusplus
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}
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#endif
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