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Merge pull request #6568 from haukepetersen/opt_periph_uarttxonly

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periph/uart: enable to run UART in TX only mode
This commit is contained in:
Alexandre Abadie 2017-02-24 13:01:38 +01:00 committed by GitHub
commit 79b2fd89bb
5 changed files with 65 additions and 28 deletions
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16
cpu/atmega_common/periph/uart.c
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@ -36,19 +36,20 @@
/**
* @brief Maximum percentage error in calculated baud before switching to double speed transmission (U2X)
* @brief Maximum percentage error in calculated baud before switching to
* double speed transmission (U2X)
*
* Takes whole numbers from 0 to 100, inclusive, with a default of 2.
*/
#if defined(UART_BAUD_TOL)
// BAUD_TOL is defined here as it is used by the setbaud.h utility
/* BAUD_TOL is defined here as it is used by the setbaud.h utility */
#define BAUD_TOL UART_BAUD_TOL
#else
#define BAUD_TOL 2
#endif
#if defined(UART_STDIO_BAUDRATE)
// BAUD and F_CPU are required by setbaud.h to calculated BRR
/* BAUD and F_CPU are required by setbaud.h to calculated BRR */
#define BAUD UART_STDIO_BAUDRATE
#define F_CPU CLOCK_CORECLOCK
#include <util/setbaud.h>
@ -129,8 +130,15 @@ int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
dev[uart]->CSRC = (1 << UCSZ00) | (1 << UCSZ01);
/* set clock divider */
_set_brr(uart, baudrate);
/* enable RX and TX and the RX interrupt */
dev[uart]->CSRB = ((1 << RXCIE0) | (1 << RXEN0) | (1 << TXEN0));
if (rx_cb) {
dev[uart]->CSRB = ((1 << RXCIE0) | (1 << RXEN0) | (1 << TXEN0));
}
else {
dev[uart]->CSRB = (1 << TXEN0);
}
return UART_OK;
}

28
cpu/ezr32wg/periph/uart.c
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@ -65,16 +65,26 @@ int uart_init(uart_t dev, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
* the division afterwards... */
uart->CLKDIV = (((CLOCK_HFPERCLK << 5) / (16 * baudrate) - 32) << 3);
/* configure the pins */
gpio_init(uart_config[dev].rx_pin, GPIO_IN);
gpio_init(uart_config[dev].tx_pin, GPIO_OUT);
uart->ROUTE = ((uart_config[dev].loc << _USART_ROUTE_LOCATION_SHIFT) |
USART_ROUTE_RXPEN | USART_ROUTE_TXPEN);
/* enable RX interrupt */
NVIC_EnableIRQ(uart_config[dev].irq);
NVIC_EnableIRQ(uart_config[dev].irq + 1);
uart->IEN |= USART_IEN_RXDATAV;
/* enable receiver and transmitter */
uart->CMD = USART_CMD_TXEN | USART_CMD_RXEN;
if (rx_cb) {
gpio_init(uart_config[dev].rx_pin, GPIO_IN);
uart->ROUTE = ((uart_config[dev].loc << _USART_ROUTE_LOCATION_SHIFT) |
USART_ROUTE_RXPEN | USART_ROUTE_TXPEN);
} else {
uart->ROUTE = ((uart_config[dev].loc << _USART_ROUTE_LOCATION_SHIFT) |
USART_ROUTE_TXPEN);
}
if (rx_cb) {
/* enable RX interrupt */
NVIC_EnableIRQ(uart_config[dev].irq);
NVIC_EnableIRQ(uart_config[dev].irq + 1);
uart->IEN |= USART_IEN_RXDATAV;
/* enable receiver and transmitter */
uart->CMD = USART_CMD_TXEN | USART_CMD_RXEN;
}
else {
uart->CMD = USART_CMD_TXEN;
}
return UART_OK;
}

28
cpu/nrf5x_common/periph/uart.c
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@ -1,5 +1,5 @@
/*
* Copyright (C) 2014-2016 Freie Universität Berlin
* Copyright (C) 2014-2017 Freie Universität Berlin
* 2015 Jan Wagner <mail@jwagner.eu>
*
*
@ -50,14 +50,20 @@ int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
/* power on the UART device */
NRF_UART0->POWER = 1;
#endif
/* reset configuration registers */
NRF_UART0->CONFIG = 0;
/* configure RX/TX pin modes */
/* configure RX pin */
if (rx_cb) {
GPIO_BASE->DIRCLR = (1 << UART_PIN_RX);
NRF_UART0->PSELRXD = UART_PIN_RX;
}
/* configure TX pin */
GPIO_BASE->DIRSET = (1 << UART_PIN_TX);
GPIO_BASE->DIRCLR = (1 << UART_PIN_RX);
/* configure UART pins to use */
NRF_UART0->PSELTXD = UART_PIN_TX;
NRF_UART0->PSELRXD = UART_PIN_RX;
/* enable HW-flow control if defined */
#if UART_HWFLOWCTRL
/* set pin mode for RTS and CTS pins */
@ -127,10 +133,14 @@ int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
NRF_UART0->ENABLE = UART_ENABLE_ENABLE_Enabled;
/* enable TX and RX */
NRF_UART0->TASKS_STARTTX = 1;
NRF_UART0->TASKS_STARTRX = 1;
/* enable global and receiving interrupt */
NVIC_EnableIRQ(UART_IRQN);
NRF_UART0->INTENSET = UART_INTENSET_RXDRDY_Msk;
if (rx_cb) {
NRF_UART0->TASKS_STARTRX = 1;
/* enable global and receiving interrupt */
NVIC_EnableIRQ(UART_IRQN);
NRF_UART0->INTENSET = UART_INTENSET_RXDRDY_Msk;
}
return UART_OK;
}

15
cpu/stm32_common/periph/uart.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (C) 2014-2016 Freie Universität Berlin
* Copyright (C) 2014-2017 Freie Universität Berlin
* Copyright (C) 2016 OTA keys
*
* This file is subject to the terms and conditions of the GNU Lesser
@ -8,7 +8,7 @@
*/
/**
* @ingroup cpu_stm32f2
* @ingroup cpu_stm32_common
* @{
*
* @file
@ -56,8 +56,7 @@ int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
isr_ctx[uart].rx_cb = rx_cb;
isr_ctx[uart].arg = arg;
/* configure RX and TX pin */
gpio_init(uart_config[uart].rx_pin, GPIO_IN);
/* configure TX pin */
gpio_init(uart_config[uart].tx_pin, GPIO_OUT);
/* set TX pin high to avoid garbage during further initialization */
gpio_set(uart_config[uart].tx_pin);
@ -65,8 +64,14 @@ int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
gpio_init_af(uart_config[uart].tx_pin, GPIO_AF_OUT_PP);
#else
gpio_init_af(uart_config[uart].tx_pin, uart_config[uart].tx_af);
gpio_init_af(uart_config[uart].rx_pin, uart_config[uart].rx_af);
#endif
/* configure RX pin */
if (rx_cb) {
gpio_init(uart_config[uart].rx_pin, GPIO_IN);
#ifndef CPU_FAM_STM32F1
gpio_init_af(uart_config[uart].rx_pin, uart_config[uart].rx_af);
#endif
}
/* enable the clock */
periph_clk_en(uart_config[uart].bus, uart_config[uart].rcc_mask);

6
drivers/include/periph/uart.h
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@ -124,10 +124,14 @@ enum {
* - 1 stop bit
* - baudrate as given
*
* If no callback parameter is given (rx_cb := NULL), the UART will be
* initialized in TX only mode.
*
* @param[in] uart UART device to initialize
* @param[in] baudrate desired baudrate in baud/s
* @param[in] rx_cb receive callback, executed in interrupt context once
* for every byte that is received (RX buffer filled)
* for every byte that is received (RX buffer filled),
* set to NULL for TX only mode
* @param[in] arg optional context passed to the callback functions
*
* @return UART_OK on success