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https://github.com/RIOT-OS/RIOT.git
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stm32f2: add adc and lpm
changes taken from DipSwitch's board: EMW3162 #4498 PR. - Adds a functional implementation of the ADC - Implements low power mode
This commit is contained in:
Toon Stegen
parent
7a0e81923b
commit
77c9ee043f
@ -152,6 +152,11 @@ typedef struct {
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} uart_conf_t;
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/** @} */
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/**
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* @brief Available number of ADC devices
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*/
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#define ADC_DEVS (2U)
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/**
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* @brief ADC channel configuration data
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*/
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@ -161,6 +166,21 @@ typedef struct {
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uint8_t chan; /**< CPU ADC channel connected to the pin */
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} adc_conf_t;
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/**
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* @brief Override the ADC resolution configuration
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* @{
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*/
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#define HAVE_ADC_RES_T
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typedef enum {
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ADC_RES_6BIT = 0x03000000, /**< ADC resolution: 6 bit */
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ADC_RES_8BIT = 0x02000000, /**< ADC resolution: 8 bit */
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ADC_RES_10BIT = 0x01000000, /**< ADC resolution: 10 bit */
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ADC_RES_12BIT = 0x00000000, /**< ADC resolution: 12 bit */
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ADC_RES_14BIT = 1, /**< ADC resolution: 14 bit (not supported) */
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ADC_RES_16BIT = 2 /**< ADC resolution: 16 bit (not supported)*/
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} adc_res_t;
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/** @} */
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/**
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* @brief DAC line configuration data
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*/
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@ -179,6 +199,13 @@ typedef struct {
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*/
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void gpio_init_af(gpio_t pin, gpio_af_t af);
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/**
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* @brief Configure the given pin to be used as ADC input
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*
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* @param[in] pin pin to configure
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*/
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void gpio_init_analog(gpio_t pin);
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/**
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* @brief Power on the DMA device the given stream belongs to
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*
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@ -34,14 +34,41 @@ enum lpm_mode lpm_arch_set(enum lpm_mode target)
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switch (target) {
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case LPM_ON: /* STM Run mode */
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current_mode = LPM_ON;
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break;
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case LPM_IDLE: /* STM Sleep mode */
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current_mode = LPM_IDLE;
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/* Reset SLEEPDEEP bit of system control block */
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SCB->SCR &= ~(SCB_SCR_SLEEPDEEP_Msk);
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/* Enter sleep mode */
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__WFI();
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break;
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case LPM_SLEEP: /* STM Stop mode */
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current_mode = LPM_SLEEP;
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/* Clear PDDS and LPDS bits to enter stop mode on */
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/* deepsleep with voltage regulator on */
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PWR->CR &= ~(PWR_CR_PDDS | PWR_CR_LPDS);
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/* Set SLEEPDEEP bit of system control block */
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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/* Enter stop mode */
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__WFI();
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break;
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case LPM_POWERDOWN: /* STM Standby mode */
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/* Fall-through */
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case LPM_OFF: /* STM Standby mode */
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current_mode = LPM_POWERDOWN;
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/* Set PDDS to enter standby mode on deepsleep and clear flags */
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PWR->CR |= (PWR_CR_PDDS | PWR_CR_CWUF | PWR_CR_CSBF);
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/* Enable WKUP pin to use for wakeup from standby mode */
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PWR->CSR |= PWR_CSR_EWUP;
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/* Set SLEEPDEEP bit of system control block */
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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#if defined ( __CC_ARM )
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/* Ensure that store operations are completed */
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__force_stores();
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#endif
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/* Enter standby mode */
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__WFI();
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break;
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default:
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break;
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@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2015 Engineering-Spirit
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* Copyright (C) 2016 Engineering-Spirit
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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@ -13,173 +13,126 @@
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* @file
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* @brief Low-level ADC driver implementation
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Nick v. IJzendoorn <nijzendoorn@engineering-spirit.nl>
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*
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* @}
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*/
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#include "cpu.h"
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#include "mutex.h"
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#include "periph/adc.h"
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#include "periph_conf.h"
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/* guard in case that no ADC device is defined */
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#if ADC_NUMOF
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/**
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* @brief Maximum allowed ADC clock speed
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*/
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#define MAX_ADC_SPEED (12000000U)
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typedef struct {
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int max_value;
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} adc_config_t;
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/**
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* @brief Load the ADC configuration
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* @{
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*/
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#ifdef ADC_CONFIG
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static const adc_conf_t adc_config[] = ADC_CONFIG;
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#else
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static const adc_conf_t adc_config[] = {};
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#endif
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adc_config_t adc_config[ADC_NUMOF];
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/**
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* @brief Allocate locks for all three available ADC devices
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*/
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static mutex_t locks[] = {
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#if ADC_DEVS > 1
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MUTEX_INIT,
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#endif
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#if ADC_DEVS > 2
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MUTEX_INIT,
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#endif
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MUTEX_INIT
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};
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int adc_init(adc_t dev, adc_precision_t precision)
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static inline ADC_TypeDef *dev(adc_t line)
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{
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ADC_TypeDef *adc = 0;
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return (ADC_TypeDef *)(ADC1_BASE + (adc_config[line].dev << 8));
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}
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adc_poweron(dev);
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static inline void prep(adc_t line)
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{
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mutex_lock(&locks[adc_config[line].dev]);
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RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN << adc_config[line].dev);
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}
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switch (dev) {
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#if ADC_0_EN
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case ADC_0:
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adc = ADC_0_DEV;
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ADC_0_PORT_CLKEN();
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ADC_0_PORT->MODER |= (3 << (ADC_0_CH0_PIN * 2) | 3 << (ADC_0_CH1_PIN * 2));
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break;
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#endif
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#if ADC_1_EN
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case ADC_1:
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adc = ADC_1_DEV;
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ADC_1_PORT_CLKEN();
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ADC_1_PORT->MODER |= (3 << (ADC_1_CH0_PIN * 2) | 3 << (ADC_1_CH1_PIN * 2));
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break;
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#endif
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default:
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return -1;
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static inline void done(adc_t line)
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{
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RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN << adc_config[line].dev);
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mutex_unlock(&locks[adc_config[line].dev]);
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}
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int adc_init(adc_t line)
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{
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uint32_t clk_div = 2;
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/* check if the line is valid */
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if (line >= ADC_NUMOF) {
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return -1;
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}
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/* reset control registers */
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adc->CR1 = 0;
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adc->CR2 = 0;
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adc->SQR1 = 0;
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/* lock and power-on the device */
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prep(line);
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/* set precision */
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switch (precision) {
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case ADC_RES_6BIT:
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adc->CR1 |= ADC_CR1_RES_0 | ADC_CR1_RES_1;
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adc_config[dev].max_value = 0x3f;
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break;
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case ADC_RES_8BIT:
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adc->CR1 |= ADC_CR1_RES_1;
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adc_config[dev].max_value = 0xff;
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break;
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case ADC_RES_10BIT:
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adc->CR1 |= ADC_CR1_RES_0;
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adc_config[dev].max_value = 0x3ff;
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break;
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case ADC_RES_12BIT:
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adc_config[dev].max_value = 0xfff;
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break;
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case ADC_RES_14BIT:
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case ADC_RES_16BIT:
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adc_poweroff(dev);
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return -1;
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/* configure the pin */
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gpio_init_analog(adc_config[line].pin);
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/* set clock prescaler to get the maximal possible ADC clock value */
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for (clk_div = 2; clk_div < 8; clk_div += 2) {
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if ((CLOCK_CORECLOCK / clk_div) <= MAX_ADC_SPEED) {
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break;
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}
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}
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/* set clock prescaler */
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ADC->CCR = (3 << 16); /* ADC clock = 10,5MHz */
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ADC->CCR = ((clk_div / 2) - 1) << 16;
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/* enable the ADC module */
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adc->CR2 |= ADC_CR2_ADON;
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dev(line)->CR2 = ADC_CR2_ADON;
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/* check if this channel is an internal ADC channel, if so
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* enable the internal temperature and Vref */
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if (adc_config[line].chan == 16 || adc_config[line].chan == 17) {
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/* check if the internal channels are configured to use ADC1 */
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if (dev(line) != ADC1) {
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return -3;
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}
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ADC->CCR |= ADC_CCR_TSVREFE;
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}
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/* free the device again */
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done(line);
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return 0;
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}
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int adc_sample(adc_t dev, int channel)
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int adc_sample(adc_t line, adc_res_t res)
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{
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ADC_TypeDef *adc = 0;
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int sample;
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switch (dev) {
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#if ADC_0_EN
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case ADC_0:
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adc = ADC_0_DEV;
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switch (channel) {
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case 0:
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adc->SQR3 = ADC_0_CH0 & 0x1f;
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break;
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case 1:
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adc->SQR3 = ADC_0_CH1 & 0x1f;
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break;
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default:
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return -1;
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}
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break;
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#endif
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#if ADC_1_EN
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case ADC_1:
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adc = ADC_1_DEV;
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switch (channel) {
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case 0:
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adc->SQR3 = ADC_1_CH0 & 0x1f;
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break;
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case 1:
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adc->SQR3 = ADC_1_CH1 & 0x1f;
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break;
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default:
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return -1;
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}
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break;
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#endif
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/* check if resolution is applicable */
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if (res < 0xff) {
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return -1;
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}
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/* start single conversion */
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adc->CR2 |= ADC_CR2_SWSTART;
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/* wait until conversion is complete */
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while (!(adc->SR & ADC_SR_EOC));
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/* read and return result */
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return (int)adc->DR;
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}
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/* lock and power on the ADC device */
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prep(line);
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void adc_poweron(adc_t dev)
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{
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switch (dev) {
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#if ADC_0_EN
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case ADC_0:
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ADC_0_CLKEN();
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break;
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#endif
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#if ADC_1_EN
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case ADC_1:
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ADC_1_CLKEN();
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break;
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#endif
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}
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}
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/* set resolution and conversion channel */
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dev(line)->CR1 = res;
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dev(line)->SQR3 = adc_config[line].chan;
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/* start conversion and wait for results */
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dev(line)->CR2 |= ADC_CR2_SWSTART;
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while (!(dev(line)->SR & ADC_SR_EOC)) {}
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/* finally read sample and reset the STRT bit in the status register */
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sample = (int)dev(line)->DR;
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void adc_poweroff(adc_t dev)
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{
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switch (dev) {
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#if ADC_0_EN
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case ADC_0:
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ADC_0_CLKDIS();
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break;
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#endif
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#if ADC_1_EN
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case ADC_1:
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ADC_1_CLKDIS();
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break;
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#endif
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}
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}
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/* power off and unlock device again */
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done(line);
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int adc_map(adc_t dev, int value, int min, int max)
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{
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return (int)adc_mapf(dev, value, (float)min, (float)max);
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return sample;
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}
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float adc_mapf(adc_t dev, int value, float min, float max)
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{
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return ((max - min) / ((float)adc_config[dev].max_value)) * value;
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}
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#endif /* ADC_NUMOF */
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